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-rw-r--r--include/asm-mips/bootinfo.h10
-rw-r--r--include/asm-mips/galileo-boards/ev96100.h55
-rw-r--r--include/asm-mips/galileo-boards/ev96100int.h12
-rw-r--r--include/asm-mips/galileo-boards/gt64120.h320
-rw-r--r--include/asm-mips/galileo-boards/gt96100.h432
-rw-r--r--include/asm-mips/io.h52
-rw-r--r--include/asm-mips/serial.h15
7 files changed, 894 insertions, 2 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 447192b20..4084ba601 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -23,9 +23,10 @@
#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */
#define MACH_GROUP_BAGET 9 /* Baget */
#define MACH_GROUP_ORION 10 /* CoSine Orion */
+#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards*/
#define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \
- "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion" }
+ "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" }
/*
* Valid machtype values for group unknown (low order halfword of mips_machtype)
@@ -115,6 +116,13 @@
#define GROUP_BAGET_NAMES { "BT23-201", "BT23-202" }
/*
+ * Valid machtype for group GALILEO
+ */
+#define MACH_EV96100 0 /* EV96100 */
+
+#define GROUP_GALILEO_NAMES { "EV96100" }
+
+/*
* Valid cputype values
*/
#define CPU_UNKNOWN 0
diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h
new file mode 100644
index 000000000..92a34cf7e
--- /dev/null
+++ b/include/asm-mips/galileo-boards/ev96100.h
@@ -0,0 +1,55 @@
+/*
+ *
+ */
+#ifndef _MIPS_EV96100_H
+#define _MIPS_EV96100_H
+
+#include <asm/addrspace.h>
+
+/*
+ * GT64120 config space base address
+ */
+#define GT64120_BASE (KSEG1ADDR(0x14000000))
+#define MIPS_GT_BASE GT64120_BASE
+
+/*
+ * PCI Bus allocation
+ */
+#define GT_PCI_MEM_BASE 0x12000000
+#define GT_PCI_MEM_SIZE 0x02000000
+#define GT_PCI_IO_BASE 0x10000000
+#define GT_PCI_IO_SIZE 0x02000000
+#define GT_ISA_IO_BASE PCI_IO_BASE
+
+/*
+ * Duart I/O ports.
+ */
+#define EV96100_COM1_BASE_ADDR (0x1d000000 + 0x20)
+#define EV96100_COM2_BASE_ADDR (0x1d000000 + 0x00)
+
+
+/*
+ * EV96100 interrupt controller register base.
+ */
+#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
+
+/*
+ * EV96100 UART register base.
+ */
+#define EV96100_UART0_REGS_BASE (KSEG1ADDR(EV96100_COM1_BASE_ADDR))
+#define EV96100_UART1_REGS_BASE (KSEG1ADDR(EV96100_COM2_BASE_ADDR))
+#define EV96100_BASE_BAUD ( 3686400 / 16 )
+
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the
+ * bytes when running bigendian.
+ */
+
+#define GT_WRITE(ofs, data) \
+ *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
+#define GT_READ(ofs, data) \
+ data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
+
+
+#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/ev96100int.h b/include/asm-mips/galileo-boards/ev96100int.h
new file mode 100644
index 000000000..47d0016bb
--- /dev/null
+++ b/include/asm-mips/galileo-boards/ev96100int.h
@@ -0,0 +1,12 @@
+/*
+ *
+ */
+#ifndef _MIPS_EV96100INT_H
+#define _MIPS_EV96100INT_H
+
+#define EV96100INT_UART_0 6 /* IP 6 */
+#define EV96100INT_TIMER 7 /* IP 7 */
+
+extern void ev96100int_init(void);
+
+#endif /* !(_MIPS_EV96100_H) */
diff --git a/include/asm-mips/galileo-boards/gt64120.h b/include/asm-mips/galileo-boards/gt64120.h
new file mode 100644
index 000000000..c2229af97
--- /dev/null
+++ b/include/asm-mips/galileo-boards/gt64120.h
@@ -0,0 +1,320 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for Galileo 64120 system controller.
+ *
+ */
+#ifndef GT64120_H
+#define GT64120_H
+
+#define MSK(n) ((1 << (n)) - 1)
+
+/************************************************************************
+ * Register offset addresses
+ ************************************************************************/
+
+#define GT_CPU_OFS 0x000
+
+#define GT_INTRCAUSE_OFS 0xc18
+#define GT_PCI0_CFGADDR_OFS 0xcf8
+#define GT_PCI0_CFGDATA_OFS 0xcfc
+#define GT_SDRAM_BM_OFS 0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+#define GT_SDRAM_B0_OFS 0x44c
+#define GT_SDRAM_B2_OFS 0x454
+#define GT_SDRAM_CFG_OFS 0x448
+#define GT_SDRAM_OPMODE_OFS 0x474
+
+#define GT_ISD_OFS 0x068
+
+#define GT_SCS10LD_OFS 0x008
+#define GT_SCS10HD_OFS 0x010
+#define GT_SCS32LD_OFS 0x018
+#define GT_SCS32HD_OFS 0x020
+#define GT_CS20LD_OFS 0x028
+#define GT_CS20HD_OFS 0x030
+#define GT_CS3BOOTLD_OFS 0x038
+#define GT_CS3BOOTHD_OFS 0x040
+#define GT_PCI0IOLD_OFS 0x048
+#define GT_PCI0IOHD_OFS 0x050
+#define GT_PCI0M0LD_OFS 0x058
+#define GT_PCI0M0HD_OFS 0x060
+#define GT_PCI0M1LD_OFS 0x080
+#define GT_PCI0M1HD_OFS 0x088
+#define GT_PCI1IOLD_OFS 0x090
+#define GT_PCI1IOHD_OFS 0x098
+#define GT_PCI1M0LD_OFS 0x0a0
+#define GT_PCI1M0HD_OFS 0x0a8
+#define GT_PCI1M1LD_OFS 0x0b0
+#define GT_PCI1M1HD_OFS 0x0b8
+
+#define GT_SCS0LD_OFS 0x400
+#define GT_SCS0HD_OFS 0x404
+#define GT_SCS1LD_OFS 0x408
+#define GT_SCS1HD_OFS 0x40c
+#define GT_SCS2LD_OFS 0x410
+#define GT_SCS2HD_OFS 0x414
+#define GT_SCS3LD_OFS 0x418
+#define GT_SCS3HD_OFS 0x41c
+#define GT_CS0LD_OFS 0x420
+#define GT_CS0HD_OFS 0x424
+#define GT_CS1LD_OFS 0x428
+#define GT_CS1HD_OFS 0x42c
+#define GT_CS2LD_OFS 0x430
+#define GT_CS2HD_OFS 0x434
+#define GT_CS3LD_OFS 0x438
+#define GT_CS3HD_OFS 0x43c
+#define GT_BOOTLD_OFS 0x440
+#define GT_BOOTHD_OFS 0x444
+
+#define GT_PCI0_BS_SCS10_OFS 0Xc08
+#define GT_PCI0_BS_SCS32_OFS 0xc0c
+#define GT_PCI0_BARE_OFS 0Xc3c
+
+#define GT_PCI0_TOR_OFS 0xc04
+
+#define GT_PCI0_IACK_OFS 0xc34
+
+
+/************************************************************************
+ * Register encodings
+ ************************************************************************/
+
+#define GT_CPU_WR_SHF 16
+#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX 0
+#define GT_CPU_WR_DDDD 1
+
+
+#define GT_CFGADDR_CFGEN_SHF 31
+#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF 16
+#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF 11
+#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF 8
+#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF 2
+#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF 2
+#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB 1
+#define GT_SDRAM_BM_ORDER_LIN 0
+
+#define GT_SDRAM_BM_RSVD_ALL1 0xFFB
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0 0
+#define GT_SDRAM_ADDRDECODE_ADDR_1 1
+#define GT_SDRAM_ADDRDECODE_ADDR_2 2
+#define GT_SDRAM_ADDRDECODE_ADDR_3 3
+#define GT_SDRAM_ADDRDECODE_ADDR_4 4
+#define GT_SDRAM_ADDRDECODE_ADDR_5 5
+#define GT_SDRAM_ADDRDECODE_ADDR_6 6
+#define GT_SDRAM_ADDRDECODE_ADDR_7 7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF 0
+#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2 1
+#define GT_SDRAM_B0_CASLAT_3 2
+
+#define GT_SDRAM_B0_FTDIS_SHF 2
+#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF 3
+#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2 0
+#define GT_SDRAM_B0_SRASPRCHG_3 1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF 4
+#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF 5
+#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2 0
+#define GT_SDRAM_B0_64BITINT_4 1
+
+#define GT_SDRAM_B0_BW_SHF 6
+#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32 0
+#define GT_SDRAM_B0_BW_64 1
+
+#define GT_SDRAM_B0_BLODD_SHF 7
+#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF 8
+#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF 9
+#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2 0
+#define GT_SDRAM_B0_SRAS2SCAS_3 1
+
+#define GT_SDRAM_B0_SIZE_SHF 11
+#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M 0
+#define GT_SDRAM_B0_SIZE_64M 1
+
+#define GT_SDRAM_B0_EXTPAR_SHF 12
+#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF 13
+#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8 0
+#define GT_SDRAM_B0_BLEN_4 1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF 0
+#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF 15
+#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF 19
+#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF 20
+#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF 21
+#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF 22
+#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF 0
+#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL 0
+#define GT_SDRAM_OPMODE_OP_NOP 1
+#define GT_SDRAM_OPMODE_OP_PRCHG 2
+#define GT_SDRAM_OPMODE_OP_MODE 3
+#define GT_SDRAM_OPMODE_OP_CBR 4
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF 3
+#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF 4
+#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF 6
+#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF 7
+#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF 8
+#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF 18
+#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF 19
+#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF 2
+#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+
+/************************************************************************
+ * Misc
+ ************************************************************************/
+
+#define GT_DEF_BASE 0x14000000
+#define GT_DEF_PCI0_MEM0_BASE 0x12000000
+#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
+#define GT_LATTIM_MIN 6 /* Minimum lat */
+
+#endif /* #ifndef GT64120_H */
diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h
new file mode 100644
index 000000000..4c48bd96c
--- /dev/null
+++ b/include/asm-mips/galileo-boards/gt96100.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or support@mvista.com
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register offsets of the MIPS GT96100 Advanced Communication Controller.
+ *
+ */
+#ifndef _GT96100_H
+#define _GT96100_H
+
+/*
+ * Galileo GT96100 internal register base.
+ */
+#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
+
+#define GT96100_WRITE(ofs, data) \
+ *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
+#define GT96100_READ(ofs) \
+ le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
+
+#define GT96100_ETH_IO_SIZE 0x4000
+
+/************************************************************************
+ * Register offset addresses follow
+ ************************************************************************/
+
+/* CPU Interface Control Registers */
+#define GT96100_CPU_INTERF_CONFIG 0x000000
+
+/* Ethernet Ports */
+#define GT96100_ETH_PHY_ADDR_REG 0x080800
+#define GT96100_ETH_SMI_REG 0x080810
+/*
+ These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
+ get offsets to port 1 registers.
+*/
+#define GT96100_ETH_PORT_CONFIG 0x084800
+#define GT96100_ETH_PORT_CONFIG_EXT 0x084808
+#define GT96100_ETH_PORT_COMM 0x084810
+#define GT96100_ETH_PORT_STATUS 0x084818
+#define GT96100_ETH_SER_PARAM 0x084820
+#define GT96100_ETH_HASH_TBL_PTR 0x084828
+#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830
+#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838
+#define GT96100_ETH_SDMA_CONFIG 0x084840
+#define GT96100_ETH_SDMA_COMM 0x084848
+#define GT96100_ETH_INT_CAUSE 0x084850
+#define GT96100_ETH_INT_MASK 0x084858
+#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880
+#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884
+#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888
+#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C
+#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0
+#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4
+#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8
+#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC
+#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0
+#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4
+#define GT96100_ETH_MIB_COUNT_BASE 0x085800
+
+/* SDMAs */
+#define GT96100_SDMA_GROUP_CONFIG 0x101AF0
+/* SDMA Group 0 */
+#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900
+#define GT96100_SDMA_G0_CHAN0_COMM 0x000908
+#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900
+#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910
+#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900
+#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910
+#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914
+#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900
+#define GT96100_SDMA_G0_CHAN1_COMM 0x010908
+#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900
+#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910
+#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900
+#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910
+#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914
+#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900
+#define GT96100_SDMA_G0_CHAN2_COMM 0x020908
+#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900
+#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910
+#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900
+#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910
+#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914
+#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900
+#define GT96100_SDMA_G0_CHAN3_COMM 0x030908
+#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900
+#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910
+#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900
+#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910
+#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914
+#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900
+#define GT96100_SDMA_G0_CHAN4_COMM 0x040908
+#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900
+#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910
+#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900
+#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910
+#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914
+#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900
+#define GT96100_SDMA_G0_CHAN5_COMM 0x050908
+#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900
+#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910
+#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900
+#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910
+#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914
+#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900
+#define GT96100_SDMA_G0_CHAN6_COMM 0x060908
+#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900
+#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910
+#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900
+#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910
+#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914
+#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900
+#define GT96100_SDMA_G0_CHAN7_COMM 0x070908
+#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900
+#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910
+#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900
+#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910
+#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914
+/* SDMA Group 1 */
+#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900
+#define GT96100_SDMA_G1_CHAN0_COMM 0x100908
+#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900
+#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910
+#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900
+#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910
+#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914
+#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900
+#define GT96100_SDMA_G1_CHAN1_COMM 0x110908
+#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900
+#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910
+#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900
+#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910
+#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914
+#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900
+#define GT96100_SDMA_G1_CHAN2_COMM 0x120908
+#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900
+#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910
+#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900
+#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910
+#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914
+#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900
+#define GT96100_SDMA_G1_CHAN3_COMM 0x130908
+#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900
+#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910
+#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900
+#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910
+#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914
+#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900
+#define GT96100_SDMA_G1_CHAN4_COMM 0x140908
+#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900
+#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910
+#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900
+#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910
+#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914
+#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900
+#define GT96100_SDMA_G1_CHAN5_COMM 0x150908
+#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900
+#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910
+#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900
+#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910
+#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914
+#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900
+#define GT96100_SDMA_G1_CHAN6_COMM 0x160908
+#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900
+#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910
+#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900
+#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910
+#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914
+#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900
+#define GT96100_SDMA_G1_CHAN7_COMM 0x170908
+#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900
+#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910
+#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900
+#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910
+#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914
+/* MPSCs */
+#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00
+#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04
+#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08
+#define GT96100_MPSC_CHAN0_REG1 0x000A0C
+#define GT96100_MPSC_CHAN0_REG2 0x000A10
+#define GT96100_MPSC_CHAN0_REG3 0x000A14
+#define GT96100_MPSC_CHAN0_REG4 0x000A18
+#define GT96100_MPSC_CHAN0_REG5 0x000A1C
+#define GT96100_MPSC_CHAN0_REG6 0x000A20
+#define GT96100_MPSC_CHAN0_REG7 0x000A24
+#define GT96100_MPSC_CHAN0_REG8 0x000A28
+#define GT96100_MPSC_CHAN0_REG9 0x000A2C
+#define GT96100_MPSC_CHAN0_REG10 0x000A30
+#define GT96100_MPSC_CHAN0_REG11 0x000A34
+#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00
+#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04
+#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08
+#define GT96100_MPSC_CHAN1_REG1 0x008A0C
+#define GT96100_MPSC_CHAN1_REG2 0x008A10
+#define GT96100_MPSC_CHAN1_REG3 0x008A14
+#define GT96100_MPSC_CHAN1_REG4 0x008A18
+#define GT96100_MPSC_CHAN1_REG5 0x008A1C
+#define GT96100_MPSC_CHAN1_REG6 0x008A20
+#define GT96100_MPSC_CHAN1_REG7 0x008A24
+#define GT96100_MPSC_CHAN1_REG8 0x008A28
+#define GT96100_MPSC_CHAN1_REG9 0x008A2C
+#define GT96100_MPSC_CHAN1_REG10 0x008A30
+#define GT96100_MPSC_CHAN1_REG11 0x008A34
+#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00
+#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04
+#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08
+#define GT96100_MPSC_CHAN2_REG1 0x010A0C
+#define GT96100_MPSC_CHAN2_REG2 0x010A10
+#define GT96100_MPSC_CHAN2_REG3 0x010A14
+#define GT96100_MPSC_CHAN2_REG4 0x010A18
+#define GT96100_MPSC_CHAN2_REG5 0x010A1C
+#define GT96100_MPSC_CHAN2_REG6 0x010A20
+#define GT96100_MPSC_CHAN2_REG7 0x010A24
+#define GT96100_MPSC_CHAN2_REG8 0x010A28
+#define GT96100_MPSC_CHAN2_REG9 0x010A2C
+#define GT96100_MPSC_CHAN2_REG10 0x010A30
+#define GT96100_MPSC_CHAN2_REG11 0x010A34
+#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00
+#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04
+#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08
+#define GT96100_MPSC_CHAN3_REG1 0x018A0C
+#define GT96100_MPSC_CHAN3_REG2 0x018A10
+#define GT96100_MPSC_CHAN3_REG3 0x018A14
+#define GT96100_MPSC_CHAN3_REG4 0x018A18
+#define GT96100_MPSC_CHAN3_REG5 0x018A1C
+#define GT96100_MPSC_CHAN3_REG6 0x018A20
+#define GT96100_MPSC_CHAN3_REG7 0x018A24
+#define GT96100_MPSC_CHAN3_REG8 0x018A28
+#define GT96100_MPSC_CHAN3_REG9 0x018A2C
+#define GT96100_MPSC_CHAN3_REG10 0x018A30
+#define GT96100_MPSC_CHAN3_REG11 0x018A34
+#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00
+#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04
+#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08
+#define GT96100_MPSC_CHAN4_REG1 0x020A0C
+#define GT96100_MPSC_CHAN4_REG2 0x020A10
+#define GT96100_MPSC_CHAN4_REG3 0x020A14
+#define GT96100_MPSC_CHAN4_REG4 0x020A18
+#define GT96100_MPSC_CHAN4_REG5 0x020A1C
+#define GT96100_MPSC_CHAN4_REG6 0x020A20
+#define GT96100_MPSC_CHAN4_REG7 0x020A24
+#define GT96100_MPSC_CHAN4_REG8 0x020A28
+#define GT96100_MPSC_CHAN4_REG9 0x020A2C
+#define GT96100_MPSC_CHAN4_REG10 0x020A30
+#define GT96100_MPSC_CHAN4_REG11 0x020A34
+#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00
+#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04
+#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08
+#define GT96100_MPSC_CHAN5_REG1 0x028A0C
+#define GT96100_MPSC_CHAN5_REG2 0x028A10
+#define GT96100_MPSC_CHAN5_REG3 0x028A14
+#define GT96100_MPSC_CHAN5_REG4 0x028A18
+#define GT96100_MPSC_CHAN5_REG5 0x028A1C
+#define GT96100_MPSC_CHAN5_REG6 0x028A20
+#define GT96100_MPSC_CHAN5_REG7 0x028A24
+#define GT96100_MPSC_CHAN5_REG8 0x028A28
+#define GT96100_MPSC_CHAN5_REG9 0x028A2C
+#define GT96100_MPSC_CHAN5_REG10 0x028A30
+#define GT96100_MPSC_CHAN5_REG11 0x028A34
+#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00
+#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04
+#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08
+#define GT96100_MPSC_CHAN6_REG1 0x030A0C
+#define GT96100_MPSC_CHAN6_REG2 0x030A10
+#define GT96100_MPSC_CHAN6_REG3 0x030A14
+#define GT96100_MPSC_CHAN6_REG4 0x030A18
+#define GT96100_MPSC_CHAN6_REG5 0x030A1C
+#define GT96100_MPSC_CHAN6_REG6 0x030A20
+#define GT96100_MPSC_CHAN6_REG7 0x030A24
+#define GT96100_MPSC_CHAN6_REG8 0x030A28
+#define GT96100_MPSC_CHAN6_REG9 0x030A2C
+#define GT96100_MPSC_CHAN6_REG10 0x030A30
+#define GT96100_MPSC_CHAN6_REG11 0x030A34
+#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00
+#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04
+#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08
+#define GT96100_MPSC_CHAN7_REG1 0x038A0C
+#define GT96100_MPSC_CHAN7_REG2 0x038A10
+#define GT96100_MPSC_CHAN7_REG3 0x038A14
+#define GT96100_MPSC_CHAN7_REG4 0x038A18
+#define GT96100_MPSC_CHAN7_REG5 0x038A1C
+#define GT96100_MPSC_CHAN7_REG6 0x038A20
+#define GT96100_MPSC_CHAN7_REG7 0x038A24
+#define GT96100_MPSC_CHAN7_REG8 0x038A28
+#define GT96100_MPSC_CHAN7_REG9 0x038A2C
+#define GT96100_MPSC_CHAN7_REG10 0x038A30
+#define GT96100_MPSC_CHAN7_REG11 0x038A34
+/* FlexTDMs */
+/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
+#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00
+#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00
+#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00
+#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00
+/* RDPR0 - Receive Dual Port RAM. block size 0xff */
+#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00
+#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00
+#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00
+#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00
+#define GT96100_FXTDM0_TX_READ_PTR 0x008B00
+#define GT96100_FXTDM0_RX_READ_PTR 0x008B04
+#define GT96100_FXTDM0_CONFIG 0x008B08
+#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
+#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
+#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
+#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
+#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00
+#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00
+#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00
+#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00
+#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00
+#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00
+#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00
+#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00
+#define GT96100_FXTDM1_TX_READ_PTR 0x018B00
+#define GT96100_FXTDM1_RX_READ_PTR 0x018B04
+#define GT96100_FXTDM1_CONFIG 0x018B08
+#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
+#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
+#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
+#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
+#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00
+#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00
+#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00
+#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00
+#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00
+#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00
+#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00
+#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00
+#define GT96100_FLTDM2_TX_READ_PTR 0x028B00
+#define GT96100_FLTDM2_RX_READ_PTR 0x028B04
+#define GT96100_FLTDM2_CONFIG 0x028B08
+#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
+#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
+#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
+#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
+#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00
+#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00
+#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00
+#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00
+#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00
+#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00
+#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00
+#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00
+#define GT96100_FXTDM3_TX_READ_PTR 0x038B00
+#define GT96100_FXTDM3_RX_READ_PTR 0x038B04
+#define GT96100_FXTDM3_CONFIG 0x038B08
+#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
+#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
+#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
+#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
+/* Baud Rate Generators */
+#define GT96100_BRG0_CONFIG 0x102A00
+#define GT96100_BRG0_BAUD_TUNE 0x102A04
+#define GT96100_BRG1_CONFIG 0x102A08
+#define GT96100_BRG1_BAUD_TUNE 0x102A0C
+#define GT96100_BRG2_CONFIG 0x102A10
+#define GT96100_BRG2_BAUD_TUNE 0x102A14
+#define GT96100_BRG3_CONFIG 0x102A18
+#define GT96100_BRG3_BAUD_TUNE 0x102A1C
+#define GT96100_BRG4_CONFIG 0x102A20
+#define GT96100_BRG4_BAUD_TUNE 0x102A24
+#define GT96100_BRG5_CONFIG 0x102A28
+#define GT96100_BRG5_BAUD_TUNE 0x102A2C
+#define GT96100_BRG6_CONFIG 0x102A30
+#define GT96100_BRG6_BAUD_TUNE 0x102A34
+#define GT96100_BRG7_CONFIG 0x102A38
+#define GT96100_BRG7_BAUD_TUNE 0x102A3C
+/* Routing Registers */
+#define GT96100_ROUTE_MAIN 0x101A00
+#define GT96100_ROUTE_RX_CLOCK 0x101A10
+#define GT96100_ROUTE_TX_CLOCK 0x101A20
+/* General Purpose Ports */
+#define GT96100_GPP_CONFIG0 0x100A00
+#define GT96100_GPP_CONFIG1 0x100A04
+#define GT96100_GPP_CONFIG2 0x100A08
+#define GT96100_GPP_CONFIG3 0x100A0C
+#define GT96100_GPP_IO0 0x100A20
+#define GT96100_GPP_IO1 0x100A24
+#define GT96100_GPP_IO2 0x100A28
+#define GT96100_GPP_IO3 0x100A2C
+#define GT96100_GPP_DATA0 0x100A40
+#define GT96100_GPP_DATA1 0x100A44
+#define GT96100_GPP_DATA2 0x100A48
+#define GT96100_GPP_DATA3 0x100A4C
+#define GT96100_GPP_LEVEL0 0x100A60
+#define GT96100_GPP_LEVEL1 0x100A64
+#define GT96100_GPP_LEVEL2 0x100A68
+#define GT96100_GPP_LEVEL3 0x100A6C
+/* Watchdog */
+#define GT96100_WD_CONFIG 0x101A80
+#define GT96100_WD_VALUE 0x101A84
+/* Communication Unit Arbiter */
+#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
+/* PCI Arbiters */
+#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
+#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
+/* CIU Arbiter */
+#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
+/* Interrupt Controller */
+#define GT96100_MAIN_CAUSE 0x000C18
+#define GT96100_INT0_MAIN_MASK 0x000C1C
+#define GT96100_INT1_MAIN_MASK 0x000C24
+#define GT96100_HIGH_CAUSE 0x000C98
+#define GT96100_INT0_HIGH_MASK 0x000C9C
+#define GT96100_INT1_HIGH_MASK 0x000CA4
+#define GT96100_INT0_SELECT 0x000C70
+#define GT96100_INT1_SELECT 0x000C74
+#define GT96100_SERIAL_CAUSE 0x103A00
+#define GT96100_SERINT0_MASK 0x103A80
+#define GT96100_SERINT1_MASK 0x103A88
+
+#endif /* _GT96100_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 3af11a591..d8b09483d 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -317,6 +317,57 @@ __OUTS(b,b,1)
__OUTS(h,w,2)
__OUTS(w,l,4)
+
+#ifdef CONFIG_MIPS_EV96100
+
+#include <asm/byteorder.h>
+
+#define inb(port) in_8((u8 *)((port)+mips_io_port_base))
+#define outb(val, port) out_8((u8 *)((port)+mips_io_port_base), (val))
+#define inw(port) in_16((u16 *)((port)+mips_io_port_base))
+#define outw(val, port) out_16((u16 *)((port)+mips_io_port_base), (val))
+#define inl(port) in_32((u32 *)((port)+mips_io_port_base))
+#define outl(val, port) out_32((u32 *)((port)+mips_io_port_base), (val))
+
+#define inb_p(port) inb((port))
+#define outb_p(val, port) outb((val), (port))
+#define inw_p(port) inw((port))
+#define outw_p(val, port) outw((val), (port))
+#define inl_p(port) inl((port))
+#define outl_p(val, port) outl((val), (port))
+
+extern inline unsigned char in_8(const unsigned char *addr)
+{
+ return *KSEG1ADDR(addr);
+}
+
+extern inline void out_8(unsigned char *addr, unsigned int val)
+{
+ *KSEG1ADDR(addr) = (unsigned char)val;
+}
+
+extern inline unsigned short in_16(const unsigned short *addr)
+{
+ return (le16_to_cpu(*KSEG1ADDR(addr)));
+}
+
+extern inline void out_16(unsigned short *addr, unsigned int val)
+{
+ *KSEG1ADDR(addr) = cpu_to_le16((unsigned short)val);
+}
+
+extern inline unsigned int in_32(const unsigned int *addr)
+{
+ return (le32_to_cpu(*KSEG1ADDR(addr)));
+}
+
+extern inline void out_32(unsigned int *addr, unsigned int val)
+{
+ *KSEG1ADDR(addr) = cpu_to_le32((unsigned int)val);
+}
+
+#else
+
/*
* Note that due to the way __builtin_constant_p() works, you
* - can't use it inside an inline function (it will never be true)
@@ -412,6 +463,7 @@ __OUTS(w,l,4)
((__builtin_constant_p((port)) && (port) < 32768) ? \
__inslc((port),(addr),(count)) : \
__insl((port),(addr),(count)))
+#endif
#define IO_SPACE_LIMIT 0xffff
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index f255684b4..519cacc25 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -76,6 +76,18 @@
#define JAZZ_SERIAL_PORT_DEFNS
#endif
+#ifdef CONFIG_MIPS_EV96100
+#include <asm/galileo-boards/ev96100.h>
+#include <asm/galileo-boards/ev96100int.h>
+#define EV96100_SERIAL_PORT_DEFNS \
+ { baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \
+ irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \
+ iomem_base: EV96100_UART0_REGS_BASE },
+#else
+#define EV96100_SERIAL_PORT_DEFNS
+#endif
+
+
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
@@ -152,7 +164,8 @@
#endif
#define SERIAL_PORT_DFNS \
+ EV96100_SERIAL_PORT_DEFNS \
JAZZ_SERIAL_PORT_DEFNS \
STD_SERIAL_PORT_DEFNS \
EXTRA_SERIAL_PORT_DEFNS \
- HUB6_SERIAL_PORT_DFNS
+ HUB6_SERIAL_PORT_DFNS