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-rw-r--r--include/asm-sparc/cache.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
index 55475a5a1..19885d7e9 100644
--- a/include/asm-sparc/cache.h
+++ b/include/asm-sparc/cache.h
@@ -1,4 +1,4 @@
-/* $Id: cache.h,v 1.7 1997/05/06 09:31:46 davem Exp $
+/* $Id: cache.h,v 1.8 1999/03/11 00:14:45 davem Exp $
* cache.h: Cache specific code for the Sparc. These include flushing
* and direct tag/data line access.
*
@@ -13,6 +13,8 @@
#define L1_CACHE_BYTES 32
#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
+#define SMP_CACHE_BYTES 32
+
/* Direct access to the instruction cache is provided through and
* alternate address space. The IDC bit must be off in the ICCR on
* HyperSparcs for these accesses to work. The code below does not do