diff options
Diffstat (limited to 'include/asm-sparc64')
43 files changed, 1722 insertions, 1592 deletions
diff --git a/include/asm-sparc64/a.out.h b/include/asm-sparc64/a.out.h index 1a16d0a74..02a745c81 100644 --- a/include/asm-sparc64/a.out.h +++ b/include/asm-sparc64/a.out.h @@ -1,4 +1,4 @@ -/* $Id: a.out.h,v 1.4 1997/05/04 07:21:19 davem Exp $ */ +/* $Id: a.out.h,v 1.6 1999/08/04 07:04:21 jj Exp $ */ #ifndef __SPARC64_A_OUT_H__ #define __SPARC64_A_OUT_H__ @@ -95,7 +95,7 @@ struct relocation_info /* used when header.a_machtype == M_SPARC */ #ifdef __KERNEL__ -#define STACK_TOP (current->tss.flags & SPARC_FLAG_32BIT ? 0xf0000000 : TASK_SIZE) +#define STACK_TOP (current->thread.flags & SPARC_FLAG_32BIT ? 0xf0000000 : 0x80000000000L) #endif diff --git a/include/asm-sparc64/asm_offsets.h b/include/asm-sparc64/asm_offsets.h index b1f87cc58..4b39659eb 100644 --- a/include/asm-sparc64/asm_offsets.h +++ b/include/asm-sparc64/asm_offsets.h @@ -4,6 +4,12 @@ #include <linux/config.h> +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +# if !((__GNUC__ > 2) || (__GNUC__ == 2 && __GNUC_MINOR__ >= 8)) +# error Please issue 'make check_asm' in linux top-level directory first +# endif +#endif + #ifndef CONFIG_SMP #define AOFF_task_state 0x00000000 @@ -36,10 +42,8 @@ #define ASIZ_task_next_task 0x00000008 #define AOFF_task_prev_task 0x00000058 #define ASIZ_task_prev_task 0x00000008 -#define AOFF_task_next_run 0x00000060 -#define ASIZ_task_next_run 0x00000008 -#define AOFF_task_prev_run 0x00000068 -#define ASIZ_task_prev_run 0x00000008 +#define AOFF_task_run_list 0x00000060 +#define ASIZ_task_run_list 0x00000010 #define AOFF_task_binfmt 0x00000070 #define ASIZ_task_binfmt 0x00000008 #define AOFF_task_exit_code 0x00000078 @@ -74,115 +78,115 @@ #define ASIZ_task_pidhash_next 0x00000008 #define AOFF_task_pidhash_pprev 0x000000d8 #define ASIZ_task_pidhash_pprev 0x00000008 -#define AOFF_task_tarray_ptr 0x000000e0 -#define ASIZ_task_tarray_ptr 0x00000008 -#define AOFF_task_wait_chldexit 0x000000e8 -#define ASIZ_task_wait_chldexit 0x00000028 -#define AOFF_task_vfork_sem 0x00000110 +#define AOFF_task_wait_chldexit 0x000000e0 +#define ASIZ_task_wait_chldexit 0x00000020 +#define AOFF_task_vfork_sem 0x00000100 #define ASIZ_task_vfork_sem 0x00000008 -#define AOFF_task_policy 0x00000118 +#define AOFF_task_policy 0x00000108 #define ASIZ_task_policy 0x00000008 -#define AOFF_task_rt_priority 0x00000120 +#define AOFF_task_rt_priority 0x00000110 #define ASIZ_task_rt_priority 0x00000008 -#define AOFF_task_it_real_value 0x00000128 +#define AOFF_task_it_real_value 0x00000118 #define ASIZ_task_it_real_value 0x00000008 -#define AOFF_task_it_prof_value 0x00000130 +#define AOFF_task_it_prof_value 0x00000120 #define ASIZ_task_it_prof_value 0x00000008 -#define AOFF_task_it_virt_value 0x00000138 +#define AOFF_task_it_virt_value 0x00000128 #define ASIZ_task_it_virt_value 0x00000008 -#define AOFF_task_it_real_incr 0x00000140 +#define AOFF_task_it_real_incr 0x00000130 #define ASIZ_task_it_real_incr 0x00000008 -#define AOFF_task_it_prof_incr 0x00000148 +#define AOFF_task_it_prof_incr 0x00000138 #define ASIZ_task_it_prof_incr 0x00000008 -#define AOFF_task_it_virt_incr 0x00000150 +#define AOFF_task_it_virt_incr 0x00000140 #define ASIZ_task_it_virt_incr 0x00000008 -#define AOFF_task_real_timer 0x00000158 +#define AOFF_task_real_timer 0x00000148 #define ASIZ_task_real_timer 0x00000028 -#define AOFF_task_times 0x00000180 +#define AOFF_task_times 0x00000170 #define ASIZ_task_times 0x00000020 -#define AOFF_task_start_time 0x000001a0 +#define AOFF_task_start_time 0x00000190 #define ASIZ_task_start_time 0x00000008 -#define AOFF_task_per_cpu_utime 0x000001a8 +#define AOFF_task_per_cpu_utime 0x00000198 #define ASIZ_task_per_cpu_utime 0x00000008 -#define AOFF_task_min_flt 0x000001b8 +#define AOFF_task_min_flt 0x000001a8 #define ASIZ_task_min_flt 0x00000008 -#define AOFF_task_maj_flt 0x000001c0 +#define AOFF_task_maj_flt 0x000001b0 #define ASIZ_task_maj_flt 0x00000008 -#define AOFF_task_nswap 0x000001c8 +#define AOFF_task_nswap 0x000001b8 #define ASIZ_task_nswap 0x00000008 -#define AOFF_task_cmin_flt 0x000001d0 +#define AOFF_task_cmin_flt 0x000001c0 #define ASIZ_task_cmin_flt 0x00000008 -#define AOFF_task_cmaj_flt 0x000001d8 +#define AOFF_task_cmaj_flt 0x000001c8 #define ASIZ_task_cmaj_flt 0x00000008 -#define AOFF_task_cnswap 0x000001e0 +#define AOFF_task_cnswap 0x000001d0 #define ASIZ_task_cnswap 0x00000008 -#define AOFF_task_uid 0x000001ec +#define AOFF_task_uid 0x000001dc #define ASIZ_task_uid 0x00000004 -#define AOFF_task_euid 0x000001f0 +#define AOFF_task_euid 0x000001e0 #define ASIZ_task_euid 0x00000004 -#define AOFF_task_suid 0x000001f4 +#define AOFF_task_suid 0x000001e4 #define ASIZ_task_suid 0x00000004 -#define AOFF_task_fsuid 0x000001f8 +#define AOFF_task_fsuid 0x000001e8 #define ASIZ_task_fsuid 0x00000004 -#define AOFF_task_gid 0x000001fc +#define AOFF_task_gid 0x000001ec #define ASIZ_task_gid 0x00000004 -#define AOFF_task_egid 0x00000200 +#define AOFF_task_egid 0x000001f0 #define ASIZ_task_egid 0x00000004 -#define AOFF_task_sgid 0x00000204 +#define AOFF_task_sgid 0x000001f4 #define ASIZ_task_sgid 0x00000004 -#define AOFF_task_fsgid 0x00000208 +#define AOFF_task_fsgid 0x000001f8 #define ASIZ_task_fsgid 0x00000004 -#define AOFF_task_ngroups 0x0000020c +#define AOFF_task_ngroups 0x000001fc #define ASIZ_task_ngroups 0x00000004 -#define AOFF_task_groups 0x00000210 +#define AOFF_task_groups 0x00000200 #define ASIZ_task_groups 0x00000080 -#define AOFF_task_cap_effective 0x00000290 +#define AOFF_task_cap_effective 0x00000280 #define ASIZ_task_cap_effective 0x00000004 -#define AOFF_task_cap_inheritable 0x00000294 +#define AOFF_task_cap_inheritable 0x00000284 #define ASIZ_task_cap_inheritable 0x00000004 -#define AOFF_task_cap_permitted 0x00000298 +#define AOFF_task_cap_permitted 0x00000288 #define ASIZ_task_cap_permitted 0x00000004 -#define AOFF_task_user 0x000002a0 +#define AOFF_task_user 0x00000290 #define ASIZ_task_user 0x00000008 -#define AOFF_task_rlim 0x000002a8 +#define AOFF_task_rlim 0x00000298 #define ASIZ_task_rlim 0x000000a0 -#define AOFF_task_used_math 0x00000348 +#define AOFF_task_used_math 0x00000338 #define ASIZ_task_used_math 0x00000002 -#define AOFF_task_comm 0x0000034a +#define AOFF_task_comm 0x0000033a #define ASIZ_task_comm 0x00000010 -#define AOFF_task_link_count 0x0000035c +#define AOFF_task_link_count 0x0000034c #define ASIZ_task_link_count 0x00000004 -#define AOFF_task_tty 0x00000360 +#define AOFF_task_tty 0x00000350 #define ASIZ_task_tty 0x00000008 -#define AOFF_task_semundo 0x00000368 +#define AOFF_task_semundo 0x00000358 #define ASIZ_task_semundo 0x00000008 -#define AOFF_task_semsleeping 0x00000370 +#define AOFF_task_semsleeping 0x00000360 #define ASIZ_task_semsleeping 0x00000008 -#define AOFF_task_tss 0x00000380 -#define ASIZ_task_tss 0x00000460 -#define AOFF_task_fs 0x000007e0 +#define AOFF_task_thread 0x00000370 +#define ASIZ_task_thread 0x00000460 +#define AOFF_task_fs 0x000007d0 #define ASIZ_task_fs 0x00000008 -#define AOFF_task_files 0x000007e8 +#define AOFF_task_files 0x000007d8 #define ASIZ_task_files 0x00000008 -#define AOFF_task_mm 0x000007f0 +#define AOFF_task_mm 0x000007e0 #define ASIZ_task_mm 0x00000008 -#define AOFF_task_sigmask_lock 0x000007f8 -#define ASIZ_task_sigmask_lock 0x00000001 -#define AOFF_task_sig 0x00000800 +#define AOFF_task_active_mm 0x000007e8 +#define ASIZ_task_active_mm 0x00000008 +#define AOFF_task_sigmask_lock 0x000007f0 +#define ASIZ_task_sigmask_lock 0x00000000 +#define AOFF_task_sig 0x000007f0 #define ASIZ_task_sig 0x00000008 -#define AOFF_task_signal 0x00000808 +#define AOFF_task_signal 0x000007f8 #define ASIZ_task_signal 0x00000008 -#define AOFF_task_blocked 0x00000810 +#define AOFF_task_blocked 0x00000800 #define ASIZ_task_blocked 0x00000008 -#define AOFF_task_sigqueue 0x00000818 +#define AOFF_task_sigqueue 0x00000808 #define ASIZ_task_sigqueue 0x00000008 -#define AOFF_task_sigqueue_tail 0x00000820 +#define AOFF_task_sigqueue_tail 0x00000810 #define ASIZ_task_sigqueue_tail 0x00000008 -#define AOFF_task_sas_ss_sp 0x00000828 +#define AOFF_task_sas_ss_sp 0x00000818 #define ASIZ_task_sas_ss_sp 0x00000008 -#define AOFF_task_sas_ss_size 0x00000830 +#define AOFF_task_sas_ss_size 0x00000820 #define ASIZ_task_sas_ss_size 0x00000008 -#define ASIZ_task 0x00000840 +#define ASIZ_task 0x00000830 #define AOFF_mm_mmap 0x00000000 #define ASIZ_mm_mmap 0x00000008 #define AOFF_mm_mmap_avl 0x00000008 @@ -191,91 +195,95 @@ #define ASIZ_mm_mmap_cache 0x00000008 #define AOFF_mm_pgd 0x00000018 #define ASIZ_mm_pgd 0x00000008 -#define AOFF_mm_count 0x00000020 -#define ASIZ_mm_count 0x00000004 -#define AOFF_mm_map_count 0x00000024 +#define AOFF_mm_mm_users 0x00000020 +#define ASIZ_mm_mm_users 0x00000004 +#define AOFF_mm_mm_count 0x00000024 +#define ASIZ_mm_mm_count 0x00000004 +#define AOFF_mm_map_count 0x00000028 #define ASIZ_mm_map_count 0x00000004 -#define AOFF_mm_mmap_sem 0x00000028 -#define ASIZ_mm_mmap_sem 0x00000038 +#define AOFF_mm_mmap_sem 0x00000030 +#define ASIZ_mm_mmap_sem 0x00000030 #define AOFF_mm_page_table_lock 0x00000060 -#define ASIZ_mm_page_table_lock 0x00000001 -#define AOFF_mm_context 0x00000068 +#define ASIZ_mm_page_table_lock 0x00000000 +#define AOFF_mm_context 0x00000060 #define ASIZ_mm_context 0x00000008 -#define AOFF_mm_start_code 0x00000070 +#define AOFF_mm_start_code 0x00000068 #define ASIZ_mm_start_code 0x00000008 -#define AOFF_mm_end_code 0x00000078 +#define AOFF_mm_end_code 0x00000070 #define ASIZ_mm_end_code 0x00000008 -#define AOFF_mm_start_data 0x00000080 +#define AOFF_mm_start_data 0x00000078 #define ASIZ_mm_start_data 0x00000008 -#define AOFF_mm_end_data 0x00000088 +#define AOFF_mm_end_data 0x00000080 #define ASIZ_mm_end_data 0x00000008 -#define AOFF_mm_start_brk 0x00000090 +#define AOFF_mm_start_brk 0x00000088 #define ASIZ_mm_start_brk 0x00000008 -#define AOFF_mm_brk 0x00000098 +#define AOFF_mm_brk 0x00000090 #define ASIZ_mm_brk 0x00000008 -#define AOFF_mm_start_stack 0x000000a0 +#define AOFF_mm_start_stack 0x00000098 #define ASIZ_mm_start_stack 0x00000008 -#define AOFF_mm_arg_start 0x000000a8 +#define AOFF_mm_arg_start 0x000000a0 #define ASIZ_mm_arg_start 0x00000008 -#define AOFF_mm_arg_end 0x000000b0 +#define AOFF_mm_arg_end 0x000000a8 #define ASIZ_mm_arg_end 0x00000008 -#define AOFF_mm_env_start 0x000000b8 +#define AOFF_mm_env_start 0x000000b0 #define ASIZ_mm_env_start 0x00000008 -#define AOFF_mm_env_end 0x000000c0 +#define AOFF_mm_env_end 0x000000b8 #define ASIZ_mm_env_end 0x00000008 -#define AOFF_mm_rss 0x000000c8 +#define AOFF_mm_rss 0x000000c0 #define ASIZ_mm_rss 0x00000008 -#define AOFF_mm_total_vm 0x000000d0 +#define AOFF_mm_total_vm 0x000000c8 #define ASIZ_mm_total_vm 0x00000008 -#define AOFF_mm_locked_vm 0x000000d8 +#define AOFF_mm_locked_vm 0x000000d0 #define ASIZ_mm_locked_vm 0x00000008 -#define AOFF_mm_def_flags 0x000000e0 +#define AOFF_mm_def_flags 0x000000d8 #define ASIZ_mm_def_flags 0x00000008 -#define AOFF_mm_cpu_vm_mask 0x000000e8 +#define AOFF_mm_cpu_vm_mask 0x000000e0 #define ASIZ_mm_cpu_vm_mask 0x00000008 -#define AOFF_mm_swap_cnt 0x000000f0 +#define AOFF_mm_swap_cnt 0x000000e8 #define ASIZ_mm_swap_cnt 0x00000008 -#define AOFF_mm_swap_address 0x000000f8 +#define AOFF_mm_swap_address 0x000000f0 #define ASIZ_mm_swap_address 0x00000008 -#define AOFF_mm_segments 0x00000100 +#define AOFF_mm_segments 0x000000f8 #define ASIZ_mm_segments 0x00000008 -#define ASIZ_mm 0x00000108 +#define ASIZ_mm 0x00000100 #define AOFF_thread_ksp 0x00000000 #define ASIZ_thread_ksp 0x00000008 #define AOFF_thread_wstate 0x00000008 -#define ASIZ_thread_wstate 0x00000002 -#define AOFF_thread_cwp 0x0000000a -#define ASIZ_thread_cwp 0x00000002 -#define AOFF_thread_flags 0x0000000c -#define ASIZ_thread_flags 0x00000002 -#define AOFF_thread_current_ds 0x0000000e +#define ASIZ_thread_wstate 0x00000001 +#define AOFF_thread_cwp 0x00000009 +#define ASIZ_thread_cwp 0x00000001 +#define AOFF_thread_flags 0x0000000a +#define ASIZ_thread_flags 0x00000001 +#define AOFF_thread_current_ds 0x0000000b #define ASIZ_thread_current_ds 0x00000001 -#define AOFF_thread_w_saved 0x00000010 -#define ASIZ_thread_w_saved 0x00000002 -#define AOFF_thread_new_signal 0x00000012 -#define ASIZ_thread_new_signal 0x00000002 -#define AOFF_thread_ctx 0x00000014 -#define ASIZ_thread_ctx 0x00000002 +#define AOFF_thread_w_saved 0x0000000c +#define ASIZ_thread_w_saved 0x00000001 +#define AOFF_thread_fpdepth 0x0000000d +#define ASIZ_thread_fpdepth 0x00000001 +#define AOFF_thread_fpsaved 0x0000000e +#define ASIZ_thread_fpsaved 0x00000007 +#define AOFF_thread___pad1 0x00000015 +#define ASIZ_thread___pad1 0x00000003 #define AOFF_thread_kregs 0x00000018 #define ASIZ_thread_kregs 0x00000008 #define AOFF_thread_utraps 0x00000020 #define ASIZ_thread_utraps 0x00000008 -#define AOFF_thread_fpdepth 0x00000028 -#define ASIZ_thread_fpdepth 0x00000001 -#define AOFF_thread_fpsaved 0x00000029 -#define ASIZ_thread_fpsaved 0x00000007 -#define AOFF_thread_gsr 0x00000030 +#define AOFF_thread_gsr 0x00000028 #define ASIZ_thread_gsr 0x00000007 -#define AOFF_thread_xfsr 0x00000038 +#define AOFF_thread___pad2 0x0000002f +#define ASIZ_thread___pad2 0x00000001 +#define AOFF_thread_sig_address 0x00000030 +#define ASIZ_thread_sig_address 0x00000008 +#define AOFF_thread_sig_desc 0x00000038 +#define ASIZ_thread_sig_desc 0x00000008 +#define AOFF_thread_xfsr 0x00000040 #define ASIZ_thread_xfsr 0x00000038 -#define AOFF_thread_reg_window 0x00000070 +#define AOFF_thread___pad3 0x00000078 +#define ASIZ_thread___pad3 0x00000008 +#define AOFF_thread_reg_window 0x00000080 #define ASIZ_thread_reg_window 0x00000380 -#define AOFF_thread_rwbuf_stkptrs 0x000003f0 +#define AOFF_thread_rwbuf_stkptrs 0x00000400 #define ASIZ_thread_rwbuf_stkptrs 0x00000038 -#define AOFF_thread_sig_address 0x00000428 -#define ASIZ_thread_sig_address 0x00000008 -#define AOFF_thread_sig_desc 0x00000430 -#define ASIZ_thread_sig_desc 0x00000008 #define AOFF_thread_user_cntd0 0x00000438 #define ASIZ_thread_user_cntd0 0x00000008 #define AOFF_thread_user_cntd1 0x00000440 @@ -322,10 +330,8 @@ #define ASIZ_task_next_task 0x00000008 #define AOFF_task_prev_task 0x00000058 #define ASIZ_task_prev_task 0x00000008 -#define AOFF_task_next_run 0x00000060 -#define ASIZ_task_next_run 0x00000008 -#define AOFF_task_prev_run 0x00000068 -#define ASIZ_task_prev_run 0x00000008 +#define AOFF_task_run_list 0x00000060 +#define ASIZ_task_run_list 0x00000010 #define AOFF_task_binfmt 0x00000070 #define ASIZ_task_binfmt 0x00000008 #define AOFF_task_exit_code 0x00000078 @@ -360,115 +366,115 @@ #define ASIZ_task_pidhash_next 0x00000008 #define AOFF_task_pidhash_pprev 0x000000d8 #define ASIZ_task_pidhash_pprev 0x00000008 -#define AOFF_task_tarray_ptr 0x000000e0 -#define ASIZ_task_tarray_ptr 0x00000008 -#define AOFF_task_wait_chldexit 0x000000e8 +#define AOFF_task_wait_chldexit 0x000000e0 #define ASIZ_task_wait_chldexit 0x00000028 -#define AOFF_task_vfork_sem 0x00000110 +#define AOFF_task_vfork_sem 0x00000108 #define ASIZ_task_vfork_sem 0x00000008 -#define AOFF_task_policy 0x00000118 +#define AOFF_task_policy 0x00000110 #define ASIZ_task_policy 0x00000008 -#define AOFF_task_rt_priority 0x00000120 +#define AOFF_task_rt_priority 0x00000118 #define ASIZ_task_rt_priority 0x00000008 -#define AOFF_task_it_real_value 0x00000128 +#define AOFF_task_it_real_value 0x00000120 #define ASIZ_task_it_real_value 0x00000008 -#define AOFF_task_it_prof_value 0x00000130 +#define AOFF_task_it_prof_value 0x00000128 #define ASIZ_task_it_prof_value 0x00000008 -#define AOFF_task_it_virt_value 0x00000138 +#define AOFF_task_it_virt_value 0x00000130 #define ASIZ_task_it_virt_value 0x00000008 -#define AOFF_task_it_real_incr 0x00000140 +#define AOFF_task_it_real_incr 0x00000138 #define ASIZ_task_it_real_incr 0x00000008 -#define AOFF_task_it_prof_incr 0x00000148 +#define AOFF_task_it_prof_incr 0x00000140 #define ASIZ_task_it_prof_incr 0x00000008 -#define AOFF_task_it_virt_incr 0x00000150 +#define AOFF_task_it_virt_incr 0x00000148 #define ASIZ_task_it_virt_incr 0x00000008 -#define AOFF_task_real_timer 0x00000158 +#define AOFF_task_real_timer 0x00000150 #define ASIZ_task_real_timer 0x00000028 -#define AOFF_task_times 0x00000180 +#define AOFF_task_times 0x00000178 #define ASIZ_task_times 0x00000020 -#define AOFF_task_start_time 0x000001a0 +#define AOFF_task_start_time 0x00000198 #define ASIZ_task_start_time 0x00000008 -#define AOFF_task_per_cpu_utime 0x000001a8 +#define AOFF_task_per_cpu_utime 0x000001a0 #define ASIZ_task_per_cpu_utime 0x00000100 -#define AOFF_task_min_flt 0x000003a8 +#define AOFF_task_min_flt 0x000003a0 #define ASIZ_task_min_flt 0x00000008 -#define AOFF_task_maj_flt 0x000003b0 +#define AOFF_task_maj_flt 0x000003a8 #define ASIZ_task_maj_flt 0x00000008 -#define AOFF_task_nswap 0x000003b8 +#define AOFF_task_nswap 0x000003b0 #define ASIZ_task_nswap 0x00000008 -#define AOFF_task_cmin_flt 0x000003c0 +#define AOFF_task_cmin_flt 0x000003b8 #define ASIZ_task_cmin_flt 0x00000008 -#define AOFF_task_cmaj_flt 0x000003c8 +#define AOFF_task_cmaj_flt 0x000003c0 #define ASIZ_task_cmaj_flt 0x00000008 -#define AOFF_task_cnswap 0x000003d0 +#define AOFF_task_cnswap 0x000003c8 #define ASIZ_task_cnswap 0x00000008 -#define AOFF_task_uid 0x000003dc +#define AOFF_task_uid 0x000003d4 #define ASIZ_task_uid 0x00000004 -#define AOFF_task_euid 0x000003e0 +#define AOFF_task_euid 0x000003d8 #define ASIZ_task_euid 0x00000004 -#define AOFF_task_suid 0x000003e4 +#define AOFF_task_suid 0x000003dc #define ASIZ_task_suid 0x00000004 -#define AOFF_task_fsuid 0x000003e8 +#define AOFF_task_fsuid 0x000003e0 #define ASIZ_task_fsuid 0x00000004 -#define AOFF_task_gid 0x000003ec +#define AOFF_task_gid 0x000003e4 #define ASIZ_task_gid 0x00000004 -#define AOFF_task_egid 0x000003f0 +#define AOFF_task_egid 0x000003e8 #define ASIZ_task_egid 0x00000004 -#define AOFF_task_sgid 0x000003f4 +#define AOFF_task_sgid 0x000003ec #define ASIZ_task_sgid 0x00000004 -#define AOFF_task_fsgid 0x000003f8 +#define AOFF_task_fsgid 0x000003f0 #define ASIZ_task_fsgid 0x00000004 -#define AOFF_task_ngroups 0x000003fc +#define AOFF_task_ngroups 0x000003f4 #define ASIZ_task_ngroups 0x00000004 -#define AOFF_task_groups 0x00000400 +#define AOFF_task_groups 0x000003f8 #define ASIZ_task_groups 0x00000080 -#define AOFF_task_cap_effective 0x00000480 +#define AOFF_task_cap_effective 0x00000478 #define ASIZ_task_cap_effective 0x00000004 -#define AOFF_task_cap_inheritable 0x00000484 +#define AOFF_task_cap_inheritable 0x0000047c #define ASIZ_task_cap_inheritable 0x00000004 -#define AOFF_task_cap_permitted 0x00000488 +#define AOFF_task_cap_permitted 0x00000480 #define ASIZ_task_cap_permitted 0x00000004 -#define AOFF_task_user 0x00000490 +#define AOFF_task_user 0x00000488 #define ASIZ_task_user 0x00000008 -#define AOFF_task_rlim 0x00000498 +#define AOFF_task_rlim 0x00000490 #define ASIZ_task_rlim 0x000000a0 -#define AOFF_task_used_math 0x00000538 +#define AOFF_task_used_math 0x00000530 #define ASIZ_task_used_math 0x00000002 -#define AOFF_task_comm 0x0000053a +#define AOFF_task_comm 0x00000532 #define ASIZ_task_comm 0x00000010 -#define AOFF_task_link_count 0x0000054c +#define AOFF_task_link_count 0x00000544 #define ASIZ_task_link_count 0x00000004 -#define AOFF_task_tty 0x00000550 +#define AOFF_task_tty 0x00000548 #define ASIZ_task_tty 0x00000008 -#define AOFF_task_semundo 0x00000558 +#define AOFF_task_semundo 0x00000550 #define ASIZ_task_semundo 0x00000008 -#define AOFF_task_semsleeping 0x00000560 +#define AOFF_task_semsleeping 0x00000558 #define ASIZ_task_semsleeping 0x00000008 -#define AOFF_task_tss 0x00000570 -#define ASIZ_task_tss 0x00000460 -#define AOFF_task_fs 0x000009d0 +#define AOFF_task_thread 0x00000560 +#define ASIZ_task_thread 0x00000460 +#define AOFF_task_fs 0x000009c0 #define ASIZ_task_fs 0x00000008 -#define AOFF_task_files 0x000009d8 +#define AOFF_task_files 0x000009c8 #define ASIZ_task_files 0x00000008 -#define AOFF_task_mm 0x000009e0 +#define AOFF_task_mm 0x000009d0 #define ASIZ_task_mm 0x00000008 -#define AOFF_task_sigmask_lock 0x000009e8 +#define AOFF_task_active_mm 0x000009d8 +#define ASIZ_task_active_mm 0x00000008 +#define AOFF_task_sigmask_lock 0x000009e0 #define ASIZ_task_sigmask_lock 0x00000001 -#define AOFF_task_sig 0x000009f0 +#define AOFF_task_sig 0x000009e8 #define ASIZ_task_sig 0x00000008 -#define AOFF_task_signal 0x000009f8 +#define AOFF_task_signal 0x000009f0 #define ASIZ_task_signal 0x00000008 -#define AOFF_task_blocked 0x00000a00 +#define AOFF_task_blocked 0x000009f8 #define ASIZ_task_blocked 0x00000008 -#define AOFF_task_sigqueue 0x00000a08 +#define AOFF_task_sigqueue 0x00000a00 #define ASIZ_task_sigqueue 0x00000008 -#define AOFF_task_sigqueue_tail 0x00000a10 +#define AOFF_task_sigqueue_tail 0x00000a08 #define ASIZ_task_sigqueue_tail 0x00000008 -#define AOFF_task_sas_ss_sp 0x00000a18 +#define AOFF_task_sas_ss_sp 0x00000a10 #define ASIZ_task_sas_ss_sp 0x00000008 -#define AOFF_task_sas_ss_size 0x00000a20 +#define AOFF_task_sas_ss_size 0x00000a18 #define ASIZ_task_sas_ss_size 0x00000008 -#define ASIZ_task 0x00000a30 +#define ASIZ_task 0x00000a20 #define AOFF_mm_mmap 0x00000000 #define ASIZ_mm_mmap 0x00000008 #define AOFF_mm_mmap_avl 0x00000008 @@ -477,91 +483,95 @@ #define ASIZ_mm_mmap_cache 0x00000008 #define AOFF_mm_pgd 0x00000018 #define ASIZ_mm_pgd 0x00000008 -#define AOFF_mm_count 0x00000020 -#define ASIZ_mm_count 0x00000004 -#define AOFF_mm_map_count 0x00000024 +#define AOFF_mm_mm_users 0x00000020 +#define ASIZ_mm_mm_users 0x00000004 +#define AOFF_mm_mm_count 0x00000024 +#define ASIZ_mm_mm_count 0x00000004 +#define AOFF_mm_map_count 0x00000028 #define ASIZ_mm_map_count 0x00000004 -#define AOFF_mm_mmap_sem 0x00000028 +#define AOFF_mm_mmap_sem 0x00000030 #define ASIZ_mm_mmap_sem 0x00000038 -#define AOFF_mm_page_table_lock 0x00000060 +#define AOFF_mm_page_table_lock 0x00000068 #define ASIZ_mm_page_table_lock 0x00000001 -#define AOFF_mm_context 0x00000068 +#define AOFF_mm_context 0x00000070 #define ASIZ_mm_context 0x00000008 -#define AOFF_mm_start_code 0x00000070 +#define AOFF_mm_start_code 0x00000078 #define ASIZ_mm_start_code 0x00000008 -#define AOFF_mm_end_code 0x00000078 +#define AOFF_mm_end_code 0x00000080 #define ASIZ_mm_end_code 0x00000008 -#define AOFF_mm_start_data 0x00000080 +#define AOFF_mm_start_data 0x00000088 #define ASIZ_mm_start_data 0x00000008 -#define AOFF_mm_end_data 0x00000088 +#define AOFF_mm_end_data 0x00000090 #define ASIZ_mm_end_data 0x00000008 -#define AOFF_mm_start_brk 0x00000090 +#define AOFF_mm_start_brk 0x00000098 #define ASIZ_mm_start_brk 0x00000008 -#define AOFF_mm_brk 0x00000098 +#define AOFF_mm_brk 0x000000a0 #define ASIZ_mm_brk 0x00000008 -#define AOFF_mm_start_stack 0x000000a0 +#define AOFF_mm_start_stack 0x000000a8 #define ASIZ_mm_start_stack 0x00000008 -#define AOFF_mm_arg_start 0x000000a8 +#define AOFF_mm_arg_start 0x000000b0 #define ASIZ_mm_arg_start 0x00000008 -#define AOFF_mm_arg_end 0x000000b0 +#define AOFF_mm_arg_end 0x000000b8 #define ASIZ_mm_arg_end 0x00000008 -#define AOFF_mm_env_start 0x000000b8 +#define AOFF_mm_env_start 0x000000c0 #define ASIZ_mm_env_start 0x00000008 -#define AOFF_mm_env_end 0x000000c0 +#define AOFF_mm_env_end 0x000000c8 #define ASIZ_mm_env_end 0x00000008 -#define AOFF_mm_rss 0x000000c8 +#define AOFF_mm_rss 0x000000d0 #define ASIZ_mm_rss 0x00000008 -#define AOFF_mm_total_vm 0x000000d0 +#define AOFF_mm_total_vm 0x000000d8 #define ASIZ_mm_total_vm 0x00000008 -#define AOFF_mm_locked_vm 0x000000d8 +#define AOFF_mm_locked_vm 0x000000e0 #define ASIZ_mm_locked_vm 0x00000008 -#define AOFF_mm_def_flags 0x000000e0 +#define AOFF_mm_def_flags 0x000000e8 #define ASIZ_mm_def_flags 0x00000008 -#define AOFF_mm_cpu_vm_mask 0x000000e8 +#define AOFF_mm_cpu_vm_mask 0x000000f0 #define ASIZ_mm_cpu_vm_mask 0x00000008 -#define AOFF_mm_swap_cnt 0x000000f0 +#define AOFF_mm_swap_cnt 0x000000f8 #define ASIZ_mm_swap_cnt 0x00000008 -#define AOFF_mm_swap_address 0x000000f8 +#define AOFF_mm_swap_address 0x00000100 #define ASIZ_mm_swap_address 0x00000008 -#define AOFF_mm_segments 0x00000100 +#define AOFF_mm_segments 0x00000108 #define ASIZ_mm_segments 0x00000008 -#define ASIZ_mm 0x00000108 +#define ASIZ_mm 0x00000110 #define AOFF_thread_ksp 0x00000000 #define ASIZ_thread_ksp 0x00000008 #define AOFF_thread_wstate 0x00000008 -#define ASIZ_thread_wstate 0x00000002 -#define AOFF_thread_cwp 0x0000000a -#define ASIZ_thread_cwp 0x00000002 -#define AOFF_thread_flags 0x0000000c -#define ASIZ_thread_flags 0x00000002 -#define AOFF_thread_current_ds 0x0000000e +#define ASIZ_thread_wstate 0x00000001 +#define AOFF_thread_cwp 0x00000009 +#define ASIZ_thread_cwp 0x00000001 +#define AOFF_thread_flags 0x0000000a +#define ASIZ_thread_flags 0x00000001 +#define AOFF_thread_current_ds 0x0000000b #define ASIZ_thread_current_ds 0x00000001 -#define AOFF_thread_w_saved 0x00000010 -#define ASIZ_thread_w_saved 0x00000002 -#define AOFF_thread_new_signal 0x00000012 -#define ASIZ_thread_new_signal 0x00000002 -#define AOFF_thread_ctx 0x00000014 -#define ASIZ_thread_ctx 0x00000002 +#define AOFF_thread_w_saved 0x0000000c +#define ASIZ_thread_w_saved 0x00000001 +#define AOFF_thread_fpdepth 0x0000000d +#define ASIZ_thread_fpdepth 0x00000001 +#define AOFF_thread_fpsaved 0x0000000e +#define ASIZ_thread_fpsaved 0x00000007 +#define AOFF_thread___pad1 0x00000015 +#define ASIZ_thread___pad1 0x00000003 #define AOFF_thread_kregs 0x00000018 #define ASIZ_thread_kregs 0x00000008 #define AOFF_thread_utraps 0x00000020 #define ASIZ_thread_utraps 0x00000008 -#define AOFF_thread_fpdepth 0x00000028 -#define ASIZ_thread_fpdepth 0x00000001 -#define AOFF_thread_fpsaved 0x00000029 -#define ASIZ_thread_fpsaved 0x00000007 -#define AOFF_thread_gsr 0x00000030 +#define AOFF_thread_gsr 0x00000028 #define ASIZ_thread_gsr 0x00000007 -#define AOFF_thread_xfsr 0x00000038 +#define AOFF_thread___pad2 0x0000002f +#define ASIZ_thread___pad2 0x00000001 +#define AOFF_thread_sig_address 0x00000030 +#define ASIZ_thread_sig_address 0x00000008 +#define AOFF_thread_sig_desc 0x00000038 +#define ASIZ_thread_sig_desc 0x00000008 +#define AOFF_thread_xfsr 0x00000040 #define ASIZ_thread_xfsr 0x00000038 -#define AOFF_thread_reg_window 0x00000070 +#define AOFF_thread___pad3 0x00000078 +#define ASIZ_thread___pad3 0x00000008 +#define AOFF_thread_reg_window 0x00000080 #define ASIZ_thread_reg_window 0x00000380 -#define AOFF_thread_rwbuf_stkptrs 0x000003f0 +#define AOFF_thread_rwbuf_stkptrs 0x00000400 #define ASIZ_thread_rwbuf_stkptrs 0x00000038 -#define AOFF_thread_sig_address 0x00000428 -#define ASIZ_thread_sig_address 0x00000008 -#define AOFF_thread_sig_desc 0x00000430 -#define ASIZ_thread_sig_desc 0x00000008 #define AOFF_thread_user_cntd0 0x00000438 #define ASIZ_thread_user_cntd0 0x00000008 #define AOFF_thread_user_cntd1 0x00000440 @@ -606,10 +616,8 @@ #define ASIZ_task_next_task 0x00000008 #define AOFF_task_prev_task 0x00000058 #define ASIZ_task_prev_task 0x00000008 -#define AOFF_task_next_run 0x00000060 -#define ASIZ_task_next_run 0x00000008 -#define AOFF_task_prev_run 0x00000068 -#define ASIZ_task_prev_run 0x00000008 +#define AOFF_task_run_list 0x00000060 +#define ASIZ_task_run_list 0x00000010 #define AOFF_task_binfmt 0x00000070 #define ASIZ_task_binfmt 0x00000008 #define AOFF_task_exit_code 0x00000078 @@ -644,115 +652,115 @@ #define ASIZ_task_pidhash_next 0x00000008 #define AOFF_task_pidhash_pprev 0x000000d8 #define ASIZ_task_pidhash_pprev 0x00000008 -#define AOFF_task_tarray_ptr 0x000000e0 -#define ASIZ_task_tarray_ptr 0x00000008 -#define AOFF_task_wait_chldexit 0x000000e8 +#define AOFF_task_wait_chldexit 0x000000e0 #define ASIZ_task_wait_chldexit 0x00000030 -#define AOFF_task_vfork_sem 0x00000118 +#define AOFF_task_vfork_sem 0x00000110 #define ASIZ_task_vfork_sem 0x00000008 -#define AOFF_task_policy 0x00000120 +#define AOFF_task_policy 0x00000118 #define ASIZ_task_policy 0x00000008 -#define AOFF_task_rt_priority 0x00000128 +#define AOFF_task_rt_priority 0x00000120 #define ASIZ_task_rt_priority 0x00000008 -#define AOFF_task_it_real_value 0x00000130 +#define AOFF_task_it_real_value 0x00000128 #define ASIZ_task_it_real_value 0x00000008 -#define AOFF_task_it_prof_value 0x00000138 +#define AOFF_task_it_prof_value 0x00000130 #define ASIZ_task_it_prof_value 0x00000008 -#define AOFF_task_it_virt_value 0x00000140 +#define AOFF_task_it_virt_value 0x00000138 #define ASIZ_task_it_virt_value 0x00000008 -#define AOFF_task_it_real_incr 0x00000148 +#define AOFF_task_it_real_incr 0x00000140 #define ASIZ_task_it_real_incr 0x00000008 -#define AOFF_task_it_prof_incr 0x00000150 +#define AOFF_task_it_prof_incr 0x00000148 #define ASIZ_task_it_prof_incr 0x00000008 -#define AOFF_task_it_virt_incr 0x00000158 +#define AOFF_task_it_virt_incr 0x00000150 #define ASIZ_task_it_virt_incr 0x00000008 -#define AOFF_task_real_timer 0x00000160 +#define AOFF_task_real_timer 0x00000158 #define ASIZ_task_real_timer 0x00000028 -#define AOFF_task_times 0x00000188 +#define AOFF_task_times 0x00000180 #define ASIZ_task_times 0x00000020 -#define AOFF_task_start_time 0x000001a8 +#define AOFF_task_start_time 0x000001a0 #define ASIZ_task_start_time 0x00000008 -#define AOFF_task_per_cpu_utime 0x000001b0 +#define AOFF_task_per_cpu_utime 0x000001a8 #define ASIZ_task_per_cpu_utime 0x00000100 -#define AOFF_task_min_flt 0x000003b0 +#define AOFF_task_min_flt 0x000003a8 #define ASIZ_task_min_flt 0x00000008 -#define AOFF_task_maj_flt 0x000003b8 +#define AOFF_task_maj_flt 0x000003b0 #define ASIZ_task_maj_flt 0x00000008 -#define AOFF_task_nswap 0x000003c0 +#define AOFF_task_nswap 0x000003b8 #define ASIZ_task_nswap 0x00000008 -#define AOFF_task_cmin_flt 0x000003c8 +#define AOFF_task_cmin_flt 0x000003c0 #define ASIZ_task_cmin_flt 0x00000008 -#define AOFF_task_cmaj_flt 0x000003d0 +#define AOFF_task_cmaj_flt 0x000003c8 #define ASIZ_task_cmaj_flt 0x00000008 -#define AOFF_task_cnswap 0x000003d8 +#define AOFF_task_cnswap 0x000003d0 #define ASIZ_task_cnswap 0x00000008 -#define AOFF_task_uid 0x000003e4 +#define AOFF_task_uid 0x000003dc #define ASIZ_task_uid 0x00000004 -#define AOFF_task_euid 0x000003e8 +#define AOFF_task_euid 0x000003e0 #define ASIZ_task_euid 0x00000004 -#define AOFF_task_suid 0x000003ec +#define AOFF_task_suid 0x000003e4 #define ASIZ_task_suid 0x00000004 -#define AOFF_task_fsuid 0x000003f0 +#define AOFF_task_fsuid 0x000003e8 #define ASIZ_task_fsuid 0x00000004 -#define AOFF_task_gid 0x000003f4 +#define AOFF_task_gid 0x000003ec #define ASIZ_task_gid 0x00000004 -#define AOFF_task_egid 0x000003f8 +#define AOFF_task_egid 0x000003f0 #define ASIZ_task_egid 0x00000004 -#define AOFF_task_sgid 0x000003fc +#define AOFF_task_sgid 0x000003f4 #define ASIZ_task_sgid 0x00000004 -#define AOFF_task_fsgid 0x00000400 +#define AOFF_task_fsgid 0x000003f8 #define ASIZ_task_fsgid 0x00000004 -#define AOFF_task_ngroups 0x00000404 +#define AOFF_task_ngroups 0x000003fc #define ASIZ_task_ngroups 0x00000004 -#define AOFF_task_groups 0x00000408 +#define AOFF_task_groups 0x00000400 #define ASIZ_task_groups 0x00000080 -#define AOFF_task_cap_effective 0x00000488 +#define AOFF_task_cap_effective 0x00000480 #define ASIZ_task_cap_effective 0x00000004 -#define AOFF_task_cap_inheritable 0x0000048c +#define AOFF_task_cap_inheritable 0x00000484 #define ASIZ_task_cap_inheritable 0x00000004 -#define AOFF_task_cap_permitted 0x00000490 +#define AOFF_task_cap_permitted 0x00000488 #define ASIZ_task_cap_permitted 0x00000004 -#define AOFF_task_user 0x00000498 +#define AOFF_task_user 0x00000490 #define ASIZ_task_user 0x00000008 -#define AOFF_task_rlim 0x000004a0 +#define AOFF_task_rlim 0x00000498 #define ASIZ_task_rlim 0x000000a0 -#define AOFF_task_used_math 0x00000540 +#define AOFF_task_used_math 0x00000538 #define ASIZ_task_used_math 0x00000002 -#define AOFF_task_comm 0x00000542 +#define AOFF_task_comm 0x0000053a #define ASIZ_task_comm 0x00000010 -#define AOFF_task_link_count 0x00000554 +#define AOFF_task_link_count 0x0000054c #define ASIZ_task_link_count 0x00000004 -#define AOFF_task_tty 0x00000558 +#define AOFF_task_tty 0x00000550 #define ASIZ_task_tty 0x00000008 -#define AOFF_task_semundo 0x00000560 +#define AOFF_task_semundo 0x00000558 #define ASIZ_task_semundo 0x00000008 -#define AOFF_task_semsleeping 0x00000568 +#define AOFF_task_semsleeping 0x00000560 #define ASIZ_task_semsleeping 0x00000008 -#define AOFF_task_tss 0x00000570 -#define ASIZ_task_tss 0x00000460 +#define AOFF_task_thread 0x00000570 +#define ASIZ_task_thread 0x00000460 #define AOFF_task_fs 0x000009d0 #define ASIZ_task_fs 0x00000008 #define AOFF_task_files 0x000009d8 #define ASIZ_task_files 0x00000008 #define AOFF_task_mm 0x000009e0 #define ASIZ_task_mm 0x00000008 -#define AOFF_task_sigmask_lock 0x000009e8 +#define AOFF_task_active_mm 0x000009e8 +#define ASIZ_task_active_mm 0x00000008 +#define AOFF_task_sigmask_lock 0x000009f0 #define ASIZ_task_sigmask_lock 0x0000000c -#define AOFF_task_sig 0x000009f8 +#define AOFF_task_sig 0x00000a00 #define ASIZ_task_sig 0x00000008 -#define AOFF_task_signal 0x00000a00 +#define AOFF_task_signal 0x00000a08 #define ASIZ_task_signal 0x00000008 -#define AOFF_task_blocked 0x00000a08 +#define AOFF_task_blocked 0x00000a10 #define ASIZ_task_blocked 0x00000008 -#define AOFF_task_sigqueue 0x00000a10 +#define AOFF_task_sigqueue 0x00000a18 #define ASIZ_task_sigqueue 0x00000008 -#define AOFF_task_sigqueue_tail 0x00000a18 +#define AOFF_task_sigqueue_tail 0x00000a20 #define ASIZ_task_sigqueue_tail 0x00000008 -#define AOFF_task_sas_ss_sp 0x00000a20 +#define AOFF_task_sas_ss_sp 0x00000a28 #define ASIZ_task_sas_ss_sp 0x00000008 -#define AOFF_task_sas_ss_size 0x00000a28 +#define AOFF_task_sas_ss_size 0x00000a30 #define ASIZ_task_sas_ss_size 0x00000008 -#define ASIZ_task 0x00000a30 +#define ASIZ_task 0x00000a40 #define AOFF_mm_mmap 0x00000000 #define ASIZ_mm_mmap 0x00000008 #define AOFF_mm_mmap_avl 0x00000008 @@ -761,91 +769,95 @@ #define ASIZ_mm_mmap_cache 0x00000008 #define AOFF_mm_pgd 0x00000018 #define ASIZ_mm_pgd 0x00000008 -#define AOFF_mm_count 0x00000020 -#define ASIZ_mm_count 0x00000004 -#define AOFF_mm_map_count 0x00000024 +#define AOFF_mm_mm_users 0x00000020 +#define ASIZ_mm_mm_users 0x00000004 +#define AOFF_mm_mm_count 0x00000024 +#define ASIZ_mm_mm_count 0x00000004 +#define AOFF_mm_map_count 0x00000028 #define ASIZ_mm_map_count 0x00000004 -#define AOFF_mm_mmap_sem 0x00000028 +#define AOFF_mm_mmap_sem 0x00000030 #define ASIZ_mm_mmap_sem 0x00000040 -#define AOFF_mm_page_table_lock 0x00000068 +#define AOFF_mm_page_table_lock 0x00000070 #define ASIZ_mm_page_table_lock 0x0000000c -#define AOFF_mm_context 0x00000078 +#define AOFF_mm_context 0x00000080 #define ASIZ_mm_context 0x00000008 -#define AOFF_mm_start_code 0x00000080 +#define AOFF_mm_start_code 0x00000088 #define ASIZ_mm_start_code 0x00000008 -#define AOFF_mm_end_code 0x00000088 +#define AOFF_mm_end_code 0x00000090 #define ASIZ_mm_end_code 0x00000008 -#define AOFF_mm_start_data 0x00000090 +#define AOFF_mm_start_data 0x00000098 #define ASIZ_mm_start_data 0x00000008 -#define AOFF_mm_end_data 0x00000098 +#define AOFF_mm_end_data 0x000000a0 #define ASIZ_mm_end_data 0x00000008 -#define AOFF_mm_start_brk 0x000000a0 +#define AOFF_mm_start_brk 0x000000a8 #define ASIZ_mm_start_brk 0x00000008 -#define AOFF_mm_brk 0x000000a8 +#define AOFF_mm_brk 0x000000b0 #define ASIZ_mm_brk 0x00000008 -#define AOFF_mm_start_stack 0x000000b0 +#define AOFF_mm_start_stack 0x000000b8 #define ASIZ_mm_start_stack 0x00000008 -#define AOFF_mm_arg_start 0x000000b8 +#define AOFF_mm_arg_start 0x000000c0 #define ASIZ_mm_arg_start 0x00000008 -#define AOFF_mm_arg_end 0x000000c0 +#define AOFF_mm_arg_end 0x000000c8 #define ASIZ_mm_arg_end 0x00000008 -#define AOFF_mm_env_start 0x000000c8 +#define AOFF_mm_env_start 0x000000d0 #define ASIZ_mm_env_start 0x00000008 -#define AOFF_mm_env_end 0x000000d0 +#define AOFF_mm_env_end 0x000000d8 #define ASIZ_mm_env_end 0x00000008 -#define AOFF_mm_rss 0x000000d8 +#define AOFF_mm_rss 0x000000e0 #define ASIZ_mm_rss 0x00000008 -#define AOFF_mm_total_vm 0x000000e0 +#define AOFF_mm_total_vm 0x000000e8 #define ASIZ_mm_total_vm 0x00000008 -#define AOFF_mm_locked_vm 0x000000e8 +#define AOFF_mm_locked_vm 0x000000f0 #define ASIZ_mm_locked_vm 0x00000008 -#define AOFF_mm_def_flags 0x000000f0 +#define AOFF_mm_def_flags 0x000000f8 #define ASIZ_mm_def_flags 0x00000008 -#define AOFF_mm_cpu_vm_mask 0x000000f8 +#define AOFF_mm_cpu_vm_mask 0x00000100 #define ASIZ_mm_cpu_vm_mask 0x00000008 -#define AOFF_mm_swap_cnt 0x00000100 +#define AOFF_mm_swap_cnt 0x00000108 #define ASIZ_mm_swap_cnt 0x00000008 -#define AOFF_mm_swap_address 0x00000108 +#define AOFF_mm_swap_address 0x00000110 #define ASIZ_mm_swap_address 0x00000008 -#define AOFF_mm_segments 0x00000110 +#define AOFF_mm_segments 0x00000118 #define ASIZ_mm_segments 0x00000008 -#define ASIZ_mm 0x00000118 +#define ASIZ_mm 0x00000120 #define AOFF_thread_ksp 0x00000000 #define ASIZ_thread_ksp 0x00000008 #define AOFF_thread_wstate 0x00000008 -#define ASIZ_thread_wstate 0x00000002 -#define AOFF_thread_cwp 0x0000000a -#define ASIZ_thread_cwp 0x00000002 -#define AOFF_thread_flags 0x0000000c -#define ASIZ_thread_flags 0x00000002 -#define AOFF_thread_current_ds 0x0000000e +#define ASIZ_thread_wstate 0x00000001 +#define AOFF_thread_cwp 0x00000009 +#define ASIZ_thread_cwp 0x00000001 +#define AOFF_thread_flags 0x0000000a +#define ASIZ_thread_flags 0x00000001 +#define AOFF_thread_current_ds 0x0000000b #define ASIZ_thread_current_ds 0x00000001 -#define AOFF_thread_w_saved 0x00000010 -#define ASIZ_thread_w_saved 0x00000002 -#define AOFF_thread_new_signal 0x00000012 -#define ASIZ_thread_new_signal 0x00000002 -#define AOFF_thread_ctx 0x00000014 -#define ASIZ_thread_ctx 0x00000002 +#define AOFF_thread_w_saved 0x0000000c +#define ASIZ_thread_w_saved 0x00000001 +#define AOFF_thread_fpdepth 0x0000000d +#define ASIZ_thread_fpdepth 0x00000001 +#define AOFF_thread_fpsaved 0x0000000e +#define ASIZ_thread_fpsaved 0x00000007 +#define AOFF_thread___pad1 0x00000015 +#define ASIZ_thread___pad1 0x00000003 #define AOFF_thread_kregs 0x00000018 #define ASIZ_thread_kregs 0x00000008 #define AOFF_thread_utraps 0x00000020 #define ASIZ_thread_utraps 0x00000008 -#define AOFF_thread_fpdepth 0x00000028 -#define ASIZ_thread_fpdepth 0x00000001 -#define AOFF_thread_fpsaved 0x00000029 -#define ASIZ_thread_fpsaved 0x00000007 -#define AOFF_thread_gsr 0x00000030 +#define AOFF_thread_gsr 0x00000028 #define ASIZ_thread_gsr 0x00000007 -#define AOFF_thread_xfsr 0x00000038 +#define AOFF_thread___pad2 0x0000002f +#define ASIZ_thread___pad2 0x00000001 +#define AOFF_thread_sig_address 0x00000030 +#define ASIZ_thread_sig_address 0x00000008 +#define AOFF_thread_sig_desc 0x00000038 +#define ASIZ_thread_sig_desc 0x00000008 +#define AOFF_thread_xfsr 0x00000040 #define ASIZ_thread_xfsr 0x00000038 -#define AOFF_thread_reg_window 0x00000070 +#define AOFF_thread___pad3 0x00000078 +#define ASIZ_thread___pad3 0x00000008 +#define AOFF_thread_reg_window 0x00000080 #define ASIZ_thread_reg_window 0x00000380 -#define AOFF_thread_rwbuf_stkptrs 0x000003f0 +#define AOFF_thread_rwbuf_stkptrs 0x00000400 #define ASIZ_thread_rwbuf_stkptrs 0x00000038 -#define AOFF_thread_sig_address 0x00000428 -#define ASIZ_thread_sig_address 0x00000008 -#define AOFF_thread_sig_desc 0x00000430 -#define ASIZ_thread_sig_desc 0x00000008 #define AOFF_thread_user_cntd0 0x00000438 #define ASIZ_thread_user_cntd0 0x00000008 #define AOFF_thread_user_cntd1 0x00000440 diff --git a/include/asm-sparc64/audioio.h b/include/asm-sparc64/audioio.h index 01bebaf73..cb9a213a3 100644 --- a/include/asm-sparc64/audioio.h +++ b/include/asm-sparc64/audioio.h @@ -299,6 +299,8 @@ struct sparcaudio_driver /* Hack to make it look like we support variable size buffers. */ int buffer_size; + + int mixer_modify_counter; }; struct sparcaudio_operations @@ -432,23 +434,6 @@ extern int cs4231_init(void); #endif -/* Mixer helper ioctls */ -#define right(a) (((a >> 8) & 0xff) % 101) -#define left(a) ((a & 0xff) % 101) - -/* Macros to convert between mixer stereo volumes and gain (mono) */ -#define s_to_m(a) ((((left(a) + right(a)) * 255) / 200) % 256) -#define m_to_s(a) ((a * 100 / 255) + ((a * 100 / 255) << 8)) - -/* convert mixer stereo volume to balance */ -#define s_to_b(a) (s_to_g(a) == 0) ? 32 : ((left(a) * AUDIO_RIGHT_BALANCE / (left(a) + right(a)))) - -/* convert mixer stereo volume to audio gain */ -#define s_to_g(a) ((((right(a) + left(a)) * 255) / 200) % 256) - -/* convert gain a and balance b to mixer volume */ -#define b_to_s(a,b) (((((b * a * 200) / (AUDIO_RIGHT_BALANCE * 255)) % 100) << 8) + ((((AUDIO_RIGHT_BALANCE - b) * a * 200) / (AUDIO_RIGHT_BALANCE * 255)) % 100)) - /* Device minor numbers */ #define SPARCAUDIO_MIXER_MINOR 0 @@ -514,4 +499,147 @@ struct stdata #define I_GETSIG _IOR('S',012,int) #define I_GETSIG_SOLARIS (('S'<<8)|12) -#endif + +/* Conversion between Sun and OSS volume settings */ +static __inline__ +int OSS_LEFT(int value) +{ + return ((value & 0xff) % 101); +} + +static __inline__ +int OSS_RIGHT(int value) +{ + return (((value >> 8) & 0xff) % 101); +} + +static __inline__ +int O_TO_S(int value) +{ + return value * 255 / 100; +} + +static __inline__ +int S_TO_O(int value) +{ + return value * 100 / 255; +} + +static __inline__ +int OSS_TO_GAIN(int value) +{ + int l = O_TO_S(OSS_LEFT(value)); + int r = O_TO_S(OSS_RIGHT(value)); + return ((l > r) ? l : r); +} + +static __inline__ +int OSS_TO_LGAIN(int value) +{ + int l = O_TO_S(OSS_LEFT(value)); + int r = O_TO_S(OSS_RIGHT(value)); + return ((l < r) ? l : r); +} + +static __inline__ +int OSS_TO_BAL(int value) +{ + if (!OSS_TO_GAIN(value)) + return AUDIO_MID_BALANCE; + if (!OSS_TO_LGAIN(value)) { + if (OSS_TO_GAIN(value) == OSS_TO_GAIN(OSS_RIGHT(value))) + return AUDIO_RIGHT_BALANCE; + else + return AUDIO_LEFT_BALANCE; + } + if (OSS_TO_GAIN(value) == OSS_TO_GAIN(OSS_RIGHT(value))) + return ((OSS_TO_GAIN(value) - OSS_TO_LGAIN(value)) >> AUDIO_BALANCE_SHIFT) + + AUDIO_MID_BALANCE; + else + return AUDIO_MID_BALANCE - ((OSS_TO_GAIN(value) - OSS_TO_LGAIN(value)) + >> AUDIO_BALANCE_SHIFT); +} + +static __inline__ +int BAL_TO_OSS(int value, unsigned char balance) +{ + int l, r, adj; + if (balance > 63) balance = 63; + if (balance < AUDIO_MID_BALANCE) { + l = (int)value * 100 / 255 + ((value * 100 % 255) > 0); + adj = ((AUDIO_MID_BALANCE - balance) << AUDIO_BALANCE_SHIFT); + if (adj < value) + r = (int)(value - adj) + * 100 / 255; + else r = 0; + } else if (balance > AUDIO_MID_BALANCE) { + r = (int)value * 100 / 255 + ((value * 100 % 255) > 0); + adj = ((balance - AUDIO_MID_BALANCE) << AUDIO_BALANCE_SHIFT); + if (adj < value) + l = (int)(value - adj) + * 100 / 255; + else l = 0; + } else { + l = r = (int)value * 100 / 255 + ((value * 100 % 255) > 0); + } + + return ((r << 8) + l); +} + +/* OSS mixer ioctl port handling */ +static __inline__ +int OSS_PORT_AUDIO(struct sparcaudio_driver *drv, unsigned int set) +{ + int p; + if (drv->ops->get_output_port) { + p = drv->ops->get_output_port(drv); + if (p & set) + return 0x6464; + } + return 0; +} + +static __inline__ +int OSS_IPORT_AUDIO(struct sparcaudio_driver *drv, unsigned int set) +{ + int p; + if (drv->ops->get_input_port) { + p = drv->ops->get_input_port(drv); + if (p & set) + return 0x6464; + } + return 0; +} + +static __inline__ +void OSS_TWIDDLE_PORT(struct sparcaudio_driver *drv, unsigned int ioctl, + unsigned int port, unsigned int set, unsigned int value) +{ + if (ioctl == port) { + int p; + if (drv->ops->get_output_port && drv->ops->set_output_port) { + p = drv->ops->get_output_port(drv); + if ((value == 0) || ((p & set) && (OSS_LEFT(value) < 100))) + drv->ops->set_output_port(drv, p & ~(set)); + else + drv->ops->set_output_port(drv, p | set); + } + } +} + +static __inline__ +void OSS_TWIDDLE_IPORT(struct sparcaudio_driver *drv, unsigned int ioctl, + unsigned int port, unsigned int set, unsigned int value) +{ + if (ioctl == port) { + int p; + if (drv->ops->get_input_port && drv->ops->set_input_port) { + p = drv->ops->get_input_port(drv); + if ((value == 0) || ((p & set) && (OSS_LEFT(value) < 100))) + drv->ops->set_input_port(drv, p & ~(set)); + else + drv->ops->set_input_port(drv, p | set); + } + } +} +#endif /* _AUDIOIO_H_ */ diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h index bc40fe99d..216b665f2 100644 --- a/include/asm-sparc64/cache.h +++ b/include/asm-sparc64/cache.h @@ -11,4 +11,12 @@ #define SMP_CACHE_BYTES 64 /* L2 cache line size. */ +#ifdef MODULE +#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) +#else +#define __cacheline_aligned \ + __attribute__((__aligned__(SMP_CACHE_BYTES), \ + __section__(".data.cacheline_aligned"))) +#endif + #endif diff --git a/include/asm-sparc64/checksum.h b/include/asm-sparc64/checksum.h index 5308186e7..519074118 100644 --- a/include/asm-sparc64/checksum.h +++ b/include/asm-sparc64/checksum.h @@ -1,4 +1,4 @@ -/* $Id: checksum.h,v 1.12 1999/05/25 16:53:36 jj Exp $ */ +/* $Id: checksum.h,v 1.13 1999/07/30 09:31:13 davem Exp $ */ #ifndef __SPARC64_CHECKSUM_H #define __SPARC64_CHECKSUM_H @@ -50,7 +50,7 @@ csum_partial_copy_nocheck (const char *src, char *dst, int len, unsigned int sum) { int ret; - unsigned char cur_ds = current->tss.current_ds.seg; + unsigned char cur_ds = current->thread.current_ds.seg; __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "i" (ASI_P)); ret = csum_partial_copy_sparc64(src, dst, len, sum); __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" (cur_ds)); diff --git a/include/asm-sparc64/dma.h b/include/asm-sparc64/dma.h index a0980bc30..b21cbcc9f 100644 --- a/include/asm-sparc64/dma.h +++ b/include/asm-sparc64/dma.h @@ -1,4 +1,4 @@ -/* $Id: dma.h,v 1.13 1998/12/16 04:33:55 davem Exp $ +/* $Id: dma.h,v 1.16 1999/09/10 10:44:32 davem Exp $ * include/asm-sparc64/dma.h * * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu) @@ -7,13 +7,14 @@ #ifndef _ASM_SPARC64_DMA_H #define _ASM_SPARC64_DMA_H +#include <linux/config.h> #include <linux/kernel.h> #include <linux/types.h> +#include <linux/spinlock.h> #include <asm/sbus.h> #include <asm/delay.h> #include <asm/oplib.h> -#include <asm/spinlock.h> extern spinlock_t dma_spin_lock; @@ -188,4 +189,12 @@ extern int get_dma_list(char *); extern int request_dma(unsigned int, __const__ char *); extern void free_dma(unsigned int); +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + #endif /* !(_ASM_SPARC64_DMA_H) */ diff --git a/include/asm-sparc64/ebus.h b/include/asm-sparc64/ebus.h index 8724757c7..7910d03ae 100644 --- a/include/asm-sparc64/ebus.h +++ b/include/asm-sparc64/ebus.h @@ -1,12 +1,14 @@ -/* $Id: ebus.h,v 1.8 1998/05/07 21:00:27 ecd Exp $ +/* $Id: ebus.h,v 1.9 1999/08/30 10:14:37 davem Exp $ * ebus.h: PCI to Ebus pseudo driver software state. * * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) + * Copyright (C) 1999 David S. Miller (davem@redhat.com) */ #ifndef __SPARC64_EBUS_H #define __SPARC64_EBUS_H +#include <asm/pbm.h> #include <asm/oplib.h> struct linux_ebus_child { @@ -15,7 +17,7 @@ struct linux_ebus_child { struct linux_ebus *bus; int prom_node; char prom_name[64]; - unsigned long base_address[PROMREG_MAX]; + struct resource resource[PROMREG_MAX]; int num_addrs; unsigned int irqs[PROMINTR_MAX]; int num_irqs; @@ -27,7 +29,7 @@ struct linux_ebus_device { struct linux_ebus *bus; int prom_node; char prom_name[64]; - unsigned long base_address[PROMREG_MAX]; + struct resource resource[PROMREG_MAX]; int num_addrs; unsigned int irqs[PROMINTR_MAX]; int num_irqs; @@ -36,8 +38,9 @@ struct linux_ebus_device { struct linux_ebus { struct linux_ebus *next; struct linux_ebus_device *devices; - struct linux_pbm_info *parent; + struct pci_pbm_info *parent; struct pci_dev *self; + int index; int prom_node; char prom_name[64]; struct linux_prom_ebus_ranges ebus_ranges[PROMREG_MAX]; diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h index e0db514fc..6fc6c3c03 100644 --- a/include/asm-sparc64/elf.h +++ b/include/asm-sparc64/elf.h @@ -1,4 +1,4 @@ -/* $Id: elf.h,v 1.19 1999/06/11 13:26:04 jj Exp $ */ +/* $Id: elf.h,v 1.21 1999/08/04 07:04:23 jj Exp $ */ #ifndef __ASM_SPARC64_ELF_H #define __ASM_SPARC64_ELF_H @@ -48,7 +48,7 @@ typedef struct { that it will "exec", and that there is sufficient room for the brk. */ #ifndef ELF_ET_DYN_BASE -#define ELF_ET_DYN_BASE 0x50000000000 +#define ELF_ET_DYN_BASE 0xfffff80000000000UL #endif @@ -67,17 +67,30 @@ typedef struct { #define ELF_PLATFORM (NULL) #ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) \ -do { \ - if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ - current->tss.flags |= SPARC_FLAG_32BIT; \ - else \ - current->tss.flags &= ~SPARC_FLAG_32BIT; \ - \ - if (ibcs2) \ - current->personality = PER_SVR4; \ - else if (current->personality != PER_LINUX32) \ - current->personality = PER_LINUX; \ +#define SET_PERSONALITY(ex, ibcs2) \ +do { unsigned char flags = current->thread.flags; \ + if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ + flags |= SPARC_FLAG_32BIT; \ + else \ + flags &= ~SPARC_FLAG_32BIT; \ + if (flags != current->thread.flags) { \ + unsigned long pgd_cache = 0UL; \ + if (flags & SPARC_FLAG_32BIT) \ + pgd_cache = \ + pgd_val(current->mm->pgd[0])<<11UL; \ + __asm__ __volatile__( \ + "stxa\t%0, [%1] %2" \ + : /* no outputs */ \ + : "r" (pgd_cache), \ + "r" (TSB_REG), \ + "i" (ASI_DMMU)); \ + current->thread.flags = flags; \ + } \ + \ + if (ibcs2) \ + current->personality = PER_SVR4; \ + else if (current->personality != PER_LINUX32) \ + current->personality = PER_LINUX; \ } while (0) #endif diff --git a/include/asm-sparc64/fbio.h b/include/asm-sparc64/fbio.h index 6f45ce973..3f5f3c81f 100644 --- a/include/asm-sparc64/fbio.h +++ b/include/asm-sparc64/fbio.h @@ -35,6 +35,8 @@ /* Does not seem to be listed in the Sun file either */ #define FBTYPE_CREATOR 22 +#define FBTYPE_PCI_IGA1682 23 +#define FBTYPE_P9100COLOR 24 #define FBTYPE_PCI_GENERIC 1000 #define FBTYPE_PCI_MACH64 1001 diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h index 80b58af20..d6d292f7d 100644 --- a/include/asm-sparc64/floppy.h +++ b/include/asm-sparc64/floppy.h @@ -289,16 +289,19 @@ extern void floppy_interrupt(int irq, void *dev_id, struct pt_regs *regs); static unsigned char sun_pci_fd_inb(unsigned long port) { + udelay(5); return inb(port); } static void sun_pci_fd_outb(unsigned char val, unsigned long port) { + udelay(5); outb(val, port); } static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port) { + udelay(5); /* * XXX: Due to SUN's broken floppy connector on AX and AXi * we need to turn on MOTOR_0 also, if the floppy is @@ -317,6 +320,7 @@ static void sun_pci_fd_broken_outb(unsigned char val, unsigned long port) #ifdef PCI_FDC_SWAP_DRIVES static void sun_pci_fd_lde_broken_outb(unsigned char val, unsigned long port) { + udelay(5); /* * XXX: Due to SUN's broken floppy connector on AX and AXi * we need to turn on MOTOR_0 also, if the floppy is @@ -339,9 +343,9 @@ static void sun_pci_fd_reset_dma(void) unsigned int dcsr; writel(EBUS_DCSR_RESET, &sun_pci_fd_ebus_dma->dcsr); - + udelay(1); dcsr = EBUS_DCSR_BURST_SZ_16 | EBUS_DCSR_TCI_DIS | - EBUS_DCSR_EN_CNT | EBUS_DCSR_INT_EN; + EBUS_DCSR_EN_CNT; writel(dcsr, (unsigned long)&sun_pci_fd_ebus_dma->dcsr); } @@ -359,12 +363,19 @@ static void sun_pci_fd_disable_dma(void) unsigned int dcsr; dcsr = readl(&sun_pci_fd_ebus_dma->dcsr); - while (dcsr & EBUS_DCSR_DRAIN) - dcsr = readl(&sun_pci_fd_ebus_dma->dcsr); - dcsr &= ~(EBUS_DCSR_EN_DMA); - if (dcsr & EBUS_DCSR_ERR_PEND) - sun_pci_fd_reset_dma(); - writel(dcsr, &sun_pci_fd_ebus_dma->dcsr); + if (dcsr & EBUS_DCSR_EN_DMA) { + while (dcsr & EBUS_DCSR_DRAIN) { + udelay(1); + dcsr = readl(&sun_pci_fd_ebus_dma->dcsr); + } + dcsr &= ~(EBUS_DCSR_EN_DMA); + writel(dcsr, &sun_pci_fd_ebus_dma->dcsr); + if (dcsr & EBUS_DCSR_ERR_PEND) { + sun_pci_fd_reset_dma(); + dcsr &= ~(EBUS_DCSR_ERR_PEND); + writel(dcsr, &sun_pci_fd_ebus_dma->dcsr); + } + } } static void sun_pci_fd_set_dma_mode(int mode) @@ -372,6 +383,11 @@ static void sun_pci_fd_set_dma_mode(int mode) unsigned int dcsr; dcsr = readl(&sun_pci_fd_ebus_dma->dcsr); + if (readl(&sun_pci_fd_ebus_dma->dbcr)) { + sun_pci_fd_reset_dma(); + writel(dcsr, &sun_pci_fd_ebus_dma->dcsr); + } + dcsr |= EBUS_DCSR_EN_CNT | EBUS_DCSR_TC; /* * For EBus WRITE means to system memory, which is @@ -397,7 +413,15 @@ static void sun_pci_fd_set_dma_addr(char *buffer) static unsigned int sun_pci_get_dma_residue(void) { - return readl(&sun_pci_fd_ebus_dma->dbcr); + unsigned int dcsr, res; + + res = readl(&sun_pci_fd_ebus_dma->dbcr); + if (res != 0) { + dcsr = readl(&sun_pci_fd_ebus_dma->dcsr); + sun_pci_fd_reset_dma(); + writel(dcsr, &sun_pci_fd_ebus_dma->dcsr); + } + return res; } static void sun_pci_fd_enable_irq(void) @@ -538,7 +562,7 @@ static int sun_pci_fd_test_drive(unsigned long port, int drive) static struct linux_prom_registers fd_regs[2]; -__initfunc(static unsigned long sun_floppy_init(void)) +static unsigned long __init sun_floppy_init(void) { char state[128]; int fd_node, num_regs; @@ -561,6 +585,9 @@ __initfunc(static unsigned long sun_floppy_init(void)) #ifdef CONFIG_PCI struct linux_ebus *ebus; struct linux_ebus_device *edev = 0; + unsigned long config = 0; + unsigned long auxio_reg; + unsigned char cfg; for_each_ebus(ebus) { for_each_ebusdev(edev, ebus) { @@ -577,20 +604,17 @@ __initfunc(static unsigned long sun_floppy_init(void)) if(!strncmp(state, "disabled", 8)) return 0; - if (check_region(edev->base_address[1], - sizeof(struct linux_ebus_dma))) { - printk("sun_floppy_init: can't get region at %016lx\n", - edev->base_address[1]); - return 0; - } - request_region(edev->base_address[1], - sizeof(struct linux_ebus_dma), "floppy DMA"); - - sun_fdc = (struct sun_flpy_controller *)edev->base_address[0]; + sun_fdc = (struct sun_flpy_controller *)edev->resource[0].start; FLOPPY_IRQ = edev->irqs[0]; + /* Make sure the high density bit is set, some systems + * (most notably Ultra5/Ultra10) come up with it clear. + */ + auxio_reg = edev->resource[2].start; + writel(readl(auxio_reg)|0x2, auxio_reg); + sun_pci_fd_ebus_dma = (struct linux_ebus_dma *) - edev->base_address[1]; + edev->resource[1].start; sun_pci_fd_reset_dma(); sun_fdops.fd_inb = sun_pci_fd_inb; @@ -628,57 +652,62 @@ __initfunc(static unsigned long sun_floppy_init(void)) if (sun_pci_fd_test_drive((unsigned long)sun_fdc, 1)) sun_floppy_types[1] = 4; -#ifdef PCI_FDC_SWAP_DRIVES /* - * If only Floppy 1 is present, swap drives. + * Find NS87303 SuperIO config registers (through ecpp). */ - if (!sun_floppy_types[0] && sun_floppy_types[1]) { - unsigned long config = 0; - unsigned char tmp; - - for_each_ebus(ebus) { - for_each_ebusdev(edev, ebus) { - if (!strcmp(edev->prom_name, "ecpp")) { - config = edev->base_address[1]; - goto config_done; - } + for_each_ebus(ebus) { + for_each_ebusdev(edev, ebus) { + if (!strcmp(edev->prom_name, "ecpp")) { + config = edev->resource[1].start; + goto config_done; } } - config_done: + } + config_done: - /* - * Sanity check, is this really the NS87303? - */ - switch (config & 0x3ff) { - case 0x02e: - case 0x15c: - case 0x26e: - case 0x398: - break; - default: - config = 0; - } + /* + * Sanity check, is this really the NS87303? + */ + switch (config & 0x3ff) { + case 0x02e: + case 0x15c: + case 0x26e: + case 0x398: + break; + default: + config = 0; + } + + if (!config) + return sun_floppy_types[0]; - if (!config) - return sun_floppy_types[0]; + /* Enable PC-AT mode. */ + cfg = ns87303_readb(config, ASC); + cfg |= 0xc0; + ns87303_writeb(config, ASC, cfg); +#ifdef PCI_FDC_SWAP_DRIVES + /* + * If only Floppy 1 is present, swap drives. + */ + if (!sun_floppy_types[0] && sun_floppy_types[1]) { /* * Set the drive exchange bit in FCR on NS87303, * make shure other bits are sane before doing so. */ - tmp = ns87303_readb(config, FER); - tmp &= ~(FER_EDM); - ns87303_writeb(config, FER, tmp); - tmp = ns87303_readb(config, ASC); - tmp &= ~(ASC_DRV2_SEL); - ns87303_writeb(config, ASC, tmp); - tmp = ns87303_readb(config, FCR); - tmp |= FCR_LDE; - ns87303_writeb(config, FCR, tmp); - - tmp = sun_floppy_types[0]; + cfg = ns87303_readb(config, FER); + cfg &= ~(FER_EDM); + ns87303_writeb(config, FER, cfg); + cfg = ns87303_readb(config, ASC); + cfg &= ~(ASC_DRV2_SEL); + ns87303_writeb(config, ASC, cfg); + cfg = ns87303_readb(config, FCR); + cfg |= FCR_LDE; + ns87303_writeb(config, FCR, cfg); + + cfg = sun_floppy_types[0]; sun_floppy_types[0] = sun_floppy_types[1]; - sun_floppy_types[1] = tmp; + sun_floppy_types[1] = cfg; if (sun_pci_broken_drive != -1) { sun_pci_broken_drive = 1 - sun_pci_broken_drive; diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h index 6ab9ef7ec..7df1d1346 100644 --- a/include/asm-sparc64/hardirq.h +++ b/include/asm-sparc64/hardirq.h @@ -6,7 +6,7 @@ #ifndef __SPARC64_HARDIRQ_H #define __SPARC64_HARDIRQ_H -#include <linux/tasks.h> +#include <linux/threads.h> #ifndef __SMP__ extern unsigned int local_irq_count; @@ -33,7 +33,7 @@ extern unsigned int local_irq_count; #else /* (__SMP__) */ #include <asm/atomic.h> -#include <asm/spinlock.h> +#include <linux/spinlock.h> #include <asm/system.h> #include <asm/smp.h> diff --git a/include/asm-sparc64/ide.h b/include/asm-sparc64/ide.h index c8db43d59..0f6d0de23 100644 --- a/include/asm-sparc64/ide.h +++ b/include/asm-sparc64/ide.h @@ -1,4 +1,4 @@ -/* $Id: ide.h,v 1.14 1999/05/15 05:02:35 davem Exp $ +/* $Id: ide.h,v 1.16 1999/08/30 10:14:42 davem Exp $ * ide.h: Ultra/PCI specific IDE glue. * * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) @@ -10,6 +10,7 @@ #ifdef __KERNEL__ +#include <linux/config.h> #include <asm/pgtable.h> #include <asm/io.h> #include <asm/hdreg.h> @@ -53,7 +54,7 @@ static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, */ static __inline__ void ide_init_default_hwifs(void) { -#ifdef __DO_I_NEED_THIS +#ifndef CONFIG_BLK_DEV_IDEPCI hw_regs_t hw; int index; @@ -62,7 +63,7 @@ static __inline__ void ide_init_default_hwifs(void) hw.irq = ide_default_irq(ide_default_io_base(index)); ide_register_hw(&hw, NULL); } -#endif /* __DO_I_NEED_THIS */ +#endif /* CONFIG_BLK_DEV_IDEPCI */ } typedef union { @@ -134,50 +135,62 @@ static __inline__ void ide_release_region(ide_ioreg_t base, unsigned int size) #define insw(port, buf, nr) ide_insw((port), (buf), (nr)) #define outsw(port, buf, nr) ide_outsw((port), (buf), (nr)) +static __inline__ unsigned int inw_be(unsigned long addr) +{ + unsigned int ret; + + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + + return ret; +} + static __inline__ void ide_insw(unsigned long port, void *dst, unsigned long count) { - volatile unsigned short *data_port; unsigned long end = (unsigned long)dst + (count << 1); u16 *ps = dst; u32 *pi; - data_port = (volatile unsigned short *)port; - if(((u64)ps) & 0x2) { - *ps++ = *data_port; + *ps++ = inw_be(port); count--; } pi = (u32 *)ps; while(count >= 2) { u32 w; - w = (*data_port) << 16; - w |= (*data_port); + w = inw_be(port) << 16; + w |= inw_be(port); *pi++ = w; count -= 2; } ps = (u16 *)pi; if(count) - *ps++ = *data_port; + *ps++ = inw_be(port); __flush_dcache_range((unsigned long)dst, end); } +static __inline__ void outw_be(unsigned short w, unsigned long addr) +{ + __asm__ __volatile__("stha %0, [%1] %2" + : /* no outputs */ + : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); +} + static __inline__ void ide_outsw(unsigned long port, const void *src, unsigned long count) { - volatile unsigned short *data_port; unsigned long end = (unsigned long)src + (count << 1); const u16 *ps = src; const u32 *pi; - data_port = (volatile unsigned short *)port; - if(((u64)src) & 0x2) { - *data_port = *ps++; + outw_be(*ps++, port); count--; } pi = (const u32 *)ps; @@ -185,13 +198,13 @@ static __inline__ void ide_outsw(unsigned long port, u32 w; w = *pi++; - *data_port = (w >> 16); - *data_port = w; + outw_be((w >> 16), port); + outw_be(w, port); count -= 2; } ps = (const u16 *)pi; if(count) - *data_port = *ps; + outw_be(*ps, port); __flush_dcache_range((unsigned long)src, end); } diff --git a/include/asm-sparc64/init.h b/include/asm-sparc64/init.h index 4aec3125a..17d215574 100644 --- a/include/asm-sparc64/init.h +++ b/include/asm-sparc64/init.h @@ -1,16 +1 @@ -#ifndef _SPARC_INIT_H -#define _SPARC_INIT_H - -#define __init __attribute__ ((__section__ (".text.init"))) -#define __initdata __attribute__ ((__section__ (".data.init"))) -#define __initfunc(__arginit) \ - __arginit __init; \ - __arginit -/* For assembly routines */ -#define __INIT .section ".text.init",#alloc,#execinstr -#define __FINIT .previous -#define __INITDATA .section ".data.init",#alloc,#write - -#define __cacheline_aligned __attribute__ ((aligned (64))) - -#endif +#error "<asm/init.h> should never be used - use <linux/init.h> instead" diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index c80345840..254babf91 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -1,4 +1,4 @@ -/* $Id: io.h,v 1.20 1999/05/14 07:23:18 davem Exp $ */ +/* $Id: io.h,v 1.24 1999/09/06 01:17:54 davem Exp $ */ #ifndef __SPARC64_IO_H #define __SPARC64_IO_H @@ -16,9 +16,6 @@ #define PCI_DVMA_HASHSZ 256 -extern unsigned long pci_dvma_offset; -extern unsigned long pci_dvma_mask; - extern unsigned long pci_dvma_v2p_hash[PCI_DVMA_HASHSZ]; extern unsigned long pci_dvma_p2v_hash[PCI_DVMA_HASHSZ]; @@ -49,11 +46,13 @@ extern __inline__ void *phys_to_virt(unsigned long addr) #define virt_to_bus virt_to_phys #define bus_to_virt phys_to_virt -extern __inline__ unsigned long bus_dvma_to_mem(unsigned long vaddr) -{ - return vaddr & pci_dvma_mask; -} +/* Different PCI controllers we support have their PCI MEM space + * mapped to an either 2GB (Psycho) or 4GB (Sabre) aligned area, + * so need to chop off the top 33 or 32 bits. + */ +extern unsigned long pci_memspace_mask; +#define bus_dvma_to_mem(__vaddr) ((__vaddr) & pci_memspace_mask) extern __inline__ unsigned int inb(unsigned long addr) { @@ -61,7 +60,7 @@ extern __inline__ unsigned int inb(unsigned long addr) __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) - : "r" (addr), "i" (ASI_PL)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); return ret; } @@ -72,7 +71,7 @@ extern __inline__ unsigned int inw(unsigned long addr) __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) - : "r" (addr), "i" (ASI_PL)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); return ret; } @@ -83,7 +82,7 @@ extern __inline__ unsigned int inl(unsigned long addr) __asm__ __volatile__("lduwa [%1] %2, %0" : "=r" (ret) - : "r" (addr), "i" (ASI_PL)); + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); return ret; } @@ -92,21 +91,21 @@ extern __inline__ void outb(unsigned char b, unsigned long addr) { __asm__ __volatile__("stba %0, [%1] %2" : /* no outputs */ - : "r" (b), "r" (addr), "i" (ASI_PL)); + : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } extern __inline__ void outw(unsigned short w, unsigned long addr) { __asm__ __volatile__("stha %0, [%1] %2" : /* no outputs */ - : "r" (w), "r" (addr), "i" (ASI_PL)); + : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } extern __inline__ void outl(unsigned int l, unsigned long addr) { __asm__ __volatile__("stwa %0, [%1] %2" : /* no outputs */ - : "r" (l), "r" (addr), "i" (ASI_PL)); + : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); } #define inb_p inb @@ -120,12 +119,66 @@ extern void insw(unsigned long addr, void *dst, unsigned long count); extern void insl(unsigned long addr, void *dst, unsigned long count); /* Memory functions, same as I/O accesses on Ultra. */ -#define readb(addr) inb((unsigned long)(addr)) -#define readw(addr) inw((unsigned long)(addr)) -#define readl(addr) inl((unsigned long)(addr)) -#define writeb(b, addr) outb((b), (unsigned long)(addr)) -#define writew(w, addr) outw((w), (unsigned long)(addr)) -#define writel(l, addr) outl((l), (unsigned long)(addr)) +extern __inline__ unsigned int _readb(unsigned long addr) +{ + unsigned int ret; + + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + + return ret; +} + +extern __inline__ unsigned int _readw(unsigned long addr) +{ + unsigned int ret; + + __asm__ __volatile__("lduha [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + + return ret; +} + +extern __inline__ unsigned int _readl(unsigned long addr) +{ + unsigned int ret; + + __asm__ __volatile__("lduwa [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); + + return ret; +} + +extern __inline__ void _writeb(unsigned char b, unsigned long addr) +{ + __asm__ __volatile__("stba %0, [%1] %2" + : /* no outputs */ + : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); +} + +extern __inline__ void _writew(unsigned short w, unsigned long addr) +{ + __asm__ __volatile__("stha %0, [%1] %2" + : /* no outputs */ + : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); +} + +extern __inline__ void _writel(unsigned int l, unsigned long addr) +{ + __asm__ __volatile__("stwa %0, [%1] %2" + : /* no outputs */ + : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)); +} + +#define readb(__addr) (_readb((unsigned long)(__addr))) +#define readw(__addr) (_readw((unsigned long)(__addr))) +#define readl(__addr) (_readl((unsigned long)(__addr))) +#define writeb(__b, __addr) (_writeb((__b), (unsigned long)(__addr))) +#define writew(__w, __addr) (_writew((__w), (unsigned long)(__addr))) +#define writel(__l, __addr) (_writel((__l), (unsigned long)(__addr))) /* * Memcpy to/from I/O space is just a regular memory operation on @@ -190,19 +243,11 @@ out: return retval; } -/* - * On the sparc we have the whole physical IO address space mapped at all - * times, so ioremap() and iounmap() do not need to do anything. +/* On sparc64 we have the whole physical IO address space accessible + * using physically addressed loads and stores, so this does nothing. */ -extern __inline__ void *ioremap(unsigned long offset, unsigned long size) -{ - return __va(offset); -} - -extern __inline__ void iounmap(void *addr) -{ -} - +#define ioremap(__offset, __size) ((void *)(__offset)) +#define iounmap(__addr) do { } while(0) extern void sparc_ultra_mapioaddr(unsigned long physaddr, unsigned long virt_addr, diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h index d74f3fc85..9c21b9dc3 100644 --- a/include/asm-sparc64/iommu.h +++ b/include/asm-sparc64/iommu.h @@ -5,9 +5,9 @@ #ifndef _SPARC64_IOMMU_H #define _SPARC64_IOMMU_H +#include <linux/spinlock.h> #include <asm/page.h> #include <asm/sysio.h> -#include <asm/spinlock.h> /* The iommu handles all virtual to physical address translations * that occur between the SYSIO and physical memory. Access by @@ -39,7 +39,8 @@ #define IOPTE_64K 0x2000000000000000 /* IOPTE is for 64k page */ #define IOPTE_STBUF 0x1000000000000000 /* DVMA can use streaming buffer */ #define IOPTE_INTRA 0x0800000000000000 /* SBUS slot-->slot direct transfer */ -#define IOPTE_PAGE 0x000001ffffffe000 /* Physical page number (PA[40:13]) */ +#define IOPTE_CONTEXT 0x07ff800000000000 /* Context number */ +#define IOPTE_PAGE 0x00007fffffffe000 /* Physical page number (PA[40:13]) */ #define IOPTE_CACHE 0x0000000000000010 /* Cached (in UPA E-cache) */ #define IOPTE_WRITE 0x0000000000000002 /* Writeable */ diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index bad6a838a..045ae8bc9 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -1,4 +1,4 @@ -/* $Id: irq.h,v 1.14 1998/12/19 11:05:41 davem Exp $ +/* $Id: irq.h,v 1.16 1999/09/06 01:17:52 davem Exp $ * irq.h: IRQ registers on the 64-bit Sparc. * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) @@ -61,19 +61,27 @@ struct ino_bucket { /*0x08*/void *irq_info; /* Sun5 Interrupt Clear Register. */ -/*0x10*/unsigned int *iclr; +/*0x10*/volatile unsigned int *iclr; /* Sun5 Interrupt Mapping Register. */ -/*0x18*/unsigned int *imap; +/*0x18*/volatile unsigned int *imap; }; +/* Only 8-bits are available, be careful. -DaveM */ +#define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */ +#define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */ +#define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */ +#define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */ + #define NUM_IVECS 8192 extern struct ino_bucket ivector_table[NUM_IVECS]; #define __irq_ino(irq) \ (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil +#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) +#define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) static __inline__ char *__irq_itoa(unsigned int irq) { @@ -86,10 +94,11 @@ static __inline__ char *__irq_itoa(unsigned int irq) #define NR_IRQS 15 extern void disable_irq(unsigned int); +#define disable_irq_nosync disable_irq extern void enable_irq(unsigned int); extern void init_timers(void (*lvl10_irq)(int, void *, struct pt_regs *), unsigned long *); -extern unsigned int build_irq(int pil, int inofixup, unsigned int *iclr, unsigned int *imap); +extern unsigned int build_irq(int pil, int inofixup, volatile unsigned int *iclr, volatile unsigned int *imap); extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); extern unsigned int psycho_build_irq(void *psycho, int imap_off, int ino, int need_dma_sync); diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h index c9f984418..e19335be7 100644 --- a/include/asm-sparc64/mmu_context.h +++ b/include/asm-sparc64/mmu_context.h @@ -1,129 +1,147 @@ -/* $Id: mmu_context.h,v 1.36 1999/05/25 16:53:34 jj Exp $ */ +/* $Id: mmu_context.h,v 1.40 1999/09/10 10:44:37 davem Exp $ */ #ifndef __SPARC64_MMU_CONTEXT_H #define __SPARC64_MMU_CONTEXT_H /* Derived heavily from Linus's Alpha/AXP ASN code... */ +#include <linux/spinlock.h> #include <asm/system.h> #include <asm/spitfire.h> -#include <asm/spinlock.h> - -#define NO_CONTEXT 0 #ifndef __ASSEMBLY__ +extern spinlock_t ctx_alloc_lock; extern unsigned long tlb_context_cache; extern unsigned long mmu_context_bmap[]; #define CTX_VERSION_SHIFT (PAGE_SHIFT - 3) #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT) #define CTX_FIRST_VERSION ((1UL << CTX_VERSION_SHIFT) + 1UL) +#define CTX_VALID(__ctx) \ + (!(((__ctx) ^ tlb_context_cache) & CTX_VERSION_MASK)) +#define CTX_HWBITS(__ctx) ((__ctx) & ~CTX_VERSION_MASK) extern void get_new_mmu_context(struct mm_struct *mm); -/* Initialize/destroy the context related info for a new mm_struct - * instance. +/* Initialize a new mmu context. This is invoked when a new + * address space instance (unique or shared) is instantiated. + * A fresh mm_struct is cleared out to zeros, so this need not + * do anything on Sparc64 since the only thing we care about + * is that mm->context is an invalid context (ie. zero). */ -#define init_new_context(__mm) ((__mm)->context = NO_CONTEXT) - -/* Kernel threads like rpciod and nfsd drop their mm, and then use - * init_mm, when this happens we must make sure the secondary context is - * updated as well. Otherwise we have disasters relating to - * set_fs/get_fs usage later on. - * - * Also we can only clear the mmu_context_bmap bit when this is - * the final reference to the address space. +#define init_new_context(__tsk, __mm) do { } while(0) + +/* Destroy a dead context. This occurs when mmput drops the + * mm_users count to zero, the mmaps have been released, and + * all the page tables have been flushed. Our job is to destroy + * any remaining processor-specific state, and in the sparc64 + * case this just means freeing up the mmu context ID held by + * this task if valid. */ -#define destroy_context(__mm) do { \ - if ((__mm)->context != NO_CONTEXT && \ - atomic_read(&(__mm)->count) == 1) { \ - if (!(((__mm)->context ^ tlb_context_cache) & CTX_VERSION_MASK))\ - clear_bit((__mm)->context & ~(CTX_VERSION_MASK), \ - mmu_context_bmap); \ - (__mm)->context = NO_CONTEXT; \ - if(current->mm == (__mm)) { \ - current->tss.ctx = 0; \ - spitfire_set_secondary_context(0); \ - __asm__ __volatile__("flush %g6"); \ - } \ - } \ -} while (0) - -/* The caller must flush the current set of user windows - * to the stack (if necessary) before we get here. +#define destroy_context(__mm) \ +do { spin_lock(&ctx_alloc_lock); \ + if (CTX_VALID((__mm)->context)) { \ + unsigned long nr = CTX_HWBITS((__mm)->context); \ + mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \ + } \ + spin_unlock(&ctx_alloc_lock); \ +} while(0) + +/* Reload the two core values used by TLB miss handler + * processing on sparc64. They are: + * 1) The physical address of mm->pgd, when full page + * table walks are necessary, this is where the + * search begins. + * 2) A "PGD cache". For 32-bit tasks only pgd[0] is + * ever used since that maps the entire low 4GB + * completely. To speed up TLB miss processing we + * make this value available to the handlers. This + * decreases the amount of memory traffic incurred. */ -extern __inline__ void __get_mmu_context(struct task_struct *tsk) +#define reload_tlbmiss_state(__tsk, __mm) \ +do { \ + register unsigned long paddr asm("o5"); \ + register unsigned long pgd_cache asm("o4"); \ + paddr = __pa((__mm)->pgd); \ + pgd_cache = 0UL; \ + if ((__tsk)->thread.flags & SPARC_FLAG_32BIT) \ + pgd_cache = pgd_val((__mm)->pgd[0]) << 11UL; \ + __asm__ __volatile__("wrpr %%g0, 0x494, %%pstate\n\t" \ + "mov %3, %%g4\n\t" \ + "mov %0, %%g7\n\t" \ + "stxa %1, [%%g4] %2\n\t" \ + "wrpr %%g0, 0x096, %%pstate" \ + : /* no outputs */ \ + : "r" (paddr), "r" (pgd_cache),\ + "i" (ASI_DMMU), "i" (TSB_REG)); \ +} while(0) + +/* Set MMU context in the actual hardware. */ +#define load_secondary_context(__mm) \ + __asm__ __volatile__("stxa %0, [%1] %2\n\t" \ + "flush %%g6" \ + : /* No outputs */ \ + : "r" (CTX_HWBITS((__mm)->context)), \ + "r" (0x10), "i" (0x58)) + +/* Clean out potential stale TLB entries due to previous + * users of this TLB context. We flush TLB contexts + * lazily on sparc64. + */ +#define clean_secondary_context() \ + __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" \ + "stxa %%g0, [%0] %2\n\t" \ + "flush %%g6" \ + : /* No outputs */ \ + : "r" (0x50), "i" (0x5f), "i" (0x57)) + +/* Switch the current MM context. */ +static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu) { - register unsigned long paddr asm("o5"); - register unsigned long pgd_cache asm("o4"); - struct mm_struct *mm = tsk->mm; - unsigned long asi; - - if(!(tsk->tss.flags & SPARC_FLAG_KTHREAD) && - !(tsk->flags & PF_EXITING)) { - unsigned long ctx = tlb_context_cache; - if((mm->context ^ ctx) & CTX_VERSION_MASK) + long dirty; + + spin_lock(&mm->page_table_lock); + if (CTX_VALID(mm->context)) + dirty = 0; + else + dirty = 1; + if (dirty || (old_mm != mm)) { + unsigned long vm_mask; + + if (dirty) get_new_mmu_context(mm); - tsk->tss.ctx = mm->context & 0x3ff; - spitfire_set_secondary_context(mm->context & 0x3ff); - __asm__ __volatile__("flush %g6"); - if(!(mm->cpu_vm_mask & (1UL<<smp_processor_id()))) { - spitfire_flush_dtlb_secondary_context(); - spitfire_flush_itlb_secondary_context(); - __asm__ __volatile__("flush %g6"); + + vm_mask = (1UL << cpu); + if (!(mm->cpu_vm_mask & vm_mask)) { + mm->cpu_vm_mask |= vm_mask; + dirty = 1; } - asi = tsk->tss.current_ds.seg; - } else { - tsk->tss.ctx = 0; - spitfire_set_secondary_context(0); - __asm__ __volatile__("flush %g6"); - asi = ASI_P; + + load_secondary_context(mm); + if (dirty != 0) + clean_secondary_context(); + reload_tlbmiss_state(tsk, mm); } - /* Sigh, damned include loops... just poke seg directly. */ - __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" (asi)); - paddr = __pa(mm->pgd); - if((tsk->tss.flags & (SPARC_FLAG_32BIT|SPARC_FLAG_KTHREAD)) == - (SPARC_FLAG_32BIT)) - pgd_cache = ((unsigned long) mm->pgd[0]) << 11UL; - else - pgd_cache = 0; - __asm__ __volatile__(" - rdpr %%pstate, %%o2 - andn %%o2, %2, %%o3 - wrpr %%o3, %5, %%pstate - mov %4, %%g4 - mov %0, %%g7 - stxa %1, [%%g4] %3 - wrpr %%o2, 0x0, %%pstate - " : /* no outputs */ - : "r" (paddr), "r" (pgd_cache), "i" (PSTATE_IE), - "i" (ASI_DMMU), "i" (TSB_REG), "i" (PSTATE_MG) - : "o2", "o3"); + spin_unlock(&mm->page_table_lock); } -/* Now we define this as a do nothing macro, because the only - * generic user right now is the scheduler, and we handle all - * the atomicity issues by having switch_to() call the above - * function itself. - */ -#define get_mmu_context(x) do { } while(0) - -/* - * After we have set current->mm to a new value, this activates - * the context for the new mm so we see the new mappings. Currently, - * this is always called for 'current', if that changes put appropriate - * checks here. - * - * We set the cpu_vm_mask first to zero to enforce a tlb flush for - * the new context above, then we set it to the current cpu so the - * smp tlb flush routines do not get confused. - */ -#define activate_context(__tsk) \ -do { flushw_user(); \ - (__tsk)->mm->cpu_vm_mask = 0; \ - __get_mmu_context(__tsk); \ - (__tsk)->mm->cpu_vm_mask = (1UL<<smp_processor_id()); \ -} while(0) +/* Activate a new MM instance for the current task. */ +static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm) +{ + unsigned long vm_mask; + + spin_lock(&mm->page_table_lock); + if (!CTX_VALID(mm->context)) + get_new_mmu_context(mm); + vm_mask = (1UL << smp_processor_id()); + if (!(mm->cpu_vm_mask & vm_mask)) + mm->cpu_vm_mask |= vm_mask; + spin_unlock(&mm->page_table_lock); + + load_secondary_context(mm); + clean_secondary_context(); + reload_tlbmiss_state(current, mm); +} #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/mostek.h b/include/asm-sparc64/mostek.h index e956a9565..e153a36cf 100644 --- a/include/asm-sparc64/mostek.h +++ b/include/asm-sparc64/mostek.h @@ -1,4 +1,4 @@ -/* $Id: mostek.h,v 1.2 1997/03/25 03:58:30 davem Exp $ +/* $Id: mostek.h,v 1.3 1999/08/30 10:14:50 davem Exp $ * mostek.h: Describes the various Mostek time of day clock registers. * * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) @@ -35,22 +35,38 @@ /* The Mostek 48t02 real time clock and NVRAM chip. The registers * other than the control register are in binary coded decimal. Some * control bits also live outside the control register. + * + * We now deal with physical addresses for I/O to the chip. -DaveM */ - -struct mostek48t02 { - volatile char eeprom[2008]; /* This is the eeprom, don't touch! */ - struct idprom idprom; /* The idprom lives here. */ - volatile unsigned char creg; /* Control register */ - volatile unsigned char sec; /* Seconds (0-59) */ - volatile unsigned char min; /* Minutes (0-59) */ - volatile unsigned char hour; /* Hour (0-23) */ - volatile unsigned char dow; /* Day of the week (1-7) */ - volatile unsigned char dom; /* Day of the month (1-31) */ - volatile unsigned char month; /* Month of year (1-12) */ - volatile unsigned char year; /* Year (0-99) */ -}; - -extern struct mostek48t02 *mstk48t02_regs; +static __inline__ u8 mostek_read(unsigned long addr) +{ + u8 ret; + + __asm__ __volatile__("lduba [%1] %2, %0" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + return ret; +} + +static __inline__ void mostek_write(unsigned long addr, u8 val) +{ + __asm__ __volatile__("stba %0, [%1] %2" + : /* no outputs */ + : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); +} + +#define MOSTEK_EEPROM 0x0000UL +#define MOSTEK_IDPROM 0x07d8UL +#define MOSTEK_CREG 0x07f8UL +#define MOSTEK_SEC 0x07f9UL +#define MOSTEK_MIN 0x07faUL +#define MOSTEK_HOUR 0x07fbUL +#define MOSTEK_DOW 0x07fcUL +#define MOSTEK_DOM 0x07fdUL +#define MOSTEK_MONTH 0x07feUL +#define MOSTEK_YEAR 0x07ffUL + +extern unsigned long mstk48t02_regs; /* Control register values. */ #define MSTK_CREG_WRITE 0x80 /* Must set this before placing values. */ @@ -79,48 +95,51 @@ extern struct mostek48t02 *mstk48t02_regs; #define MSTK_DECIMAL_TO_REGVAL(x) ((((x) / 0x0A) << 0x04) + ((x) % 0x0A)) /* Generic register set and get macros for internal use. */ -#define MSTK_GET(regs,var,mask) (MSTK_REGVAL_TO_DECIMAL(regs->var & MSTK_ ## mask ## _MASK)) -#define MSTK_SET(regs,var,value,mask) do { regs->var &= ~(MSTK_ ## mask ## _MASK); regs->var |= MSTK_DECIMAL_TO_REGVAL(value) & (MSTK_ ## mask ## _MASK); } while (0) +#define MSTK_GET(regs,name) \ + (MSTK_REGVAL_TO_DECIMAL(mostek_read(regs + MOSTEK_ ## name) & MSTK_ ## name ## _MASK)) +#define MSTK_SET(regs,name,value) \ +do { u8 __val = mostek_read(regs + MOSTEK_ ## name); \ + __val &= ~(MSTK_ ## name ## _MASK); \ + __val |= (MSTK_DECIMAL_TO_REGVAL(value) & \ + (MSTK_ ## name ## _MASK)); \ + mostek_write(regs + MOSTEK_ ## name, __val); \ +} while(0) /* Macros to make register access easier on our fingers. These give you * the decimal value of the register requested if applicable. You pass * the a pointer to a 'struct mostek48t02'. */ -#define MSTK_REG_CREG(regs) (regs->creg) -#define MSTK_REG_SEC(regs) MSTK_GET(regs,sec,SEC) -#define MSTK_REG_MIN(regs) MSTK_GET(regs,min,MIN) -#define MSTK_REG_HOUR(regs) MSTK_GET(regs,hour,HOUR) -#define MSTK_REG_DOW(regs) MSTK_GET(regs,dow,DOW) -#define MSTK_REG_DOM(regs) MSTK_GET(regs,dom,DOM) -#define MSTK_REG_MONTH(regs) MSTK_GET(regs,month,MONTH) -#define MSTK_REG_YEAR(regs) MSTK_GET(regs,year,YEAR) - -#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,sec,value,SEC) -#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,min,value,MIN) -#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,hour,value,HOUR) -#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,dow,value,DOW) -#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,dom,value,DOM) -#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,month,value,MONTH) -#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,year,value,YEAR) +#define MSTK_REG_CREG(regs) (mostek_read((regs) + MOSTEK_CREG)) +#define MSTK_REG_SEC(regs) MSTK_GET(regs,SEC) +#define MSTK_REG_MIN(regs) MSTK_GET(regs,MIN) +#define MSTK_REG_HOUR(regs) MSTK_GET(regs,HOUR) +#define MSTK_REG_DOW(regs) MSTK_GET(regs,DOW) +#define MSTK_REG_DOM(regs) MSTK_GET(regs,DOM) +#define MSTK_REG_MONTH(regs) MSTK_GET(regs,MONTH) +#define MSTK_REG_YEAR(regs) MSTK_GET(regs,YEAR) + +#define MSTK_SET_REG_SEC(regs,value) MSTK_SET(regs,SEC,value) +#define MSTK_SET_REG_MIN(regs,value) MSTK_SET(regs,MIN,value) +#define MSTK_SET_REG_HOUR(regs,value) MSTK_SET(regs,HOUR,value) +#define MSTK_SET_REG_DOW(regs,value) MSTK_SET(regs,DOW,value) +#define MSTK_SET_REG_DOM(regs,value) MSTK_SET(regs,DOM,value) +#define MSTK_SET_REG_MONTH(regs,value) MSTK_SET(regs,MONTH,value) +#define MSTK_SET_REG_YEAR(regs,value) MSTK_SET(regs,YEAR,value) /* The Mostek 48t08 clock chip. Found on Sun4m's I think. It has the * same (basically) layout of the 48t02 chip except for the extra * NVRAM on board (8 KB against the 48t02's 2 KB). */ -struct mostek48t08 { - char offset[6*1024]; /* Magic things may be here, who knows? */ - struct mostek48t02 regs; /* Here is what we are interested in. */ -}; -extern struct mostek48t08 *mstk48t08_regs; +#define MOSTEK_48T08_OFFSET 0x0000UL /* Lower NVRAM portions */ +#define MOSTEK_48T08_48T02 0x1800UL /* Offset to 48T02 chip */ +extern unsigned long mstk48t08_regs; /* SUN5 systems usually have 48t59 model clock chipsets. But we keep the older * clock chip definitions around just in case. */ -struct mostek48t59 { - char offset[6*1024]; - struct mostek48t02 regs; -}; -extern struct mostek48t59 *mstk48t59_regs; +#define MOSTEK_48T59_OFFSET 0x0000UL /* Lower NVRAM portions */ +#define MOSTEK_48T59_48T02 0x1800UL /* Offset to 48T02 chip */ +extern unsigned long mstk48t59_regs; #endif /* !(_SPARC64_MOSTEK_H) */ diff --git a/include/asm-sparc64/oplib.h b/include/asm-sparc64/oplib.h index 52e55758a..f0ca1df71 100644 --- a/include/asm-sparc64/oplib.h +++ b/include/asm-sparc64/oplib.h @@ -1,4 +1,4 @@ -/* $Id: oplib.h,v 1.10 1998/12/18 10:02:03 davem Exp $ +/* $Id: oplib.h,v 1.11 1999/08/31 19:25:49 davem Exp $ * oplib.h: Describes the interface and available routines in the * Linux Prom library. * @@ -205,7 +205,8 @@ extern int prom_wakeupsystem(void); /* MMU and memory related OBP interfaces. */ /* Get unique string identifying SIMM at given physical address. */ -extern int prom_getunumber(unsigned long phys_lo, unsigned long phys_hi, +extern int prom_getunumber(int syndrome_code, + unsigned long phys_addr, char *buf, int buflen); /* Retain physical memory to the caller across soft resets. */ @@ -336,6 +337,7 @@ extern long p1275_cmd (char *, long, ...); #define P1275_ARG_OUT_32B 3 #define P1275_ARG_IN_FUNCTION 4 #define P1275_ARG_IN_BUF 5 +#define P1275_ARG_IN_64B 6 #define P1275_IN(x) ((x) & 0xf) #define P1275_OUT(x) (((x) << 4) & 0xf0) diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index 1a808c0ba..1e89c16e6 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h @@ -1,4 +1,4 @@ -/* $Id: page.h,v 1.24 1998/10/20 03:09:16 jj Exp $ */ +/* $Id: page.h,v 1.27 1999/07/31 00:07:25 davem Exp $ */ #ifndef _SPARC64_PAGE_H #define _SPARC64_PAGE_H @@ -18,9 +18,8 @@ #ifndef __ASSEMBLY__ -#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0) -#define PAGE_BUG(page) do { \ - BUG(); } while (0) +#define BUG() __builtin_trap() +#define PAGE_BUG(page) BUG() extern void clear_page(unsigned long page); extern void copy_page(unsigned long to, unsigned long from); @@ -85,7 +84,7 @@ typedef unsigned long iopgprot_t; #endif /* (STRICT_MM_TYPECHECKS) */ -#define TASK_UNMAPPED_BASE ((current->tss.flags & SPARC_FLAG_32BIT) ? \ +#define TASK_UNMAPPED_BASE ((current->thread.flags & SPARC_FLAG_32BIT) ? \ (0x0000000070000000UL) : (PAGE_OFFSET)) #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/parport.h b/include/asm-sparc64/parport.h new file mode 100644 index 000000000..67a0da1fa --- /dev/null +++ b/include/asm-sparc64/parport.h @@ -0,0 +1,182 @@ +/* $Id: parport.h,v 1.5 1999/08/30 10:14:52 davem Exp $ + * parport.h: sparc64 specific parport initialization and dma. + * + * Copyright (C) 1999 Eddie C. Dost (ecd@skynet.be) + */ + +#ifndef _ASM_SPARC64_PARPORT_H +#define _ASM_SPARC64_PARPORT_H 1 + +#include <linux/config.h> +#include <asm/ebus.h> +#include <asm/ns87303.h> + +#ifdef CONFIG_PARPORT_PC_PCMCIA +#define __maybe_init +#define __maybe_initdata +#else +#define __maybe_init __init +#define __maybe_initdata __initdata +#endif + +#undef HAVE_SLOW_DEVICES + +#define PARPORT_PC_MAX_PORTS PARPORT_MAX + +static struct linux_ebus_dma *sparc_ebus_dmas[PARPORT_PC_MAX_PORTS]; + +static __inline__ void +reset_dma(unsigned int dmanr) +{ + unsigned int dcsr; + + writel(EBUS_DCSR_RESET, &sparc_ebus_dmas[dmanr]->dcsr); + udelay(1); + dcsr = EBUS_DCSR_BURST_SZ_16 | EBUS_DCSR_TCI_DIS | + EBUS_DCSR_EN_CNT; + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); +} + +static __inline__ void +enable_dma(unsigned int dmanr) +{ + unsigned int dcsr; + + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + dcsr |= EBUS_DCSR_EN_DMA; + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); +} + +static __inline__ void +disable_dma(unsigned int dmanr) +{ + unsigned int dcsr; + + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + if (dcsr & EBUS_DCSR_EN_DMA) { + while (dcsr & EBUS_DCSR_DRAIN) { + udelay(1); + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + } + dcsr &= ~(EBUS_DCSR_EN_DMA); + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); + + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + if (dcsr & EBUS_DCSR_ERR_PEND) { + reset_dma(dmanr); + dcsr &= ~(EBUS_DCSR_ERR_PEND); + } + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); + } +} + +static __inline__ void +clear_dma_ff(unsigned int dmanr) +{ + /* nothing */ +} + +static __inline__ void +set_dma_mode(unsigned int dmanr, char mode) +{ + unsigned int dcsr; + + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + dcsr |= EBUS_DCSR_EN_CNT | EBUS_DCSR_TC; + if (mode == DMA_MODE_WRITE) + dcsr &= ~(EBUS_DCSR_WRITE); + else + dcsr |= EBUS_DCSR_WRITE; + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); +} + +static __inline__ void +set_dma_addr(unsigned int dmanr, unsigned int addr) +{ + writel(addr, &sparc_ebus_dmas[dmanr]->dacr); +} + +static __inline__ void +set_dma_count(unsigned int dmanr, unsigned int count) +{ + writel(count, &sparc_ebus_dmas[dmanr]->dbcr); +} + +static __inline__ int +get_dma_residue(unsigned int dmanr) +{ + unsigned int dcsr; + int res; + + res = readl(&sparc_ebus_dmas[dmanr]->dbcr); + if (res != 0) { + dcsr = readl(&sparc_ebus_dmas[dmanr]->dcsr); + reset_dma(dmanr); + writel(dcsr, &sparc_ebus_dmas[dmanr]->dcsr); + } + return res; +} + +static int __maybe_init parport_pc_init_pci(int irq, int dma); + +static int user_specified __initdata = 0; + +int __init +parport_pc_init(int *io, int *io_hi, int *irq, int *dma) +{ + struct linux_ebus *ebus; + struct linux_ebus_device *edev; + int count = 0; + + if (!pci_present()) + return 0; + + for_each_ebus(ebus) { + for_each_ebusdev(edev, ebus) { + if (!strcmp(edev->prom_name, "ecpp")) { + unsigned long base = edev->resource[0].start; + unsigned long config = edev->resource[1].start; + unsigned char cfg; + + sparc_ebus_dmas[count] = + (struct linux_ebus_dma *) + edev->resource[2].start; + reset_dma(count); + + /* Enable ECP, set bit 2 of the CTR first */ + outb(0x04, base + 0x02); + cfg = ns87303_readb(config, PCR); + cfg |= (PCR_ECP_ENABLE | PCR_ECP_CLK_ENA); + ns87303_writeb(config, PCR, cfg); + + /* CTR bit 5 controls direction of port */ + cfg = ns87303_readb(config, PTR); + cfg |= PTR_LPT_REG_DIR; + ns87303_writeb(config, PTR, cfg); + + /* Configure IRQ to Push Pull, Level Low */ + cfg = ns87303_readb(config, PCR); + cfg &= ~(PCR_IRQ_ODRAIN); + cfg |= PCR_IRQ_POLAR; + ns87303_writeb(config, PCR, cfg); + +#ifndef HAVE_SLOW_DEVICES + /* Enable Zero Wait State for ECP */ + cfg = ns87303_readb(config, FCR); + cfg |= FCR_ZWS_ENA; + ns87303_writeb(config, FCR, cfg); +#endif + + if (parport_pc_probe_port(base, base + 0x400, + edev->irqs[0], + count)) + count++; + } + } + } + + count += parport_pc_init_pci(PARPORT_IRQ_AUTO, PARPORT_DMA_NONE); + return count; +} + +#endif /* !(_ASM_SPARC64_PARPORT_H */ diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h index 4f0f51f30..1f740c845 100644 --- a/include/asm-sparc64/pbm.h +++ b/include/asm-sparc64/pbm.h @@ -1,34 +1,92 @@ -/* $Id: pbm.h,v 1.16 1999/03/14 18:13:03 davem Exp $ - * pbm.h: U2P PCI bus module pseudo driver software state. +/* $Id: pbm.h,v 1.18 1999/09/10 10:44:40 davem Exp $ + * pbm.h: UltraSparc PCI controller software state. * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) + * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) */ #ifndef __SPARC64_PBM_H #define __SPARC64_PBM_H +#include <linux/types.h> #include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/spinlock.h> -#include <asm/psycho.h> +#include <asm/io.h> +#include <asm/page.h> #include <asm/oplib.h> -struct linux_pbm_info; +/* The abstraction used here is that there are PCI controllers, + * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules + * underneath. Each PCI controller has a single IOMMU shared + * by the PCI bus modules underneath, and if a streaming buffer + * is present, each PCI bus module has it's own. (ie. the IOMMU + * is shared between PBMs, the STC is not) Furthermore, each + * PCI bus module controls it's own autonomous PCI bus. + */ + +struct pci_controller_info; -/* This is what we use to determine what the PROM has assigned so - * far, so that we can perform assignments for addresses which - * were not taken care of by OBP. See psycho.c for details. - * Per-PBM these are ordered by start address. +/* This contains the software state necessary to drive a PCI + * controller's IOMMU. */ -struct pci_vma { - struct pci_vma *next; - struct linux_pbm_info *pbm; - unsigned int start; - unsigned int end; - unsigned int offset; - unsigned int _pad; +struct pci_iommu { + /* This protects the controller's IOMMU and all + * streaming buffers underneath. + */ + spinlock_t lock; + + /* Context allocator. */ + unsigned int iommu_cur_ctx; + + /* IOMMU page table, a linear array of ioptes. */ + iopte_t *page_table; /* The page table itself. */ + int page_table_sz; /* How many pages does it map? */ + + /* Base PCI memory space address where IOMMU mappings + * begin. + */ + u32 page_table_map_base; + + /* IOMMU Controller Registers */ + int iommu_has_ctx_flush; /* Feature test. */ + unsigned long iommu_control; /* IOMMU control register */ + unsigned long iommu_tsbbase; /* IOMMU page table base register */ + unsigned long iommu_flush; /* IOMMU page flush register */ + unsigned long iommu_ctxflush; /* IOMMU context flush register */ + + /* This is a register in the PCI controller, which if + * read will have no side-effects but will guarentee + * completion of all previous writes into IOMMU/STC. + */ + unsigned long write_complete_reg; }; -struct linux_psycho; +/* This describes a PCI bus module's streaming buffer. */ +struct pci_strbuf { + int strbuf_enabled; /* Present and using it? */ + int strbuf_has_ctx_flush; /* Supports context flushing? */ + + /* Streaming Buffer Control Registers */ + unsigned long strbuf_control; /* STC control register */ + unsigned long strbuf_pflush; /* STC page flush register */ + unsigned long strbuf_fsync; /* STC flush synchronization reg */ + unsigned long strbuf_ctxflush; /* STC context flush register */ + unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */ + unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */ + volatile unsigned long *strbuf_flushflag; /* The flush flag itself */ + + /* And this is the actual flush flag area. + * We allocate extra because the chips require + * a 64-byte aligned area. + */ + volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)]; +}; + +#define PCI_STC_FLUSHFLAG_INIT(STC) \ + (*((STC)->strbuf_flushflag) = 0UL) +#define PCI_STC_FLUSHFLAG_SET(STC) \ + (*((STC)->strbuf_flushflag) != 0UL) /* There can be quite a few ranges and interrupt maps on a PCI * segment. Thus... @@ -36,10 +94,14 @@ struct linux_psycho; #define PROM_PCIRNG_MAX 64 #define PROM_PCIIMAP_MAX 64 -struct linux_pbm_info { - struct linux_psycho *parent; - struct pci_vma *IO_assignments; - struct pci_vma *MEM_assignments; +struct pci_pbm_info { + /* PCI controller we sit under. */ + struct pci_controller_info *parent; + + /* Name used for top-level resources. */ + char name[64]; + + /* OBP specific information. */ int prom_node; char prom_name[64]; struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX]; @@ -48,27 +110,54 @@ struct linux_pbm_info { int num_pbm_intmap; struct linux_prom_pci_intmask pbm_intmask; + /* PBM I/O and Memory space resources. */ + struct resource io_space; + struct resource mem_space; + + /* This PBM's streaming buffer. */ + struct pci_strbuf stc; + /* Now things for the actual PCI bus probes. */ unsigned int pci_first_busno; unsigned int pci_last_busno; - struct pci_bus pci_bus; + struct pci_bus *pci_bus; }; -struct linux_psycho { - struct linux_psycho *next; - struct psycho_regs *psycho_regs; - unsigned long *pci_config_space; - unsigned long *pci_IO_space; - unsigned long *pci_mem_space; - u32 upa_portid; +struct pci_controller_info { + /* List of all PCI controllers. */ + struct pci_controller_info *next; + + /* Physical address base of controller registers + * and PCI config space. + */ + unsigned long controller_regs; + unsigned long config_space; + + /* Opaque 32-bit system bus Port ID. */ + u32 portid; + + /* Each controller gets a unique index, used mostly for + * error logging purposes. + */ int index; - struct linux_pbm_info pbm_A; - struct linux_pbm_info pbm_B; + + /* The PCI bus modules controlled by us. */ + struct pci_pbm_info pbm_A; + struct pci_pbm_info pbm_B; + + /* Operations which are controller specific. */ + void (*scan_bus)(struct pci_controller_info *); + unsigned int (*irq_build)(struct pci_controller_info *, struct pci_dev *, unsigned int); + void (*base_address_update)(struct pci_dev *, int); + void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *); /* Now things for the actual PCI bus probes. */ + struct pci_ops *pci_ops; unsigned int pci_first_busno; unsigned int pci_last_busno; - struct pci_bus *pci_bus; + + /* IOMMU state shared by both PBM segments. */ + struct pci_iommu iommu; void *starfire_cookie; }; @@ -78,17 +167,19 @@ struct linux_psycho { * code. */ struct pcidev_cookie { - struct linux_pbm_info *pbm; + struct pci_pbm_info *pbm; + char prom_name[64]; int prom_node; + struct linux_prom_pci_registers prom_regs[PROMREG_MAX]; + int num_prom_regs; + struct linux_prom_pci_registers prom_assignments[PROMREG_MAX]; + int num_prom_assignments; }; - -#define PCI_IRQ_IGN 0x000007c0 /* PSYCHO "Int Group Number". */ -#define PCI_IRQ_INO 0x0000003f /* PSYCHO INO. */ - -/* Used by EBus */ -extern unsigned int psycho_irq_build(struct linux_pbm_info *pbm, - struct pci_dev *pdev, - unsigned int full_ino); +/* Currently these are the same across all PCI controllers + * we support. Someday they may not be... + */ +#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */ +#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */ #endif /* !(__SPARC64_PBM_H) */ diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h new file mode 100644 index 000000000..6d1558daf --- /dev/null +++ b/include/asm-sparc64/pci.h @@ -0,0 +1,44 @@ +#ifndef __SPARC64_PCI_H +#define __SPARC64_PCI_H + +#include <asm/scatterlist.h> + +/* Can be used to override the logic in pci_scan_bus for skipping + * already-configured bus numbers - to be used for buggy BIOSes + * or architectures with incomplete PCI setup by the loader. + */ +#define pcibios_assign_all_busses() 0 + +/* Map kernel buffer using consistant mode DMA for PCI device. + * Returns a 32-bit PCI DMA address. + */ +extern u32 pci_map_consistant(struct pci_dev *, void *, int); + +/* Unmap a consistant DMA translation. */ +extern void pci_unmap_consistant(struct pci_dev *, u32, int); + +/* Map a single buffer for PCI DMA in streaming mode. */ +extern u32 pci_map_single(struct pci_dev *, void *, int); + +/* Unmap a single streaming mode DMA translation. */ +extern void pci_unmap_single(struct pci_dev *, u32, int); + +/* Map a set of buffers described by scatterlist in streaming + * mode for PCI DMA. + */ +extern void pci_map_sg(struct pci_dev *, struct scatterlist *, int); + +/* Unmap a set of streaming mode DMA translations. */ +extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int); + +/* Make physical memory consistant for a single + * streaming mode DMA translation after a transfer. + */ +extern void pci_dma_sync_single(struct pci_dev *, u32, int); + +/* Make physical memory consistant for a set of streaming + * mode DMA translations after a transfer. + */ +extern void pci_dma_sync_sg(struct pci_dev *, struct scatterlist *, int); + +#endif /* __SPARC64_PCI_H */ diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index d3a8ec9a2..5b31257da 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -1,4 +1,4 @@ -/* $Id: pgtable.h,v 1.105 1999/05/27 04:52:51 davem Exp $ +/* $Id: pgtable.h,v 1.110 1999/08/30 10:14:57 davem Exp $ * pgtable.h: SpitFire page table operations. * * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) @@ -47,14 +47,14 @@ * is different so we can optimize correctly for 32-bit tasks. */ #define REAL_PTRS_PER_PMD (1UL << (PAGE_SHIFT-2)) -#define PTRS_PER_PMD ((const int)((current->tss.flags & SPARC_FLAG_32BIT) ? \ +#define PTRS_PER_PMD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \ (REAL_PTRS_PER_PMD >> 2) : (REAL_PTRS_PER_PMD))) /* We cannot use the top 16G because VPTE table lives there. */ #define PTRS_PER_PGD ((1UL << (PAGE_SHIFT-3))-1) /* Kernel has a separate 44bit address space. */ -#define USER_PTRS_PER_PGD ((const int)((current->tss.flags & SPARC_FLAG_32BIT) ? \ +#define USER_PTRS_PER_PGD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \ (1) : (PTRS_PER_PGD))) #define PTE_TABLE_SIZE 0x2000 /* 1024 entries 8 bytes each */ @@ -167,9 +167,12 @@ extern void *sparc_init_alloc(unsigned long *kbrk, unsigned long size); /* Cache and TLB flush operations. */ /* These are the same regardless of whether this is an SMP kernel or not. */ -#define flush_cache_mm(mm) flushw_user() -#define flush_cache_range(mm, start, end) flushw_user() -#define flush_cache_page(vma, page) flushw_user() +#define flush_cache_mm(__mm) \ + do { if ((__mm) == current->mm) flushw_user(); } while(0) +#define flush_cache_range(mm, start, end) \ + flush_cache_mm(mm) +#define flush_cache_page(vma, page) \ + flush_cache_mm((vma)->vm_mm) /* These operations are unnecessary on the SpitFire since D-CACHE is write-through. */ #define flush_icache_range(start, end) do { } while (0) @@ -191,16 +194,16 @@ extern void __flush_tlb_page(unsigned long context, unsigned long page, unsigned #define flush_cache_all() __flush_cache_all() #define flush_tlb_all() __flush_tlb_all() -#define flush_tlb_mm(mm) \ -do { if((mm)->context != NO_CONTEXT) \ - __flush_tlb_mm((mm)->context & 0x3ff, SECONDARY_CONTEXT); \ +#define flush_tlb_mm(__mm) \ +do { if(CTX_VALID((__mm)->context)) \ + __flush_tlb_mm(CTX_HWBITS((__mm)->context), SECONDARY_CONTEXT); \ } while(0) -#define flush_tlb_range(mm, start, end) \ -do { if((mm)->context != NO_CONTEXT) { \ +#define flush_tlb_range(__mm, start, end) \ +do { if(CTX_VALID((__mm)->context)) { \ unsigned long __start = (start)&PAGE_MASK; \ unsigned long __end = (end)&PAGE_MASK; \ - __flush_tlb_range((mm)->context & 0x3ff, __start, \ + __flush_tlb_range(CTX_HWBITS((__mm)->context), __start, \ SECONDARY_CONTEXT, __end, PAGE_SIZE, \ (__end - __start)); \ } \ @@ -208,8 +211,8 @@ do { if((mm)->context != NO_CONTEXT) { \ #define flush_tlb_page(vma, page) \ do { struct mm_struct *__mm = (vma)->vm_mm; \ - if(__mm->context != NO_CONTEXT) \ - __flush_tlb_page(__mm->context & 0x3ff, (page)&PAGE_MASK, \ + if(CTX_VALID(__mm->context)) \ + __flush_tlb_page(CTX_HWBITS(__mm->context), (page)&PAGE_MASK, \ SECONDARY_CONTEXT); \ } while(0) @@ -227,14 +230,14 @@ extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page); extern __inline__ void flush_tlb_mm(struct mm_struct *mm) { - if(mm->context != NO_CONTEXT) + if (CTX_VALID(mm->context)) smp_flush_tlb_mm(mm); } extern __inline__ void flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) { - if(mm->context != NO_CONTEXT) + if (CTX_VALID(mm->context)) smp_flush_tlb_range(mm, start, end); } @@ -242,7 +245,7 @@ extern __inline__ void flush_tlb_page(struct vm_area_struct *vma, unsigned long { struct mm_struct *mm = vma->vm_mm; - if(mm->context != NO_CONTEXT) + if (CTX_VALID(mm->context)) smp_flush_tlb_page(mm, page); } @@ -520,34 +523,13 @@ extern int do_check_pgt_cache(int, int); #define set_pgdir(address, entry) do { } while(0) extern pgd_t swapper_pg_dir[1]; - -extern inline void SET_PAGE_DIR(struct task_struct *tsk, pgd_t *pgdir) -{ - if(pgdir != swapper_pg_dir && tsk == current) { - register unsigned long paddr asm("o5"); - - paddr = __pa(pgdir); - __asm__ __volatile__ (" - rdpr %%pstate, %%o4 - wrpr %%o4, %1, %%pstate - mov %3, %%g4 - mov %0, %%g7 - stxa %%g0, [%%g4] %2 - wrpr %%o4, 0x0, %%pstate - " : /* No outputs */ - : "r" (paddr), "i" (PSTATE_MG|PSTATE_IE), - "i" (ASI_DMMU), "i" (TSB_REG) - : "o4"); - flush_tlb_mm(current->mm); - } -} - /* Routines for getting a dvma scsi buffer. */ struct mmu_sglist { char *addr; char *__dont_touch; unsigned int len; __u32 dvma_addr; + __u32 dvma_len; }; extern __u32 mmu_get_scsi_one(char *, unsigned long, struct linux_sbus *sbus); diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 855be2e88..d5074144d 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -1,4 +1,4 @@ -/* $Id: processor.h,v 1.55 1999/05/27 04:52:54 davem Exp $ +/* $Id: processor.h,v 1.57 1999/08/04 03:20:05 davem Exp $ * include/asm-sparc64/processor.h * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) @@ -47,66 +47,61 @@ typedef struct { /* The Sparc processor specific thread struct. */ struct thread_struct { -/*DC1*/ unsigned long ksp __attribute__ ((aligned(16))); - unsigned short wstate; - unsigned short cwp; - unsigned short flags; + /* D$ line 1 */ + unsigned long ksp __attribute__ ((aligned(16))); + unsigned char wstate, cwp, flags; mm_segment_t current_ds; - -/*DC2*/ unsigned short w_saved; - unsigned short new_signal; - unsigned short ctx; - struct pt_regs *kregs; - -/*DC3*/ unsigned long *utraps; - unsigned char fpdepth; + unsigned char w_saved, fpdepth; unsigned char fpsaved[7]; + unsigned char __pad1[3]; + struct pt_regs *kregs; + + /* D$ line 2 */ + unsigned long *utraps; + unsigned char gsr[7]; + unsigned char __pad2; + unsigned long sig_address; + unsigned long sig_desc; -/*DC4*/ unsigned char gsr[7]; + /* D$ lines 3 and 4 */ unsigned long xfsr[7]; + unsigned long __pad3; - struct reg_window reg_window[NSWINS] __attribute__ ((aligned (16))); - unsigned long rwbuf_stkptrs[NSWINS] __attribute__ ((aligned (8))); - - unsigned long sig_address __attribute__ ((aligned (8))); - unsigned long sig_desc; + struct reg_window reg_window[NSWINS]; + unsigned long rwbuf_stkptrs[NSWINS]; /* Performance counter state */ u64 *user_cntd0, *user_cntd1; u64 kernel_cntd0, kernel_cntd1; u64 pcr_reg; - }; #endif /* !(__ASSEMBLY__) */ -#define SPARC_FLAG_KTHREAD 0x010 /* task is a kernel thread */ -#define SPARC_FLAG_UNALIGNED 0x020 /* is allowed to do unaligned accesses */ -#define SPARC_FLAG_NEWSIGNALS 0x040 /* task wants new-style signals */ -#define SPARC_FLAG_32BIT 0x080 /* task is older 32-bit binary */ -#define SPARC_FLAG_NEWCHILD 0x100 /* task is just-spawned child process */ -#define SPARC_FLAG_PERFCTR 0x200 /* task has performance counters active */ +#define SPARC_FLAG_UNALIGNED 0x01 /* is allowed to do unaligned accesses */ +#define SPARC_FLAG_NEWSIGNALS 0x02 /* task wants new-style signals */ +#define SPARC_FLAG_32BIT 0x04 /* task is older 32-bit binary */ +#define SPARC_FLAG_NEWCHILD 0x08 /* task is just-spawned child process */ +#define SPARC_FLAG_PERFCTR 0x10 /* task has performance counters active */ #define INIT_MMAP { &init_mm, 0xfffff80000000000, 0xfffff80001000000, \ NULL, PAGE_SHARED , VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } -#define INIT_TSS { \ -/* ksp, wstate, cwp, flags, current_ds, */ \ - 0, 0, 0, SPARC_FLAG_KTHREAD, KERNEL_DS, \ -/* w_saved, new_signal, ctx, kregs, */ \ - 0, 0, 0, 0, \ -/* utraps, */ \ - 0, \ -/* fpdepth, fpsaved, gsr, xfsr */ \ - 0, { 0 }, { 0 }, { 0 }, \ -/* reg_window */ \ - { { { 0, }, { 0, } }, }, \ -/* rwbuf_stkptrs */ \ - { 0, 0, 0, 0, 0, 0, 0, }, \ -/* sig_address, sig_desc */ \ - 0, 0, \ +#define INIT_THREAD { \ +/* ksp, wstate, cwp, flags, current_ds, */ \ + 0, 0, 0, 0, KERNEL_DS, \ +/* w_saved, fpdepth, fpsaved, pad1, kregs, */ \ + 0, 0, { 0 }, { 0 }, 0, \ +/* utraps, gsr, pad2, sig_address, sig_desc, */ \ + 0, { 0 }, 0, 0, 0, \ +/* xfsr, pad3, */ \ + { 0 }, 0, \ +/* reg_window */ \ + { { { 0, }, { 0, } }, }, \ +/* rwbuf_stkptrs */ \ + { 0, 0, 0, 0, 0, 0, 0, }, \ /* user_cntd0, user_cndd1, kernel_cntd0, kernel_cntd0, pcr_reg */ \ - 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, \ } #ifndef __ASSEMBLY__ @@ -134,14 +129,13 @@ do { \ regs->tpc = ((pc & (~3)) - 4); \ regs->tnpc = regs->tpc + 4; \ regs->y = 0; \ - current->tss.flags &= ~SPARC_FLAG_32BIT; \ - current->tss.wstate = (1 << 3); \ - if (current->tss.utraps) { \ - if (*(current->tss.utraps) < 2) \ - kfree (current->tss.utraps); \ + current->thread.wstate = (1 << 3); \ + if (current->thread.utraps) { \ + if (*(current->thread.utraps) < 2) \ + kfree (current->thread.utraps); \ else \ - (*(current->tss.utraps))--; \ - current->tss.utraps = NULL; \ + (*(current->thread.utraps))--; \ + current->thread.utraps = NULL; \ } \ __asm__ __volatile__( \ "stx %%g0, [%0 + %2 + 0x00]\n\t" \ @@ -175,17 +169,15 @@ do { \ regs->tpc = ((pc & (~3)) - 4); \ regs->tnpc = regs->tpc + 4; \ regs->y = 0; \ - current->tss.flags |= SPARC_FLAG_32BIT; \ - current->tss.wstate = (2 << 3); \ - if (current->tss.utraps) { \ - if (*(current->tss.utraps) < 2) \ - kfree (current->tss.utraps); \ + current->thread.wstate = (2 << 3); \ + if (current->thread.utraps) { \ + if (*(current->thread.utraps) < 2) \ + kfree (current->thread.utraps); \ else \ - (*(current->tss.utraps))--; \ - current->tss.utraps = NULL; \ + (*(current->thread.utraps))--; \ + current->thread.utraps = NULL; \ } \ __asm__ __volatile__( \ - "stxa %3, [%4] %5\n\t" \ "stx %%g0, [%0 + %2 + 0x00]\n\t" \ "stx %%g0, [%0 + %2 + 0x08]\n\t" \ "stx %%g0, [%0 + %2 + 0x10]\n\t" \ @@ -205,19 +197,20 @@ do { \ "wrpr %%g0, (2 << 3), %%wstate\n\t" \ : \ : "r" (regs), "r" (sp - REGWIN32_SZ), \ - "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0])), \ - "r" (((unsigned long)current->mm->pgd[0])<<11UL), \ - "r" (TSB_REG), "i" (ASI_DMMU)); \ + "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \ } while(0) /* Free all resources held by a thread. */ #define release_thread(tsk) do { } while(0) -#define copy_segments(nr, tsk, mm) do { } while (0) +extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +#define copy_segments(tsk, mm) do { } while (0) #define release_segments(mm) do { } while (0) #define forget_segments() do { } while (0) #ifdef __KERNEL__ +#define THREAD_SIZE (2*PAGE_SIZE) /* Allocation and freeing of task_struct and kernel stack. */ #define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL, 1)) #define free_task_struct(tsk) free_pages((unsigned long)(tsk),1) diff --git a/include/asm-sparc64/psycho.h b/include/asm-sparc64/psycho.h deleted file mode 100644 index 0833bf0eb..000000000 --- a/include/asm-sparc64/psycho.h +++ /dev/null @@ -1,400 +0,0 @@ -/* $Id: psycho.h,v 1.5 1999/04/01 12:27:28 davem Exp $ - * psycho.h: UltraSparc AX specific PCI definitions. - * - * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) - */ - -#ifndef __SPARC64_PSYCHO_H -#define __SPARC64_PSYCHO_H - -#include <linux/types.h> - -/* Ultra AX PSYCHO Register Set, one per controller probed. */ -struct psycho_regs { -/*0x0000*/ u64 upa_id; /* PSYCHO UPA Port ID Register */ -/*0x0008*/ u64 upa_cfg; /* PSYCHO UPA Config Register */ -/*0x0010*/ u64 control; /* PSYCHO Control Register */ -/*0x0018*/ u64 __pad0; -/*0x0020*/ u64 ecc_control; /* ECC Control Register */ -/*0x0028*/ u64 __pad1; - - /* Uncorrectable Error Fault Registers */ -/*0x0030*/ u64 ue_afsr; /* UE Async Fault Status */ -/*0x0038*/ u64 ue_afar; /* UE Async Fault Address */ - - /* Correctable Error Fault Registers */ -/*0x0040*/ u64 ce_afsr; /* CE Async Fault Status */ -/*0x0048*/ u64 ce_afar; /* CE Async Fault Address */ - - u64 __pad2[0x16]; - - /* Performance Monitoring Registers */ -/*0x0100*/ u64 pmon_control; -/*0x0108*/ u64 pmon_counter; - - u64 __pad3[0x1e]; - - /* PCI Bus IOMMU lives here */ -/*0x0200*/ u64 iommu_control; /* IOMMU Control */ -/*0x0208*/ u64 iommu_tsbbase; /* IOMMU TSB Base */ -/*0x0210*/ u64 iommu_flush; /* IOMMU Flush Register */ - - u64 __pad4[0x13d]; - - /* Interrupt mapping/control registers */ -/*0x0c00*/ u64 imap_a_slot0; /* PCI A Slot 0 Int Mapping */ -/*0x0c08*/ u64 imap_a_slot1; /* PCI A Slot 1 Int Mapping */ -/*0x0c10*/ u64 imap_a_slot2; /* PCI A Slot 2 Int Mapping (IIi only)*/ -/*0x0c18*/ u64 imap_a_slot3; /* PCI A Slot 3 Int Mapping (IIi only)*/ - -/*0x0c20*/ u64 imap_b_slot0; /* PCI B Slot 0 Int Mapping */ -/*0x0c28*/ u64 imap_b_slot1; /* PCI B Slot 1 Int Mapping */ -/*0x0c30*/ u64 imap_b_slot2; /* PCI B Slot 2 Int Mapping */ -/*0x0c38*/ u64 imap_b_slot3; /* PCI B Slot 3 Int Mapping */ - - u64 __pad6[0x78]; - -/*0x1000*/ u64 imap_scsi; /* SCSI Int Mapping */ -/*0x1008*/ u64 imap_eth; /* Ethernet Int Mapping */ -/*0x1010*/ u64 imap_bpp; /* Parallel Port Int Mapping */ -/*0x1018*/ u64 imap_au_rec; /* Audio Record Int Mapping */ -/*0x1020*/ u64 imap_au_play; /* Audio Playback Int Mapping */ -/*0x1028*/ u64 imap_pfail; /* Power Fail Int Mapping */ -/*0x1030*/ u64 imap_kms; /* Kbd/Mouse/Ser Int Mapping */ -/*0x1038*/ u64 imap_flpy; /* Floppy Int Mapping */ -/*0x1040*/ u64 imap_shw; /* Spare HW Int Mapping */ -/*0x1048*/ u64 imap_kbd; /* Kbd Only Int Mapping */ -/*0x1050*/ u64 imap_ms; /* Mouse Only Int Mapping */ -/*0x1058*/ u64 imap_ser; /* Serial Only Int Mapping */ -/*0x1060*/ u64 imap_tim0; /* Timer 0 Int Mapping */ -/*0x1068*/ u64 imap_tim1; /* Timer 1 Int Mapping */ -/*0x1070*/ u64 imap_ue; /* UE Int Mapping */ -/*0x1078*/ u64 imap_ce; /* CE Int Mapping */ -/*0x1080*/ u64 imap_a_err; /* PCI A Err Int Mapping */ -/*0x1088*/ u64 imap_b_err; /* PCI B Err Int Mapping */ -/*0x1090*/ u64 imap_pmgmt; /* Power Mgmt Int Mapping */ -/*0x1098*/ u64 imap_gfx; /* OB Graphics Int Mapping */ -/*0x10a0*/ u64 imap_eupa; /* UPA Expansion Int Mapping */ - - u64 __pad7[0x6b]; - - /* Interrupt Clear Registers */ -/*0x1400*/ u64 iclr_a_slot0[4]; /* PCI A Slot 0 Clear Int Reg */ -/*0x1420*/ u64 iclr_a_slot1[4]; /* PCI A Slot 1 Clear Int Reg */ -/*0x1440*/ u64 iclr_a_slot2[4]; /* PCI A Slot 2 Clear Int Reg */ -/*0x1460*/ u64 iclr_a_slot3[4]; /* PCI A Slot 3 Clear Int Reg */ - -/*0x1480*/ u64 iclr_b_slot0[4]; /* PCI B Slot 0 Clear Int Reg */ -/*0x14a0*/ u64 iclr_b_slot1[4]; /* PCI B Slot 1 Clear Int Reg */ -/*0x14c0*/ u64 iclr_b_slot2[4]; /* PCI B Slot 2 Clear Int Reg */ -/*0x14e0*/ u64 iclr_b_slot3[4]; /* PCI B Slot 3 Clear Int Reg */ - - u64 __pad9[0x60]; - -/*0x1800*/ u64 iclr_scsi; -/*0x1808*/ u64 iclr_eth; -/*0x1810*/ u64 iclr_bpp; -/*0x1818*/ u64 iclr_au_rec; -/*0x1820*/ u64 iclr_au_play; -/*0x1828*/ u64 iclr_pfail; -/*0x1830*/ u64 iclr_kms; -/*0x1838*/ u64 iclr_flpy; -/*0x1840*/ u64 iclr_shw; -/*0x1848*/ u64 iclr_kbd; -/*0x1850*/ u64 iclr_ms; -/*0x1858*/ u64 iclr_ser; -/*0x1860*/ u64 iclr_tim0; -/*0x1868*/ u64 iclr_tim1; -/*0x1870*/ u64 iclr_ue; -/*0x1878*/ u64 iclr_ce; -/*0x1880*/ u64 iclr_a_err; -/*0x1888*/ u64 iclr_b_err; -/*0x1890*/ u64 iclr_pmgmt; - - u64 __pad10[0x2d]; - - /* Interrupt Retry Timer. */ -/*0x1a00*/ u64 irq_retry; - - u64 __pad11[0x3f]; - - /* Counters/Timers */ -/*0x1c00*/ u64 tim0_cnt; -/*0x1c08*/ u64 tim0_lim; -/*0x1c10*/ u64 tim1_cnt; -/*0x1c18*/ u64 tim1_lim; -/*0x1c20*/ u64 pci_dma_wsync; /* PCI DMA Write Sync Register (IIi) */ - - u64 __pad12[0x7b]; - - /* PCI Bus A Registers */ -/*0x2000*/ u64 pci_a_control; /* PCI Bus A Control Register */ -/*0x2008*/ u64 __pad13; -/*0x2010*/ u64 pci_a_afsr; /* PCI Bus A Async Fault Status */ -/*0x2018*/ u64 pci_a_afar; /* PCI Bus A Async Fault Address*/ -/*0x2020*/ u64 pci_a_diag; /* PCI Bus A Diag Register */ -/*0x2028*/ u64 pci_tasr; /* PCI Target Address Space Reg (IIi) */ - - u64 __pad14[0xfa]; - - /* PCI Bus A/IOMMU Streaming Buffer Registers */ -/*0x2800*/ u64 sbuf_a_control; /* StrBuffer Control */ -/*0x2808*/ u64 sbuf_a_pflush; /* StrBuffer Page Flush */ -/*0x2810*/ u64 sbuf_a_fsync; /* StrBuffer Flush Sync Reg */ - - u64 __pad15[0x2fd]; - - /* PCI Bus B Registers */ -/*0x4000*/ u64 pci_b_control; /* PCI Bus B Control Register */ -/*0x4008*/ u64 __pad16; -/*0x4010*/ u64 pci_b_afsr; /* PCI Bus B Async Fault Status */ -/*0x4018*/ u64 pci_b_afar; /* PCI Bus B Async Fault Address*/ -/*0x4020*/ u64 pci_b_diag; /* PCI Bus B Diag Register */ - - u64 __pad17[0x7b]; - - /* IOMMU diagnostic things */ -/*0x4400*/ u64 iommu_vdiag; /* VADDR Diagnostic Register */ -/*0x4408*/ u64 iommu_tcompare; /* IOMMU TLB Tag Compare */ - - u64 __pad18[0x7e]; - - /* PCI Bus B/IOMMU Streaming Buffer Registers */ -/*0x4800*/ u64 sbuf_b_control; /* StrBuffer Control */ -/*0x4808*/ u64 sbuf_b_pflush; /* StrBuffer Page Flush */ -/*0x4810*/ u64 sbuf_b_fsync; /* StrBuffer Flush Sync Reg */ - - u64 __pad19[0xafd]; - - /* DMA Scoreboard Diagnostic Registers */ -/*0xa000*/ u64 dscore_reg0; /* DMA Scoreboard Diag Reg 0 */ -/*0xa008*/ u64 dscore_reg1; /* DMA Scoreboard Diag Reg 1 */ - - u64 __pad20[0x9e]; - - /* More IOMMU diagnostic things */ -/*0xa500*/ u64 iommu_lru[16]; /* IOMMU LRU Queue Diag */ -/*0xa580*/ u64 iommu_tag[16]; /* IOMMU TLB Tag Diag */ -/*0xa600*/ u64 iommu_data[16]; /* IOMMU TLB Data RAM Diag */ - - u64 __pad21[0x30]; - - /* Interrupt State Diagnostics */ -/*0xa800*/ u64 pci_istate; -/*0xa808*/ u64 obio_istate; - - u64 __pad22[0xfe]; - - /* Streaming Buffer A Diagnostic Area */ -/*0xb000*/ u64 sbuf_a_data[128]; /* StrBuffer Data Ram Diag */ -/*0xb400*/ u64 sbuf_a_errs[128]; /* StrBuffer Error Status Diag*/ -/*0xb800*/ u64 sbuf_a_ptag[16]; /* StrBuffer Page Tag Diag */ -/*0xb880*/ u64 __pad23[16]; -/*0xb900*/ u64 sbuf_a_ltag[16]; /* StrBuffer Line Tag Diag */ - - u64 __pad24[0xd0]; - - /* Streaming Buffer B Diagnostic Area */ -/*0xc000*/ u64 sbuf_b_data[128]; /* StrBuffer Data Ram Diag */ -/*0xc400*/ u64 sbuf_b_errs[128]; /* StrBuffer Error Status Diag*/ -/*0xc800*/ u64 sbuf_b_ptag[16]; /* StrBuffer Page Tag Diag */ -/*0xc880*/ u64 __pad25[16]; -/*0xc900*/ u64 sbuf_b_ltag[16]; /* StrBuffer Line Tag Diag */ -}; - -/* PSYCHO UPA Port ID */ -#define PSYCHO_UPPID_FESC 0xff00000000000000 /* FCode escape, 0xfc */ -#define PSYCHO_UPPID_RESV1 0x00fffff800000000 /* Reserved */ -#define PSYCHO_UPPID_ENV 0x0000000400000000 /* Cannot generate ECC */ -#define PSYCHO_UPPID_ORD 0x0000000200000000 /* One Outstanding Read */ -#define PSYCHO_UPPID_RESV2 0x0000000180000000 /* Reserved */ -#define PSYCHO_UPPID_PDQ 0x000000007e000000 /* Data Queue size */ -#define PSYCHO_UPPID_PRQ 0x0000000001e00000 /* Request Queue size */ -#define PSYCHO_UPPID_UCAP 0x00000000001f0000 /* UPA Capabilities */ -#define PSYCHO_UPPID_JEDEC 0x000000000000ffff /* JEDEC ID for PSYCHO */ - -/* PSYCHO UPA Configuration Register */ -#define PSYCHO_UPCFG_RESV 0xffffffffffffff00 /* Reserved */ -#define PSYCHO_UPCFG_SCIQ1 0x00000000000000f0 /* Unused, always zero */ -#define PSYCHO_UPCFG_SCIQ2 0x000000000000000f /* Requests Queue size 0x2 */ - -/* PSYCHO Control Register */ -#define PSYCHO_CONTROL_IMPL 0xf000000000000000 /* Implementation of this PSYCHO*/ -#define PSYCHO_CONTROL_VER 0x0f00000000000000 /* Version of this PSYCHO */ -#define PSYCHO_CONTROL_MID 0x00f8000000000000 /* UPA Module ID of PSYCHO */ -#define PSYCHO_CONTROL_IGN 0x0007c00000000000 /* Interrupt Group Number */ -#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0 /* Reserved */ -#define PSYCHO_CONTROL_APCKEN 0x0000000000000008 /* Address Parity Check Enable */ -#define PSYCHO_CONTROL_APERR 0x0000000000000004 /* Incoming System Addr Parerr */ -#define PSYCHO_CONTROL_IAP 0x0000000000000002 /* Invert UPA Parity */ -#define PSYCHO_CONTROL_MODE 0x0000000000000001 /* PSYCHO clock mode */ - -/* PSYCHO ECC Control Register */ -#define PSYCHO_ECNTRL_ECCEN 0x8000000000000000 /* Enable ECC Checking */ -#define PSYCHO_ECNTRL_UEEN 0x4000000000000000 /* Enable UE Interrupts */ -#define PSYCHO_ECNTRL_CEEN 0x2000000000000000 /* Enable CE Interrupts */ - -/* Uncorrectable Error AFSR, AFAR holds low 40bits of faulting physical address. */ -#define PSYCHO_UEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */ -#define PSYCHO_UEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */ -#define PSYCHO_UEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */ -#define PSYCHO_UEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */ -#define PSYCHO_UEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */ -#define PSYCHO_UEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/ -#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000 /* Reserved */ -#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */ -#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000 /* Doubleword Offset */ -#define PSYCHO_UEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */ -#define PSYCHO_UEAFSR_BLK 0x0000000000800000 /* Trans was block operation */ -#define PSYCHO_UEAFSR_RESV2 0x00000000007fffff /* Reserved */ - -/* Correctable Error AFSR, AFAR holds low 40bits of faulting physical address. */ -#define PSYCHO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */ -#define PSYCHO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */ -#define PSYCHO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */ -#define PSYCHO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */ -#define PSYCHO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */ -#define PSYCHO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/ -#define PSYCHO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */ -#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */ -#define PSYCHO_CEAFSR_SIZE 0x0000ffff00000000 /* Bytemask of failed transfer */ -#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000 /* Double Offset */ -#define PSYCHO_CEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */ -#define PSYCHO_CEAFSR_BLK 0x0000000000800000 /* Trans was block operation */ -#define PSYCHO_CEAFSR_RESV2 0x00000000007fffff /* Reserved */ - -/* PSYCHO Performance Monitor Register, the counter holds 2 32-bit event counters. */ -#define PSYCHO_PMCTRL_RESV3 0xffffffffffff0000 /* Reserved */ -#define PSYCHO_PMCTRL_CLR1 0x0000000000008000 /* Clear SEL1 counter */ -#define PSYCHO_PMCTRL_RESV2 0x0000000000006000 /* Reserved */ -#define PSYCHO_PMCTRL_SEL1 0x0000000000001f00 /* Event source 1 */ -#define PSYCHO_PMCTRL_CLR0 0x0000000000000080 /* Clear SEL0 counter */ -#define PSYCHO_PMCTRL_RESV1 0x0000000000000060 /* Reserved */ -#define PSYCHO_PMCTRL_SEL0 0x000000000000001f /* Event source 0 */ - -/* SEL0/SEL1 each can take any one of the following values. */ -#define PMCTRL_SEL_NSDRA 0x00 /* # of streaming dvma reads for PCI A */ -#define PMCTRL_SEL_NSDWA 0x01 /* # of streaming dvma writes for PCI A */ -#define PMCTRL_SEL_NCDRA 0x02 /* # of consistent dvma reads for PCI A */ -#define PMCTRL_SEL_NCDWA 0x03 /* # of consistent dvma writes for PCI A */ -#define PMCTRL_SEL_SBMA 0x04 /* # of streaming buffer misses on PCI A */ -#define PMCTRL_SEL_DCGA 0x05 /* # of DVMA granted cycles on PCI A */ -#define PMCTRL_SEL_DWTA 0x06 /* # of DVMA words transferred on PCI A */ -#define PMCTRL_SEL_CPIOA 0x07 /* # of PIO cycles used by PSYCHO on PCI A */ -#define PMCTRL_SEL_NSDRB 0x08 /* # of streaming dvma reads for PCI B */ -#define PMCTRL_SEL_NSDWB 0x09 /* # of streaming dvma writes for PCI B */ -#define PMCTRL_SEL_NCDRB 0x0a /* # of consistent dvma reads for PCI B */ -#define PMCTRL_SEL_NCDWB 0x0b /* # of consistent dvma writes for PCI B */ -#define PMCTRL_SEL_SBMB 0x0c /* # of streaming buffer misses on PCI B */ -#define PMCTRL_SEL_DCGB 0x0d /* # of DVMA granted cycles on PCI B */ -#define PMCTRL_SEL_DWTB 0x0e /* # of DVMA words transferred on PCI B */ -#define PMCTRL_SEL_CPIOB 0x0f /* # of PIO cycles used by PSYCHO on PCI B */ -#define PMCTRL_SEL_TMISS 0x10 /* # of IOMMU TLB misses */ -#define PMCTRL_SEL_IRQ 0x11 /* # of interrupts */ -#define PMCTRL_SEL_INACK 0x12 /* # of interrupt NACKs on UPA */ -#define PMCTRL_SEL_PRD 0x13 /* # of PIO reads */ -#define PMCTRL_SEL_PWR 0x14 /* # of PIO writes */ -#define PMCTRL_SEL_MBT 0x15 /* # of Merge Buffer transactions */ -#define PMCTRL_SEL_PDRTA 0x16 /* # of PCI A DVMA tablewalk induced retries */ -#define PMCTRL_SEL_PDRSA 0x17 /* # of PCI A DVMA str buf induced retries */ -#define PMCTRL_SEL_PDRTB 0x18 /* # of PCI B DVMA tablewalk induced retries */ -#define PMCTRL_SEL_PDRSB 0x19 /* # of PCI B DVMA str buf induced retries */ -/* Values 0x1a --> 0x1f are reserved. */ - -/* PSYCHO PCI Control Register */ -#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000 /* Reserved */ -#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000 /* Streaming byte hole error */ -#define PSYCHO_PCICTRL_SERR 0x0000000400000000 /* SERR signal asserted */ -#define PSYCHO_PCICTRL_SPEED 0x0000000200000000 /* PCI speed (1 is U2P clock) */ -#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000 /* Reserved */ -#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ -#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800 /* Reserved */ -#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400 /* Streaming byte hole int enab */ -#define PSYCHO_PCICTRL_WEN 0x0000000000000200 /* Power Mgmt Wake Enable */ -#define PSYCHO_PCICTRL_EEN 0x0000000000000100 /* PCI Error Interrupt Enable */ -#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0 /* Reserved */ -#define PSYCHO_PCICTRL_AEN 0x000000000000003f /* PCI DVMA Arbitration Enable */ - -/* PSYCHO PCI AFSR, AFAR holds low 40 bits of physical address causing the fault. */ -#define PSYCHO_PCIAFSR_PMA 0x8000000000000000 /* Primary Master Abort Error */ -#define PSYCHO_PCIAFSR_PTA 0x4000000000000000 /* Primary Target Abort Error */ -#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000 /* Primary Excessive Retries */ -#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000 /* Primary Parity Error */ -#define PSYCHO_PCIAFSR_SMA 0x0800000000000000 /* Secondary Master Abort Error */ -#define PSYCHO_PCIAFSR_STA 0x0400000000000000 /* Secondary Target Abort Error */ -#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000 /* Secondary Excessive Retries */ -#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000 /* Secondary Parity Error */ -#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000 /* Reserved */ -#define PSYCHO_PCIAFSR_SIZE 0x0000ffff00000000 /* Bytemask of failed transfer */ -#define PSYCHO_PCIAFSR_BLK 0x0000000080000000 /* Trans was block operation */ -#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000 /* Reserved */ -#define PSYCHO_PCIAFSR_MID 0x000000003e000000 /* MID causing the error */ -#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffff /* Reserved */ - -/* PSYCHO Diagnostic Register. */ -#define PSYCHO_PSYDIAG_RESV 0xffffffffffffff80 /* Reserved */ -#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040 /* Disable retry limit */ -#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020 /* Disable DMA wr / irq sync */ -#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010 /* Disable DMA wr / PIO rd sync */ -#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008 /* Invert DMA data parity */ -#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004 /* Invert PIO data parity */ -#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002 /* Invert PIO address parity */ -#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001 /* Enable loopback mode */ - -/* IOMMU things defined fully in asm-sparc64/iommu.h */ - -/* Streaming Buffer Control Register */ -#define PSYCHO_SBUFCTRL_RESV 0xffffffffffffff80 /* Reserved */ -#define PSYCHO_SBUFCTRL_LRU_LP 0x0000000000000070 /* LRU Lock Pointer */ -#define PSYCHO_SBUFCTRL_LRU_LE 0x0000000000000008 /* LRU Lock Enable */ -#define PSYCHO_SBUFCTRL_RR_DIS 0x0000000000000004 /* Rerun Disable */ -#define PSYCHO_SBUFCTRL_DE 0x0000000000000002 /* Diag Mode Enable */ -#define PSYCHO_SBUFCTRL_SB_EN 0x0000000000000001 /* Streaming Buffer Enable */ - -/* Streaming Buffer Page Invalidate/Flush Register */ -#define PSYCHO_SBUFFLUSH_ADDR 0x00000000ffffe000 /* DVMA Page to be flushed */ -#define PSYCHO_SBUFFLUSH_RESV 0x0000000000001fff /* Ignored bits */ - -/* Streaming Buffer Flush Synchronization Register */ -#define PSYCHO_SBUFSYNC_ADDR 0x000001ffffffffc0 /* Physical address to update */ -#define PSYCHO_SBUFSYNC_RESV 0x000000000000003f /* Ignored bits */ - -/* DMA Scoreboard Diagnostic Register(s) */ -#define PSYCHO_DSCORE_VALID 0x8000000000000000 /* Entry is valid */ -#define PSYCHO_DSCORE_C 0x4000000000000000 /* Transaction cacheable */ -#define PSYCHO_DSCORE_READ 0x2000000000000000 /* Transaction was a read */ -#define PSYCHO_DSCORE_TAG 0x1f00000000000000 /* Transaction ID */ -#define PSYCHO_DSCORE_ADDR 0x00fffffffff80000 /* Transaction PADDR */ -#define PSYCHO_DSCORE_BMSK 0x000000000007fff8 /* Bytemask of pending transfer */ -#define PSYCHO_DSCORE_SRC 0x0000000000000007 /* Transaction source */ - -/* PSYCHO Interrupt mapping register(s). */ -#define PSYCHO_IMAP_RESV1 0xffffffff00000000 /* Reserved */ -#define PSYCHO_IMAP_VALID 0x0000000080000000 /* This enables delivery. */ -#define PSYCHO_IMAP_TID 0x000000007c000000 /* Target ID (MID to send it to)*/ -#define PSYCHO_IMAP_RESV2 0x0000000003fff800 /* Reserved */ -#define PSYCHO_IMAP_IGN 0x00000000000007c0 /* Interrupt Group Number. */ -#define PSYCHO_IMAP_INO 0x000000000000003f /* Interrupt Number Offset. */ -#define PSYCHO_IMAP_INR 0x00000000000007ff /* Interrupt # (Gfx/UPA_slave) */ - -/* PSYCHO Interrupt clear pseudo register(s). */ -#define PSYCHO_ICLR_RESV1 0xfffffffffffffff0 /* Reserved */ -#define PSYCHO_ICLR_IDLE 0x0000000000000000 /* Transition to idle state. */ -#define PSYCHO_ICLR_TRANSMIT 0x0000000000000001 /* Transition to transmit state */ -#define PSYCHO_ICLR_RESV2 0x0000000000000002 /* Reserved. */ -#define PSYCHO_ICLR_PENDING 0x0000000000000003 /* Transition to pending state. */ - -/* PSYCHO Interrupt Retry Timer register. */ -#define PSYCHO_IRETRY_LIMIT 0x00000000000fffff /* The retry interval. */ - -/* PSYCHO Interrupt State registers. XXX fields to be documented later */ - -/* PSYCHO Counter register. XXX fields to be documented later */ - -/* PSYCHO Limit register. XXX fields to be documented later */ - -/* PSYCHO Performance Monitor Control register. XXX fields to be documented later */ - -/* PSYCHO Performance Monitor Counter register. XXX fields to be documented later */ - -#endif /* !(__SPARC64_PSYCHO_H) */ diff --git a/include/asm-sparc64/reg.h b/include/asm-sparc64/reg.h index 2aabb1f42..fc68f9018 100644 --- a/include/asm-sparc64/reg.h +++ b/include/asm-sparc64/reg.h @@ -1,4 +1,4 @@ -/* $Id: reg.h,v 1.4 1997/09/14 08:40:29 davem Exp $ +/* $Id: reg.h,v 1.6 1999/09/06 08:22:10 jj Exp $ * linux/asm-sparc64/reg.h * Layout of the registers as expected by gdb on the Sparc * we should replace the user.h definitions with those in @@ -38,6 +38,9 @@ struct regs { unsigned int r_fprs; }; +#define FPU_REGS_TYPE unsigned int +#define FPU_FSR_TYPE unsigned long + struct fp_status { unsigned long fpu_fr[32]; unsigned long Fpu_fsr; @@ -48,5 +51,6 @@ struct fpu { }; #define fpu_regs f_fpstatus.fpu_fr +#define fpu_fsr f_fpstatus.Fpu_fsr #endif /* __SPARC64_REG_H */ diff --git a/include/asm-sparc64/resource.h b/include/asm-sparc64/resource.h index 02ba40894..a8ecef2a7 100644 --- a/include/asm-sparc64/resource.h +++ b/include/asm-sparc64/resource.h @@ -1,4 +1,4 @@ -/* $Id: resource.h,v 1.4 1998/11/19 20:01:49 davem Exp $ +/* $Id: resource.h,v 1.5 1999/07/30 09:31:21 davem Exp $ * resource.h: Resource definitions. * * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) @@ -25,13 +25,13 @@ #define RLIM_NLIMITS 10 #ifdef __KERNEL__ -#define INIT_RLIMITS \ -{ \ - {LONG_MAX, LONG_MAX}, {LONG_MAX, LONG_MAX}, \ - {LONG_MAX, LONG_MAX}, {_STK_LIM, LONG_MAX}, \ - { 0, LONG_MAX}, {LONG_MAX, LONG_MAX}, \ - {NR_OPEN, NR_OPEN}, {MAX_TASKS_PER_USER, MAX_TASKS_PER_USER}, \ - {LONG_MAX, LONG_MAX}, {LONG_MAX, LONG_MAX} \ +#define INIT_RLIMITS \ +{ \ + {LONG_MAX, LONG_MAX}, {LONG_MAX, LONG_MAX}, \ + {LONG_MAX, LONG_MAX}, {_STK_LIM, LONG_MAX}, \ + { 0, LONG_MAX}, {LONG_MAX, LONG_MAX}, \ + {INR_OPEN, INR_OPEN}, {0, 0}, \ + {LONG_MAX, LONG_MAX}, {LONG_MAX, LONG_MAX} \ } #endif /* __KERNEL__ */ diff --git a/include/asm-sparc64/scatterlist.h b/include/asm-sparc64/scatterlist.h index 9811fc06e..d64162a5a 100644 --- a/include/asm-sparc64/scatterlist.h +++ b/include/asm-sparc64/scatterlist.h @@ -1,4 +1,4 @@ -/* $Id: scatterlist.h,v 1.6 1998/12/16 04:33:57 davem Exp $ */ +/* $Id: scatterlist.h,v 1.7 1999/08/30 10:15:01 davem Exp $ */ #ifndef _SPARC64_SCATTERLIST_H #define _SPARC64_SCATTERLIST_H @@ -11,6 +11,7 @@ struct scatterlist { unsigned int length; __u32 dvma_address; /* A place to hang host-specific addresses at. */ + __u32 dvma_length; }; extern unsigned long phys_base; diff --git a/include/asm-sparc64/sigcontext.h b/include/asm-sparc64/sigcontext.h index 4ce040a78..d7128a875 100644 --- a/include/asm-sparc64/sigcontext.h +++ b/include/asm-sparc64/sigcontext.h @@ -1,20 +1,18 @@ -/* $Id: sigcontext.h,v 1.11 1998/10/06 09:28:37 jj Exp $ */ +/* $Id: sigcontext.h,v 1.12 1999/09/06 08:22:09 jj Exp $ */ #ifndef __SPARC64_SIGCONTEXT_H #define __SPARC64_SIGCONTEXT_H +#ifdef __KERNEL__ #include <asm/ptrace.h> - -#define SUNOS_MAXWIN 31 +#endif #ifndef __ASSEMBLY__ -/* SunOS system call sigstack() uses this arg. */ -struct sunos_sigstack { - unsigned int sig_sp; - int onstack_flag; -}; +#ifdef __KERNEL__ + +#define __SUNOS_MAXWIN 31 -/* This is what SunOS does, so shall I. */ +/* This is what SunOS does, so shall I unless we use new 32bit signals or rt signals. */ struct sigcontext32 { int sigc_onstack; /* state to restore */ int sigc_mask; /* sigmask to restore */ @@ -31,44 +29,30 @@ struct sigcontext32 { int sigc_oswins; /* outstanding windows */ /* stack ptrs for each regwin buf */ - unsigned sigc_spbuf[SUNOS_MAXWIN]; + unsigned sigc_spbuf[__SUNOS_MAXWIN]; /* Windows to restore after signal */ - struct reg_window32 sigc_wbuf[SUNOS_MAXWIN]; + struct reg_window32 sigc_wbuf[__SUNOS_MAXWIN]; }; -/* This is what SunOS doesn't, so we have to write this alone. */ -struct sigcontext { - int sigc_onstack; /* state to restore */ - int sigc_mask; /* sigmask to restore */ - unsigned long sigc_sp; /* stack pointer */ - unsigned long sigc_pc; /* program counter */ - unsigned long sigc_npc; /* next program counter */ - unsigned long sigc_psr; /* for condition codes etc */ - unsigned long sigc_g1; /* User uses these two registers */ - unsigned long sigc_o0; /* within the trampoline code. */ - - /* Now comes information regarding the users window set - * at the time of the signal. - */ - int sigc_oswins; /* outstanding windows */ +#endif - /* stack ptrs for each regwin buf */ - char *sigc_spbuf[SUNOS_MAXWIN]; +#ifdef __KERNEL__ - /* Windows to restore after signal */ - struct reg_window sigc_wbuf[SUNOS_MAXWIN]; -}; +/* This is what we use for 32bit new non-rt signals. */ typedef struct { - struct pt_regs32 si_regs; + struct { + unsigned int psr; + unsigned int pc; + unsigned int npc; + unsigned int y; + unsigned int u_regs[16]; /* globals and ins */ + } si_regs; int si_mask; } __siginfo32_t; -typedef struct { - struct pt_regs si_regs; - long si_mask; -} __siginfo_t; +#endif typedef struct { unsigned int si_float_regs [64]; @@ -77,6 +61,30 @@ typedef struct { unsigned long si_fprs; } __siginfo_fpu_t; +/* This is what SunOS doesn't, so we have to write this alone + and do it properly. */ +struct sigcontext { + /* The size of this array has to match SI_MAX_SIZE from siginfo.h */ + char sigc_info[128]; + struct { + unsigned long u_regs[16]; /* globals and ins */ + unsigned long tstate; + unsigned long tpc; + unsigned long tnpc; + unsigned int y; + unsigned int fprs; + } sigc_regs; + __siginfo_fpu_t * sigc_fpu_save; + struct { + void * ss_sp; + int ss_flags; + unsigned long ss_size; + } sigc_stack; + unsigned long sigc_mask; +}; + +#ifdef __KERNEL__ + /* This magic should be in g_upper[0] for all upper parts to be valid. */ #define SIGINFO_EXTRA_V8PLUS_MAGIC 0x130e269 @@ -85,6 +93,8 @@ typedef struct { unsigned int o_upper[8]; } siginfo_extra_v8plus_t; +#endif + #endif /* !(__ASSEMBLY__) */ #endif /* !(__SPARC64_SIGCONTEXT_H) */ diff --git a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h index a23240e66..9e60d6015 100644 --- a/include/asm-sparc64/siginfo.h +++ b/include/asm-sparc64/siginfo.h @@ -57,7 +57,7 @@ typedef struct siginfo { clock_t _stime; } _sigchld; - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ + /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */ struct { void *_addr; /* faulting insn/memory ref. */ int _trapno; /* TRAP # which caused the signal */ @@ -84,7 +84,7 @@ typedef struct siginfo32 { /* kill() */ struct { __kernel_pid_t32 _pid; /* sender's pid */ - __kernel_uid_t32 _uid; /* sender's uid */ + unsigned int _uid; /* sender's uid */ } _kill; /* POSIX.1b timers */ @@ -96,19 +96,20 @@ typedef struct siginfo32 { /* POSIX.1b signals */ struct { __kernel_pid_t32 _pid; /* sender's pid */ - __kernel_uid_t32 _uid; /* sender's uid */ + unsigned int _uid; /* sender's uid */ sigval_t32 _sigval; } _rt; /* SIGCHLD */ struct { __kernel_pid_t32 _pid; /* which child */ - int _status; /* exit code */ + unsigned int _uid; /* sender's uid */ + int _status; /* exit code */ __kernel_clock_t32 _utime; __kernel_clock_t32 _stime; } _sigchld; - /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ + /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */ struct { u32 _addr; /* faulting insn/memory ref. */ int _trapno; @@ -144,6 +145,7 @@ typedef struct siginfo32 { * si_code values * Digital reserves positive values for kernel-generated signals. */ +#define SI_NOINFO 32767 /* no information in siginfo_t */ #define SI_USER 0 /* sent by kill, sigsend, raise */ #define SI_KERNEL 0x80 /* sent by the kernel from somewhere */ #define SI_QUEUE -1 /* sent by sigqueue */ @@ -226,6 +228,12 @@ typedef struct siginfo32 { #define NSIGPOLL 6 /* + * SIGEMT si_codes + */ +#define EMT_TAGOVF 1 /* tag overflow */ +#define NSIGEMT 1 + +/* * sigevent definitions * * It seems likely that SIGEV_THREAD will have to be handled from diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h index ba179564b..463ef3fdd 100644 --- a/include/asm-sparc64/signal.h +++ b/include/asm-sparc64/signal.h @@ -1,4 +1,4 @@ -/* $Id: signal.h,v 1.8 1998/07/29 16:32:39 jj Exp $ */ +/* $Id: signal.h,v 1.9 1999/09/06 08:22:11 jj Exp $ */ #ifndef _ASMSPARC64_SIGNAL_H #define _ASMSPARC64_SIGNAL_H @@ -196,7 +196,7 @@ struct sigstack { /* Type of a signal handler. */ #ifdef __KERNEL__ -typedef void (*__sighandler_t)(int, int, struct sigcontext *, char *); +typedef void (*__sighandler_t)(int, struct sigcontext *); #else typedef void (*__sighandler_t)(int); #endif @@ -219,10 +219,12 @@ struct __new_sigaction32 { __new_sigset_t32 sa_mask; }; +#ifdef __KERNEL__ struct k_sigaction { struct __new_sigaction sa; void *ka_restorer; }; +#endif struct __old_sigaction { __sighandler_t sa_handler; @@ -239,16 +241,18 @@ struct __old_sigaction32 { }; typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - __kernel_size_t ss_size; + void *ss_sp; + int ss_flags; + size_t ss_size; } stack_t; +#ifdef __KERNEL__ typedef struct sigaltstack32 { - u32 ss_sp; - int ss_flags; - __kernel_size_t32 ss_size; + u32 ss_sp; + int ss_flags; + __kernel_size_t32 ss_size; } stack_t32; +#endif #endif /* !(__ASSEMBLY__) */ diff --git a/include/asm-sparc64/smp.h b/include/asm-sparc64/smp.h index c5e99dab3..d20d9f1b4 100644 --- a/include/asm-sparc64/smp.h +++ b/include/asm-sparc64/smp.h @@ -6,7 +6,7 @@ #ifndef _SPARC64_SMP_H #define _SPARC64_SMP_H -#include <linux/tasks.h> +#include <linux/threads.h> #include <asm/asi.h> #ifndef __ASSEMBLY__ diff --git a/include/asm-sparc64/smplock.h b/include/asm-sparc64/smplock.h index 88a9e8bd1..5791e3c7a 100644 --- a/include/asm-sparc64/smplock.h +++ b/include/asm-sparc64/smplock.h @@ -5,7 +5,7 @@ */ #include <linux/sched.h> #include <linux/interrupt.h> -#include <asm/spinlock.h> +#include <linux/spinlock.h> extern spinlock_t kernel_flag; diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h index e8d68eca3..c4e571564 100644 --- a/include/asm-sparc64/spinlock.h +++ b/include/asm-sparc64/spinlock.h @@ -8,78 +8,6 @@ #ifndef __ASSEMBLY__ -#ifndef __SMP__ - -typedef unsigned char spinlock_t; -#define SPIN_LOCK_UNLOCKED 0 - -#define spin_lock_init(lock) do { } while(0) -#define spin_lock(lock) do { } while(0) -#define spin_trylock(lock) (1) -#define spin_unlock_wait(lock) do { } while(0) -#define spin_unlock(lock) do { } while(0) -#define spin_lock_irq(lock) cli() -#define spin_unlock_irq(lock) sti() -#define spin_lock_bh(lock) \ -do { local_bh_count++; \ - barrier(); \ -} while(0) -#define spin_unlock_bh(lock) \ -do { barrier(); \ - local_bh_count--; \ -} while(0) - -#define spin_lock_irqsave(lock, flags) save_and_cli(flags) -#define spin_unlock_irqrestore(lock, flags) restore_flags(flags) - -/* - * Read-write spinlocks, allowing multiple readers - * but only one writer. - * - * NOTE! it is quite common to have readers in interrupts - * but no interrupt writers. For those circumstances we - * can "mix" irq-safe locks - any writer needs to get a - * irq-safe write-lock, but readers can get non-irqsafe - * read-locks. - */ -typedef unsigned int rwlock_t; -#define RW_LOCK_UNLOCKED (rwlock_t) { 0 } - -#define read_lock(lock) do { } while(0) -#define read_unlock(lock) do { } while(0) -#define write_lock(lock) do { } while(0) -#define write_unlock(lock) do { } while(0) -#define read_lock_irq(lock) cli() -#define read_unlock_irq(lock) sti() -#define read_lock_bh(lock) \ -do { local_bh_count++; \ - barrier(); \ -} while(0) -#define read_unlock_bh(lock) \ -do { barrier(); \ - local_bh_count--; \ -} while(0) - -#define write_lock_irq(lock) cli() -#define write_unlock_irq(lock) sti() - -#define write_lock_bh(lock) \ -do { local_bh_count++; \ - barrier(); \ -} while(0) - -#define write_unlock_bh(lock) \ -do { barrier(); \ - local_bh_count--; \ -} while(0) - -#define read_lock_irqsave(lock, flags) save_and_cli(flags) -#define read_unlock_irqrestore(lock, flags) restore_flags(flags) -#define write_lock_irqsave(lock, flags) save_and_cli(flags) -#define write_unlock_irqrestore(lock, flags) restore_flags(flags) - -#else /* !(__SMP__) */ - /* To get debugging spinlocks which detect and catch * deadlock situations, set DEBUG_SPINLOCKS in the sparc64 * specific makefile and rebuild your kernel. @@ -141,82 +69,12 @@ extern __inline__ int spin_trylock(spinlock_t *lock) extern __inline__ void spin_unlock(spinlock_t *lock) { __asm__ __volatile__("membar #StoreStore | #LoadStore\n\t" - "stb %%g0, [%0]\n\t" + "stb %%g0, [%0]" : /* No outputs */ : "r" (lock) : "memory"); } -extern __inline__ void spin_lock_irq(spinlock_t *lock) -{ - __asm__ __volatile__(" - wrpr %%g0, 15, %%pil -1: ldstub [%0], %%g7 - brnz,pn %%g7, 2f - membar #StoreLoad | #StoreStore - .subsection 2 -2: ldub [%0], %%g7 - brnz,pt %%g7, 2b - membar #LoadLoad - b,a,pt %%xcc, 1b - .previous -" : /* no outputs */ - : "r" (lock) - : "g7", "memory"); -} - -extern __inline__ void spin_unlock_irq(spinlock_t *lock) -{ - __asm__ __volatile__(" - membar #StoreStore | #LoadStore - stb %%g0, [%0] - wrpr %%g0, 0x0, %%pil -" : /* no outputs */ - : "r" (lock) - : "memory"); -} - -#define spin_lock_bh(__lock) \ -do { local_bh_count++; \ - spin_lock(__lock); \ -} while(0) - -#define spin_unlock_bh(__lock) \ -do { spin_unlock(__lock); \ - local_bh_count--; \ -} while(0) - -#define spin_lock_irqsave(__lock, flags) \ -do { register spinlock_t *__lp asm("g1"); \ - __lp = (__lock); \ - __asm__ __volatile__( \ - "\n rdpr %%pil, %0\n" \ - " wrpr %%g0, 15, %%pil\n" \ - "1: ldstub [%1], %%g7\n" \ - " brnz,pn %%g7, 2f\n" \ - " membar #StoreLoad | #StoreStore\n" \ - " .subsection 2\n" \ - "2: ldub [%1], %%g7\n" \ - " brnz,pt %%g7, 2b\n" \ - " membar #LoadLoad\n" \ - " b,a,pt %%xcc, 1b\n" \ - " .previous\n" \ - : "=&r" (flags) \ - : "r" (__lp) \ - : "g7", "memory"); \ -} while(0) - -extern __inline__ void spin_unlock_irqrestore(spinlock_t *lock, unsigned long flags) -{ - __asm__ __volatile__(" - membar #StoreStore | #LoadStore - stb %%g0, [%0] - wrpr %1, 0x0, %%pil -" : /* no outputs */ - : "r" (lock), "r" (flags) - : "memory"); -} - #else /* !(SPIN_LOCK_DEBUG) */ typedef struct { @@ -241,13 +99,7 @@ extern int _spin_trylock (spinlock_t *lock); #define spin_trylock(lp) _spin_trylock(lp) #define spin_lock(lock) _do_spin_lock(lock, "spin_lock") -#define spin_lock_irq(lock) do { __cli(); _do_spin_lock(lock, "spin_lock_irq"); } while(0) -#define spin_lock_bh(lock) do { local_bh_count++; _do_spin_lock(lock, "spin_lock_bh"); } while(0) -#define spin_lock_irqsave(lock, flags) do { __save_and_cli(flags); _do_spin_lock(lock, "spin_lock_irqsave"); } while(0) #define spin_unlock(lock) _do_spin_unlock(lock) -#define spin_unlock_irq(lock) do { _do_spin_unlock(lock); __sti(); } while(0) -#define spin_unlock_bh(lock) do { _do_spin_unlock(lock); local_bh_count--; } while(0) -#define spin_unlock_irqrestore(lock, flags) do { _do_spin_unlock(lock); __restore_flags(flags); } while(0) #endif /* SPIN_LOCK_DEBUG */ @@ -294,24 +146,6 @@ do { register rwlock_t *__X asm("g1"); \ : "g2", "g3", "g5", "g7", "cc", "memory"); \ } while(0) -#define read_lock_irq(lock) do { __cli(); read_lock(lock); } while (0) -#define read_unlock_irq(lock) do { read_unlock(lock); __sti(); } while (0) -#define read_lock_bh(lock) do { local_bh_count++; read_lock(lock); } while (0) -#define read_unlock_bh(lock) do { read_unlock(lock); local_bh_count--; } while (0) -#define write_lock_irq(lock) do { __cli(); write_lock(lock); } while (0) -#define write_unlock_irq(lock) do { write_unlock(lock); __sti(); } while (0) -#define write_lock_bh(lock) do { local_bh_count++; write_lock(lock); } while (0) -#define write_unlock_bh(lock) do { write_unlock(lock); local_bh_count--; } while (0) - -#define read_lock_irqsave(lock, flags) \ - do { __save_and_cli(flags); read_lock(lock); } while (0) -#define read_unlock_irqrestore(lock, flags) \ - do { read_unlock(lock); __restore_flags(flags); } while (0) -#define write_lock_irqsave(lock, flags) \ - do { __save_and_cli(flags); write_lock(lock); } while (0) -#define write_unlock_irqrestore(lock, flags) \ - do { write_unlock(lock); __restore_flags(flags); } while (0) - #else /* !(SPIN_LOCK_DEBUG) */ typedef struct { @@ -332,9 +166,6 @@ do { unsigned long flags; \ _do_read_lock(lock, "read_lock"); \ __restore_flags(flags); \ } while(0) -#define read_lock_irq(lock) do { __cli(); _do_read_lock(lock, "read_lock_irq"); } while(0) -#define read_lock_bh(lock) do { local_bh_count++; _do_read_lock(lock, "read_lock_bh"); } while(0) -#define read_lock_irqsave(lock, flags) do { __save_and_cli(flags); _do_read_lock(lock, "read_lock_irqsave"); } while(0) #define read_unlock(lock) \ do { unsigned long flags; \ @@ -342,9 +173,6 @@ do { unsigned long flags; \ _do_read_unlock(lock, "read_unlock"); \ __restore_flags(flags); \ } while(0) -#define read_unlock_irq(lock) do { _do_read_unlock(lock, "read_unlock_irq"); __sti() } while(0) -#define read_unlock_bh(lock) do { _do_read_unlock(lock, "read_unlock_bh"); local_bh_count--; } while(0) -#define read_unlock_irqrestore(lock, flags) do { _do_read_unlock(lock, "read_unlock_irqrestore"); __restore_flags(flags); } while(0) #define write_lock(lock) \ do { unsigned long flags; \ @@ -352,9 +180,6 @@ do { unsigned long flags; \ _do_write_lock(lock, "write_lock"); \ __restore_flags(flags); \ } while(0) -#define write_lock_irq(lock) do { __cli(); _do_write_lock(lock, "write_lock_irq"); } while(0) -#define write_lock_bh(lock) do { local_bh_count++; _do_write_lock(lock, "write_lock_bh"); } while(0) -#define write_lock_irqsave(lock, flags) do { __save_and_cli(flags); _do_write_lock(lock, "write_lock_irqsave"); } while(0) #define write_unlock(lock) \ do { unsigned long flags; \ @@ -362,14 +187,9 @@ do { unsigned long flags; \ _do_write_unlock(lock); \ __restore_flags(flags); \ } while(0) -#define write_unlock_irq(lock) do { _do_write_unlock(lock); __sti(); } while(0) -#define write_unlock_bh(lock) do { _do_write_unlock(lock); local_bh_count--; } while(0) -#define write_unlock_irqrestore(lock, flags) do { _do_write_unlock(lock); __restore_flags(flags); } while(0) #endif /* SPIN_LOCK_DEBUG */ -#endif /* __SMP__ */ - #endif /* !(__ASSEMBLY__) */ -#endif /* !(__SPARC64_SPIN%0_H) */ +#endif /* !(__SPARC64_SPINLOCK_H) */ diff --git a/include/asm-sparc64/sunbpp.h b/include/asm-sparc64/sunbpp.h new file mode 100644 index 000000000..b441cc9c4 --- /dev/null +++ b/include/asm-sparc64/sunbpp.h @@ -0,0 +1,80 @@ +/* $Id: sunbpp.h,v 1.1 1999/08/13 06:21:44 shadow Exp $ + * include/asm-sparc64/sunbpp.h + */ + +#ifndef _ASM_SPARC64_SUNBPP_H +#define _ASM_SPARC64_SUNBPP_H + +struct bpp_regs { + /* DMA registers */ + __volatile__ __u32 p_csr; /* DMA Control/Status Register */ + __volatile__ __u32 p_addr; /* Address Register */ + __volatile__ __u32 p_bcnt; /* Byte Count Register */ + __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */ + /* Parallel Port registers */ + __volatile__ __u16 p_hcr; /* Hardware Configuration Register */ + __volatile__ __u16 p_ocr; /* Operation Configuration Register */ + __volatile__ __u8 p_dr; /* Parallel Data Register */ + __volatile__ __u8 p_tcr; /* Transfer Control Register */ + __volatile__ __u8 p_or; /* Output Register */ + __volatile__ __u8 p_ir; /* Input Register */ + __volatile__ __u16 p_icr; /* Interrupt Control Register */ +}; + +/* P_HCR. Time is in increments of SBus clock. */ +#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */ +#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */ +#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */ + +/* P_OCR. */ +#define P_OCR_MEM_CLR 0x8000 +#define P_OCR_DATA_SRC 0x4000 /* ) */ +#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */ +#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */ +#define P_OCR_ACK_DSEL 0x0800 /* ) */ +#define P_OCR_EN_DIAG 0x0400 +#define P_OCR_BUSY_OP 0x0200 /* Busy operation */ +#define P_OCR_ACK_OP 0x0100 /* Ack operation */ +#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */ +#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */ +#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */ +#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */ + +/* P_TCR */ +#define P_TCR_DIR 0x08 +#define P_TCR_BUSY 0x04 +#define P_TCR_ACK 0x02 +#define P_TCR_DS 0x01 /* Strobe */ + +/* P_OR */ +#define P_OR_V3 0x20 /* ) */ +#define P_OR_V2 0x10 /* ) on Zebra only */ +#define P_OR_V1 0x08 /* ) */ +#define P_OR_INIT 0x04 +#define P_OR_AFXN 0x02 /* Auto Feed */ +#define P_OR_SLCT_IN 0x01 + +/* P_IR */ +#define P_IR_PE 0x04 +#define P_IR_SLCT 0x02 +#define P_IR_ERR 0x01 + +/* P_ICR */ +#define P_DS_IRQ 0x8000 /* RW1 */ +#define P_ACK_IRQ 0x4000 /* RW1 */ +#define P_BUSY_IRQ 0x2000 /* RW1 */ +#define P_PE_IRQ 0x1000 /* RW1 */ +#define P_SLCT_IRQ 0x0800 /* RW1 */ +#define P_ERR_IRQ 0x0400 /* RW1 */ +#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */ +#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */ +#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */ +#define P_BUSY_IRQ_EN 0x0040 /* RW */ +#define P_PE_IRP 0x0020 /* RW 1= rising edge */ +#define P_PE_IRQ_EN 0x0010 /* RW */ +#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */ +#define P_SLCT_IRQ_EN 0x0004 /* RW */ +#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */ +#define P_ERR_IRQ_EN 0x0001 /* RW */ + +#endif /* !(_ASM_SPARC64_SUNBPP_H) */ diff --git a/include/asm-sparc64/sysio.h b/include/asm-sparc64/sysio.h index 8508f7e0c..5ee5875f2 100644 --- a/include/asm-sparc64/sysio.h +++ b/include/asm-sparc64/sysio.h @@ -1,4 +1,4 @@ -/* $Id: sysio.h,v 1.8 1998/11/29 15:49:54 davem Exp $ +/* $Id: sysio.h,v 1.9 1999/08/30 10:15:03 davem Exp $ * sysio.h: UltraSparc sun5 specific SBUS definitions. * * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) @@ -11,34 +11,34 @@ /* SUN5 SYSIO Register Set, one per controller probed. */ struct sysio_regs { -/*0x0000*/ u64 upa_id; /* SYSIO UPA Port ID Register */ -/*0x0008*/ u64 upa_cfg; /* SYSIO UPA Config Register */ -/*0x0010*/ u64 control; /* SYSIO Control Register */ -/*0x0018*/ u64 _unused1; -/*0x0020*/ u64 ecc_control; /* ECC Control Register */ -/*0x0028*/ u64 _unused2; +/*0x0000*/ volatile u64 upa_id; /* SYSIO UPA Port ID Register */ +/*0x0008*/ volatile u64 upa_cfg; /* SYSIO UPA Config Register */ +/*0x0010*/ volatile u64 control; /* SYSIO Control Register */ +/*0x0018*/ volatile u64 _unused1; +/*0x0020*/ volatile u64 ecc_control; /* ECC Control Register */ +/*0x0028*/ volatile u64 _unused2; /* Uncorrectable Error Fault Registers */ -/*0x0030*/ u64 ue_afsr; /* UE Async Fault Status */ -/*0x0038*/ u64 ue_afar; /* UE Async Fault Address */ +/*0x0030*/ volatile u64 ue_afsr; /* UE Async Fault Status */ +/*0x0038*/ volatile u64 ue_afar; /* UE Async Fault Address */ /* Correctable Error Fault Registers */ -/*0x0040*/ u64 ce_afsr; /* CE Async Fault Status */ -/*0x0048*/ u64 ce_afar; /* CE Async Fault Address */ +/*0x0040*/ volatile u64 ce_afsr; /* CE Async Fault Status */ +/*0x0048*/ volatile u64 ce_afar; /* CE Async Fault Address */ - u64 __pad0[0x16]; + volatile u64 __pad0[0x16]; /* Performance Monitoring Registers */ -/*0x0100*/ u64 pmon_control; -/*0x0108*/ u64 pmon_counter; +/*0x0100*/ volatile u64 pmon_control; +/*0x0108*/ volatile u64 pmon_counter; - u64 __pad1[0x3de]; + volatile u64 __pad1[0x3de]; /* SBUS Module Registers */ -/*0x2000*/ u64 sbus_control; /* SBUS Control Register */ -/*0x2008*/ u64 _unused3; -/*0x2010*/ u64 sbus_afsr; /* SBUS Async Fault Status */ -/*0x2018*/ u64 sbus_afar; /* SBUS Async Fault Address */ +/*0x2000*/ volatile u64 sbus_control; /* SBUS Control Register */ +/*0x2008*/ volatile u64 _unused3; +/*0x2010*/ volatile u64 sbus_afsr; /* SBUS Async Fault Status */ +/*0x2018*/ volatile u64 sbus_afar; /* SBUS Async Fault Address */ /* SBUS Slot Configuration Registers. * On Fusion/Electron/Pulsar desktops/servers slots 4-->6 @@ -52,137 +52,137 @@ struct sysio_regs { * On Sunfire/Starfire/Wildfire enterprise boxen these upper slots * are unused. */ -/*0x2020*/ u64 sbus_s0cfg; /* SBUS Slot 0 Config */ -/*0x2028*/ u64 sbus_s1cfg; /* SBUS Slot 1 Config */ -/*0x2030*/ u64 sbus_s2cfg; /* SBUS Slot 2 Config */ -/*0x2038*/ u64 sbus_s3cfg; /* SBUS Slot 3 Config */ -/*0x2040*/ u64 sbus_s4cfg; /* SBUS Slot 4 Config */ -/*0x2048*/ u64 sbus_s5cfg; /* SBUS Slot 5 Config */ -/*0x2050*/ u64 sbus_s6cfg; /* SBUS Slot 6 Config */ +/*0x2020*/ volatile u64 sbus_s0cfg; /* SBUS Slot 0 Config */ +/*0x2028*/ volatile u64 sbus_s1cfg; /* SBUS Slot 1 Config */ +/*0x2030*/ volatile u64 sbus_s2cfg; /* SBUS Slot 2 Config */ +/*0x2038*/ volatile u64 sbus_s3cfg; /* SBUS Slot 3 Config */ +/*0x2040*/ volatile u64 sbus_s4cfg; /* SBUS Slot 4 Config */ +/*0x2048*/ volatile u64 sbus_s5cfg; /* SBUS Slot 5 Config */ +/*0x2050*/ volatile u64 sbus_s6cfg; /* SBUS Slot 6 Config */ - u64 __pad2[0x75]; + volatile u64 __pad2[0x75]; /* SBUS IOMMU lives here */ -/*0x2400*/ u64 iommu_control; /* IOMMU Control */ -/*0x2408*/ u64 iommu_tsbbase; /* IOMMU TSB Base */ -/*0x2410*/ u64 iommu_flush; /* IOMMU Flush Register */ +/*0x2400*/ volatile u64 iommu_control; /* IOMMU Control */ +/*0x2408*/ volatile u64 iommu_tsbbase; /* IOMMU TSB Base */ +/*0x2410*/ volatile u64 iommu_flush; /* IOMMU Flush Register */ - u64 __pad3[0x7d]; + volatile u64 __pad3[0x7d]; /* SBUS/IOMMU Streaming Buffer Registers */ -/*0x2800*/ u64 sbuf_control; /* StrBuffer Control */ -/*0x2808*/ u64 sbuf_pflush; /* StrBuffer Page Flush */ -/*0x2810*/ u64 sbuf_fsync; /* StrBuffer Flush Synchronization Reg */ +/*0x2800*/ volatile u64 sbuf_control; /* StrBuffer Control */ +/*0x2808*/ volatile u64 sbuf_pflush; /* StrBuffer Page Flush */ +/*0x2810*/ volatile u64 sbuf_fsync; /* StrBuffer Flush Synchronization Reg */ - u64 __pad4[0x7d]; + volatile u64 __pad4[0x7d]; /* Interrupt mapping/control registers */ -/*0x2c00*/ u32 _uim0, imap_slot0; /* SBUS Slot 0 Int Mapping */ -/*0x2c08*/ u32 _uim1, imap_slot1; /* SBUS Slot 1 Int Mapping */ -/*0x2c10*/ u32 _uim2, imap_slot2; /* SBUS Slot 2 Int Mapping */ -/*0x2c18*/ u32 _uim3, imap_slot3; /* SBUS Slot 3 Int Mapping */ +/*0x2c00*/ volatile u32 _uim0, imap_slot0; /* SBUS Slot 0 Int Mapping */ +/*0x2c08*/ volatile u32 _uim1, imap_slot1; /* SBUS Slot 1 Int Mapping */ +/*0x2c10*/ volatile u32 _uim2, imap_slot2; /* SBUS Slot 2 Int Mapping */ +/*0x2c18*/ volatile u32 _uim3, imap_slot3; /* SBUS Slot 3 Int Mapping */ /* Interrupt Retry Timer. */ -/*0x2c20*/ u32 _irpad, irq_retry; +/*0x2c20*/ volatile u32 _irpad, irq_retry; - u64 __pad5[0x7b]; + volatile u64 __pad5[0x7b]; /* The following are only used on Fusion/Electron/Pulsar * desktop systems, they mean nothing on Sunfire/Starfire/Wildfire */ -/*0x3000*/ u32 _uis, imap_scsi; /* SCSI Int Mapping */ -/*0x3008*/ u32 _uie, imap_eth; /* Ethernet Int Mapping */ -/*0x3010*/ u32 _uip, imap_bpp; /* Parallel Port Int Mapping */ -/*0x3018*/ u32 _uia, imap_audio; /* Audio Int Mapping */ -/*0x3020*/ u32 _uipf, imap_pfail; /* Power Fail Int Mapping */ -/*0x3028*/ u32 _uik, imap_kms; /* Kbd/Mouse/Serial Int Mapping */ -/*0x3030*/ u32 _uif, imap_flpy; /* Floppy Int Mapping */ -/*0x3038*/ u32 _uishw, imap_shw; /* Spare HW Int Mapping */ -/*0x3040*/ u32 _uikbd, imap_kbd; /* Kbd Only Int Mapping */ -/*0x3048*/ u32 _uims, imap_ms; /* Mouse Only Int Mapping */ -/*0x3050*/ u32 _uiser, imap_ser; /* Serial Only Int Mapping */ -/*0x3058*/ u64 _imap_unused; -/*0x3060*/ u32 _uit0, imap_tim0; /* Timer 0 Int Mapping */ -/*0x3068*/ u32 _uit1, imap_tim1; /* Timer 1 Int Mapping */ -/*0x3070*/ u32 _uiue, imap_ue; /* UE Int Mapping */ -/*0x3078*/ u32 _uice, imap_ce; /* CE Int Mapping */ -/*0x3080*/ u32 _uisbe, imap_sberr; /* SBUS Err Int Mapping */ -/*0x3088*/ u32 _uipm, imap_pmgmt; /* Power Mgmt Int Mapping */ -/*0x3090*/ u32 _uigfx, imap_gfx; /* OB Graphics Int Mapping */ -/*0x3098*/ u32 _uieupa, imap_eupa; /* UPA Expansion Int Mapping */ - - u64 __pad6[0x6c]; +/*0x3000*/ volatile u32 _uis, imap_scsi; /* SCSI Int Mapping */ +/*0x3008*/ volatile u32 _uie, imap_eth; /* Ethernet Int Mapping */ +/*0x3010*/ volatile u32 _uip, imap_bpp; /* Parallel Port Int Mapping */ +/*0x3018*/ volatile u32 _uia, imap_audio; /* Audio Int Mapping */ +/*0x3020*/ volatile u32 _uipf, imap_pfail; /* Power Fail Int Mapping */ +/*0x3028*/ volatile u32 _uik, imap_kms; /* Kbd/Ms/Serial Int Mapping */ +/*0x3030*/ volatile u32 _uif, imap_flpy; /* Floppy Int Mapping */ +/*0x3038*/ volatile u32 _uishw, imap_shw; /* Spare HW Int Mapping */ +/*0x3040*/ volatile u32 _uikbd, imap_kbd; /* Kbd Only Int Mapping */ +/*0x3048*/ volatile u32 _uims, imap_ms; /* Mouse Only Int Mapping */ +/*0x3050*/ volatile u32 _uiser, imap_ser; /* Serial Only Int Mapping */ +/*0x3058*/ volatile u64 _imap_unused; +/*0x3060*/ volatile u32 _uit0, imap_tim0; /* Timer 0 Int Mapping */ +/*0x3068*/ volatile u32 _uit1, imap_tim1; /* Timer 1 Int Mapping */ +/*0x3070*/ volatile u32 _uiue, imap_ue; /* UE Int Mapping */ +/*0x3078*/ volatile u32 _uice, imap_ce; /* CE Int Mapping */ +/*0x3080*/ volatile u32 _uisbe, imap_sberr; /* SBUS Err Int Mapping */ +/*0x3088*/ volatile u32 _uipm, imap_pmgmt; /* Power Mgmt Int Mapping */ +/*0x3090*/ volatile u32 _uigfx, imap_gfx; /* OB Graphics Int Mapping */ +/*0x3098*/ volatile u32 _uieupa, imap_eupa; /* UPA Expansion Int Mapping */ + + volatile u64 __pad6[0x6c]; /* Interrupt Clear Registers */ -/*0x3400*/ u32 __ucu0, iclr_unused0; -/*0x3408*/ u32 _ucs0, iclr_slot0; - u64 __pad7[0x7]; -/*0x3448*/ u32 _ucs1, iclr_slot1; - u64 __pad8[0x7]; -/*0x3488*/ u32 _ucs2, iclr_slot2; - u64 __pad9[0x7]; -/*0x34c8*/ u32 _ucs3, iclr_slot3; - u64 __pad10[0x66]; -/*0x3800*/ u32 _ucscsi, iclr_scsi; -/*0x3808*/ u32 _uceth, iclr_eth; -/*0x3810*/ u32 _ucbpp, iclr_bpp; -/*0x3818*/ u32 _ucaudio, iclr_audio; -/*0x3820*/ u32 _ucpfail, iclr_pfail; -/*0x3828*/ u32 _uckms, iclr_kms; -/*0x3830*/ u32 _ucflpy, iclr_flpt; -/*0x3838*/ u32 _ucshw, iclr_shw; -/*0x3840*/ u32 _uckbd, iclr_kbd; -/*0x3848*/ u32 _ucms, iclr_ms; -/*0x3850*/ u32 _ucser, iclr_ser; -/*0x3858*/ u64 iclr_unused1; -/*0x3860*/ u32 _uctim0, iclr_tim0; -/*0x3868*/ u32 _uctim1, iclr_tim1; -/*0x3870*/ u32 _ucue, iclr_ue; -/*0x3878*/ u32 _ucce, iclr_ce; -/*0x3880*/ u32 _ucserr, iclr_serr; -/*0x3888*/ u32 _ucpmgmt, iclr_pmgmt; - - u64 __pad11[0x6e]; +/*0x3400*/ volatile u32 __ucu0, iclr_unused0; +/*0x3408*/ volatile u32 _ucs0, iclr_slot0; + volatile u64 __pad7[0x7]; +/*0x3448*/ volatile u32 _ucs1, iclr_slot1; + volatile u64 __pad8[0x7]; +/*0x3488*/ volatile u32 _ucs2, iclr_slot2; + volatile u64 __pad9[0x7]; +/*0x34c8*/ volatile u32 _ucs3, iclr_slot3; + volatile u64 __pad10[0x66]; +/*0x3800*/ volatile u32 _ucscsi, iclr_scsi; +/*0x3808*/ volatile u32 _uceth, iclr_eth; +/*0x3810*/ volatile u32 _ucbpp, iclr_bpp; +/*0x3818*/ volatile u32 _ucaudio, iclr_audio; +/*0x3820*/ volatile u32 _ucpfail, iclr_pfail; +/*0x3828*/ volatile u32 _uckms, iclr_kms; +/*0x3830*/ volatile u32 _ucflpy, iclr_flpt; +/*0x3838*/ volatile u32 _ucshw, iclr_shw; +/*0x3840*/ volatile u32 _uckbd, iclr_kbd; +/*0x3848*/ volatile u32 _ucms, iclr_ms; +/*0x3850*/ volatile u32 _ucser, iclr_ser; +/*0x3858*/ volatile u64 iclr_unused1; +/*0x3860*/ volatile u32 _uctim0, iclr_tim0; +/*0x3868*/ volatile u32 _uctim1, iclr_tim1; +/*0x3870*/ volatile u32 _ucue, iclr_ue; +/*0x3878*/ volatile u32 _ucce, iclr_ce; +/*0x3880*/ volatile u32 _ucserr, iclr_serr; +/*0x3888*/ volatile u32 _ucpmgmt, iclr_pmgmt; + + volatile u64 __pad11[0x6e]; /* Counters/Timers */ -/*0x3c00*/ u64 tim0_cnt; -/*0x3c08*/ u64 tim0_lim; -/*0x3c10*/ u64 tim1_cnt; -/*0x3c18*/ u64 tim1_lim; +/*0x3c00*/ volatile u64 tim0_cnt; +/*0x3c08*/ volatile u64 tim0_lim; +/*0x3c10*/ volatile u64 tim1_cnt; +/*0x3c18*/ volatile u64 tim1_lim; - u64 __pad12[0x7c]; + volatile u64 __pad12[0x7c]; /* DMA Scoreboard Diagnostic Registers */ -/*0x4000*/ u64 dscore_reg0; /* DMA Scoreboard Diag Reg 0 */ -/*0x4008*/ u64 dscore_reg1; /* DMA Scoreboard Diag Reg 1 */ +/*0x4000*/ volatile u64 dscore_reg0; /* DMA Scoreboard Diag Reg 0 */ +/*0x4008*/ volatile u64 dscore_reg1; /* DMA Scoreboard Diag Reg 1 */ - u64 __pad13[0x7e]; + volatile u64 __pad13[0x7e]; /* SBUS IOMMU Diagnostic Registers */ -/*0x4400*/ u64 sbus_vdiag; /* SBUS VADDR Diagnostic Register */ -/*0x4408*/ u64 sbus_tcompare; /* SBUS IOMMU TLB Tag Compare */ +/*0x4400*/ volatile u64 sbus_vdiag; /* SBUS VADDR Diagnostic Register */ +/*0x4408*/ volatile u64 sbus_tcompare; /* SBUS IOMMU TLB Tag Compare */ - u64 __pad14[0x1e]; + volatile u64 __pad14[0x1e]; /* More IOMMU diagnostic things */ -/*0x4500*/ u64 iommu_lru[16]; /* IOMMU LRU Queue Diagnostic Access */ -/*0x4580*/ u64 iommu_tag[16]; /* IOMMU TLB Tag Diagnostic Access */ -/*0x4600*/ u64 iommu_data[32]; /* IOMMU TLB Data RAM Diagnostic Access */ +/*0x4500*/ volatile u64 iommu_lru[16]; /* IOMMU LRU Queue Diagnostic Access */ +/*0x4580*/ volatile u64 iommu_tag[16]; /* IOMMU TLB Tag Diagnostic Access */ +/*0x4600*/ volatile u64 iommu_data[32]; /* IOMMU TLB Data RAM Diag Access */ - u64 __pad15[0x20]; + volatile u64 __pad15[0x20]; /* Interrupt State Diagnostics */ -/*0x4800*/ u64 sbus_istate; -/*0x4808*/ u64 obio_istate; +/*0x4800*/ volatile u64 sbus_istate; +/*0x4808*/ volatile u64 obio_istate; - u64 __pad16[0xfe]; + volatile u64 __pad16[0xfe]; /* Streaming Buffer Diagnostic Area */ -/*0x5000*/ u64 sbuf_data[128]; /* StrBuffer Data Ram Diagnostic */ -/*0x5400*/ u64 sbuf_errs[128]; /* StrBuffer Error Status Diagnostics */ -/*0x5800*/ u64 sbuf_ptag[16]; /* StrBuffer Page Tag Diagnostics */ -/*0x5880*/ u64 _unusedXXX[16]; -/*0x5900*/ u64 sbuf_ltag[16]; /* StrBuffer Line Tag Diagnostics */ +/*0x5000*/ volatile u64 sbuf_data[128]; /* StrBuffer Data Ram Diagnostic */ +/*0x5400*/ volatile u64 sbuf_errs[128]; /* StrBuffer Error Status Diagnostics */ +/*0x5800*/ volatile u64 sbuf_ptag[16]; /* StrBuffer Page Tag Diagnostics */ +/*0x5880*/ volatile u64 _unusedXXX[16]; +/*0x5900*/ volatile u64 sbuf_ltag[16]; /* StrBuffer Line Tag Diagnostics */ }; /* SYSIO UPA Port ID */ diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index 82cf1eb41..5989d8c4a 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h @@ -1,4 +1,4 @@ -/* $Id: system.h,v 1.50 1999/05/08 03:03:22 davem Exp $ */ +/* $Id: system.h,v 1.55 1999/09/10 10:44:44 davem Exp $ */ #ifndef __SPARC64_SYSTEM_H #define __SPARC64_SYSTEM_H @@ -63,9 +63,13 @@ extern unsigned long empty_zero_page; retval; \ }) -#define __save_flags(flags) ((flags) = getipl()) -#define __save_and_cli(flags) ((flags) = read_pil_and_cli()) -#define __restore_flags(flags) setipl((flags)) +#define __save_flags(flags) ((flags) = getipl()) +#define __save_and_cli(flags) ((flags) = read_pil_and_cli()) +#define __restore_flags(flags) setipl((flags)) +#define local_irq_disable() __cli() +#define local_irq_enable() __sti() +#define local_irq_save(flags) __save_and_cli(flags) +#define local_irq_restore(flags) __restore_flags(flags) #ifndef __SMP__ #define cli() __cli() @@ -97,6 +101,12 @@ extern void __global_restore_flags(unsigned long flags); #define membar(type) __asm__ __volatile__ ("membar " type : : : "memory"); #define rmb() membar("#LoadLoad | #LoadStore") #define wmb() membar("#StoreLoad | #StoreStore") +#define set_mb(__var, __value) \ + do { __var = __value; membar("#StoreLoad | #StoreStore"); } while(0) +#define set_rmb(__var, __value) \ + do { __var = __value; membar("#StoreLoad"); } while(0) +#define set_wmb(__var, __value) \ + do { __var = __value; membar("#StoreStore"); } while(0) #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory") @@ -124,6 +134,8 @@ extern __inline__ void flushw_user(void) } #define flush_user_windows flushw_user +#define flush_register_windows flushw_all +#define prepare_to_switch flushw_all /* See what happens when you design the chip correctly? * @@ -135,20 +147,19 @@ extern __inline__ void flushw_user(void) * and 2 stores in this critical code path. -DaveM */ #define switch_to(prev, next, last) \ -do { if (current->tss.flags & SPARC_FLAG_PERFCTR) { \ +do { if (current->thread.flags & SPARC_FLAG_PERFCTR) { \ unsigned long __tmp; \ read_pcr(__tmp); \ - current->tss.pcr_reg = __tmp; \ + current->thread.pcr_reg = __tmp; \ read_pic(__tmp); \ - current->tss.kernel_cntd0 += (unsigned int)(__tmp); \ - current->tss.kernel_cntd1 += ((__tmp) >> 32); \ + current->thread.kernel_cntd0 += (unsigned int)(__tmp); \ + current->thread.kernel_cntd1 += ((__tmp) >> 32); \ } \ save_and_clear_fpu(); \ - __asm__ __volatile__( \ - "flushw\n\t" \ - "wrpr %g0, 0x94, %pstate\n\t"); \ - __get_mmu_context(next); \ - (next)->mm->cpu_vm_mask |= (1UL << smp_processor_id()); \ + /* If you are tempted to conditionalize the following */ \ + /* so that ASI is only written if it changes, think again. */ \ + __asm__ __volatile__("wr %%g0, %0, %%asi" \ + : : "r" (next->thread.current_ds.seg)); \ __asm__ __volatile__( \ "mov %%g6, %%g5\n\t" \ "wrpr %%g0, 0x95, %%pstate\n\t" \ @@ -156,15 +167,15 @@ do { if (current->tss.flags & SPARC_FLAG_PERFCTR) { \ "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ "rdpr %%wstate, %%o5\n\t" \ "stx %%o6, [%%g6 + %3]\n\t" \ - "sth %%o5, [%%g6 + %2]\n\t" \ + "stb %%o5, [%%g6 + %2]\n\t" \ "rdpr %%cwp, %%o5\n\t" \ - "sth %%o5, [%%g6 + %5]\n\t" \ + "stb %%o5, [%%g6 + %5]\n\t" \ "mov %1, %%g6\n\t" \ - "lduh [%1 + %5], %%g1\n\t" \ + "ldub [%1 + %5], %%g1\n\t" \ "wrpr %%g1, %%cwp\n\t" \ "ldx [%%g6 + %3], %%o6\n\t" \ - "lduh [%%g6 + %2], %%o5\n\t" \ - "lduh [%%g6 + %4], %%o7\n\t" \ + "ldub [%%g6 + %2], %%o5\n\t" \ + "ldub [%%g6 + %4], %%o7\n\t" \ "mov %%g6, %%l2\n\t" \ "wrpr %%o5, 0x0, %%wstate\n\t" \ "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ @@ -172,22 +183,23 @@ do { if (current->tss.flags & SPARC_FLAG_PERFCTR) { \ "wrpr %%g0, 0x94, %%pstate\n\t" \ "mov %%l2, %%g6\n\t" \ "wrpr %%g0, 0x96, %%pstate\n\t" \ - "andcc %%o7, 0x100, %%g0\n\t" \ + "andcc %%o7, %6, %%g0\n\t" \ "bne,pn %%icc, ret_from_syscall\n\t" \ " mov %%g5, %0\n\t" \ : "=&r" (last) \ : "r" (next), \ - "i" ((const unsigned long)(&((struct task_struct *)0)->tss.wstate)), \ - "i" ((const unsigned long)(&((struct task_struct *)0)->tss.ksp)), \ - "i" ((const unsigned long)(&((struct task_struct *)0)->tss.flags)), \ - "i" ((const unsigned long)(&((struct task_struct *)0)->tss.cwp)) \ + "i" ((const unsigned long)(&((struct task_struct *)0)->thread.wstate)),\ + "i" ((const unsigned long)(&((struct task_struct *)0)->thread.ksp)), \ + "i" ((const unsigned long)(&((struct task_struct *)0)->thread.flags)),\ + "i" ((const unsigned long)(&((struct task_struct *)0)->thread.cwp)), \ + "i" (SPARC_FLAG_NEWCHILD) \ : "cc", "g1", "g2", "g3", "g5", "g7", \ "l2", "l3", "l4", "l5", "l6", "l7", \ "i0", "i1", "i2", "i3", "i4", "i5", \ "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \ /* If you fuck with this, update ret_from_syscall code too. */ \ - if (current->tss.flags & SPARC_FLAG_PERFCTR) { \ - write_pcr(current->tss.pcr_reg); \ + if (current->thread.flags & SPARC_FLAG_PERFCTR) { \ + write_pcr(current->thread.pcr_reg); \ reset_pic(); \ } \ } while(0) diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h index 135692768..2d1067c7d 100644 --- a/include/asm-sparc64/timer.h +++ b/include/asm-sparc64/timer.h @@ -1,4 +1,4 @@ -/* $Id: timer.h,v 1.2 1998/05/04 12:43:59 ralf Exp $ +/* $Id: timer.h,v 1.2 1998/03/15 17:23:52 ecd Exp $ * timer.h: System timer definitions for sun5. * * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) diff --git a/include/asm-sparc64/ttable.h b/include/asm-sparc64/ttable.h index 7619264ae..4289e581c 100644 --- a/include/asm-sparc64/ttable.h +++ b/include/asm-sparc64/ttable.h @@ -1,4 +1,4 @@ -/* $Id: ttable.h,v 1.11 1999/03/29 12:38:12 jj Exp $ */ +/* $Id: ttable.h,v 1.13 1999/08/31 19:25:50 davem Exp $ */ #ifndef _SPARC64_TTABLE_H #define _SPARC64_TTABLE_H @@ -54,6 +54,13 @@ clr %l6; \ nop; +#define TRAPTL1_CEE \ + ldxa [%g0] ASI_AFSR, %g1; \ + membar #Sync; \ + stxa %g1, [%g0] ASI_AFSR; \ + membar #Sync; \ + retry; nop; nop; nop; + #define TRAP_ARG(routine, arg) \ sethi %hi(109f), %g7; \ ba,pt %xcc, etrap; \ @@ -91,7 +98,7 @@ nop;nop;nop; #define TRAP_UTRAP(handler,lvl) \ - ldx [%g6 + AOFF_task_tss + AOFF_thread_utraps], %g1; \ + ldx [%g6 + AOFF_task_thread + AOFF_thread_utraps], %g1; \ sethi %hi(109f), %g7; \ brz,pn %g1, utrap; \ or %g7, %lo(109f), %g7; \ diff --git a/include/asm-sparc64/uaccess.h b/include/asm-sparc64/uaccess.h index a6f5c9a44..e0dd2e4f3 100644 --- a/include/asm-sparc64/uaccess.h +++ b/include/asm-sparc64/uaccess.h @@ -1,4 +1,4 @@ -/* $Id: uaccess.h,v 1.30 1999/05/25 16:53:32 jj Exp $ */ +/* $Id: uaccess.h,v 1.31 1999/07/30 09:31:24 davem Exp $ */ #ifndef _ASM_UACCESS_H #define _ASM_UACCESS_H @@ -36,14 +36,14 @@ #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define get_fs() (current->tss.current_ds) +#define get_fs() (current->thread.current_ds) #define get_ds() (KERNEL_DS) #define segment_eq(a,b) ((a).seg == (b).seg) #define set_fs(val) \ do { \ - current->tss.current_ds = (val); \ + current->thread.current_ds = (val); \ __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \ } while(0) diff --git a/include/asm-sparc64/uctx.h b/include/asm-sparc64/uctx.h index 1899ff971..6eaf16ef2 100644 --- a/include/asm-sparc64/uctx.h +++ b/include/asm-sparc64/uctx.h @@ -1,4 +1,4 @@ -/* $Id: uctx.h,v 1.1 1997/07/18 06:29:24 ralf Exp $ +/* $Id: uctx.h,v 1.1 1997/06/18 16:51:58 davem Exp $ * uctx.h: Sparc64 {set,get}context() register state layouts. * * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) diff --git a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h index 87a6833c5..6e364cc7d 100644 --- a/include/asm-sparc64/unistd.h +++ b/include/asm-sparc64/unistd.h @@ -1,4 +1,4 @@ -/* $Id: unistd.h,v 1.28 1999/04/07 17:14:19 davem Exp $ */ +/* $Id: unistd.h,v 1.31 1999/08/04 03:20:06 davem Exp $ */ #ifndef _SPARC64_UNISTD_H #define _SPARC64_UNISTD_H @@ -225,7 +225,7 @@ #define __NR_syslog 207 /* Linux Specific */ /* #define __NR_olduname 208 Linux Specific */ /* #define __NR_iopl 209 Linux Specific - i386 specific, unused */ -#define __NR_idle 210 /* Linux Specific */ +/* #define __NR_idle 210 Linux Specific - was sys_idle, now unused */ /* #define __NR_vm86 211 Linux Specific - i386 specific, unused */ #define __NR_waitpid 212 /* Linux Specific */ #define __NR_swapoff 213 /* Linux Specific */ @@ -411,7 +411,6 @@ return -1; \ * some others too. */ #define __NR__exit __NR_exit -static __inline__ _syscall0(int,idle) static __inline__ _syscall0(int,pause) static __inline__ _syscall0(int,sync) static __inline__ _syscall0(pid_t,setsid) @@ -431,8 +430,6 @@ static __inline__ pid_t wait(int * wait_stat) return waitpid(-1,wait_stat,0); } -extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - #endif /* __KERNEL_SYSCALLS__ */ #ifdef __KERNEL__ |