diff options
Diffstat (limited to 'include')
122 files changed, 4292 insertions, 2763 deletions
diff --git a/include/asm-alpha/keyboard.h b/include/asm-alpha/keyboard.h index 0761803f7..429898812 100644 --- a/include/asm-alpha/keyboard.h +++ b/include/asm-alpha/keyboard.h @@ -3,7 +3,7 @@ * * Created 3 Nov 1996 by Geert Uytterhoeven * - * $Id: keyboard.h,v 1.8 1999/06/10 08:02:36 ralf Exp $ + * $Id: keyboard.h,v 1.9 1999/11/19 20:35:47 ralf Exp $ */ /* @@ -76,5 +76,30 @@ extern unsigned char pckbd_sysrq_xlate[128]; "PS/2 Mouse", NULL) #define aux_free_irq(dev_id) free_irq(AUX_IRQ, NULL) +/* resource allocation */ +#define kbd_request_region() +#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \ + "keyboard", NULL) + +/* How to access the keyboard macros on this platform. */ +#define kbd_read_input() inb(KBD_DATA_REG) +#define kbd_read_status() inb(KBD_STATUS_REG) +#define kbd_write_output(val) outb(val, KBD_DATA_REG) +#define kbd_write_command(val) outb(val, KBD_CNTL_REG) + +/* Some stoneage hardware needs delays after some operations. */ +#define kbd_pause() do { } while(0) + +/* + * Machine specific bits for the PS/2 driver + */ + +#define AUX_IRQ 12 + +#define aux_request_irq(hand, dev_id) \ + request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS/2 Mouse", dev_id) + +#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) + #endif /* __KERNEL__ */ #endif /* __ASM_ALPHA_KEYBOARD_H */ diff --git a/include/asm-alpha/uaccess.h b/include/asm-alpha/uaccess.h index e08947135..adba04b1f 100644 --- a/include/asm-alpha/uaccess.h +++ b/include/asm-alpha/uaccess.h @@ -487,6 +487,15 @@ extern inline long strlen_user(const char *str) return access_ok(VERIFY_READ,str,0) ? __strlen_user(str) : 0; } +/* Returns: 0 if exception before NUL or reaching the supplied limit (N), + * a value greater than N if the limit would be exceeded, else strlen. */ +extern long __strnlen_user(const char *, long); + +extern inline long strnlen_user(const char *str, long n) +{ + return access_ok(VERIFY_READ,str,0) ? __strnlen_user(str, n) : 0; +} + /* * About the exception table: * diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h index 7b035d9a3..69fcbac3e 100644 --- a/include/asm-i386/apic.h +++ b/include/asm-i386/apic.h @@ -10,7 +10,10 @@ #define APIC_ID 0x20 #define GET_APIC_ID(x) (((x)>>24)&0x0F) -#define APIC_VERSION 0x30 +#define APIC_LVR 0x30 +#define GET_APIC_VERSION(x) ((x)&0xFF) +#define GET_APIC_MAXLVT(x) (((x)>>16)&0x0F) +#define APIC_INTEGRATED(x) ((x)&0xF0) #define APIC_TASKPRI 0x80 #define APIC_TPRI_MASK 0xFF #define APIC_ARBPRI 0x90 @@ -23,6 +26,7 @@ #define APIC_LDR_MASK (0xFF<<24) #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF) #define SET_APIC_LOGICAL_ID(x) (((x)<<24)) +#define APIC_ALL_CPUS 0xFF #define APIC_DFR 0xE0 #define GET_APIC_DFR(x) (((x)>>28)&0x0F) #define SET_APIC_DFR(x) ((x)<<28) @@ -62,7 +66,14 @@ #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) #define SET_APIC_DEST_FIELD(x) ((x)<<24) #define APIC_LVTT 0x320 +#define APIC_LVTPC 0x340 #define APIC_LVT0 0x350 +#define APIC_LVT_TIMER_BASE_MASK (0x3<<18) +#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3) +#define SET_APIC_TIMER_BASE(x) (((x)<<18)) +#define APIC_TIMER_BASE_CLKIN 0x0 +#define APIC_TIMER_BASE_TMBASE 0x1 +#define APIC_TIMER_BASE_DIV 0x2 #define APIC_LVT_TIMER_PERIODIC (1<<17) #define APIC_LVT_MASKED (1<<16) #define APIC_LVT_LEVEL_TRIGGER (1<<15) @@ -75,10 +86,11 @@ #define APIC_MODE_NMI 0x4 #define APIC_MODE_EXINT 0x7 #define APIC_LVT1 0x360 -#define APIC_LVERR 0x370 +#define APIC_LVTERR 0x370 #define APIC_TMICT 0x380 #define APIC_TMCCT 0x390 #define APIC_TDCR 0x3E0 +#define APIC_TDR_DIV_TMBASE (1<<2) #define APIC_TDR_DIV_1 0xB #define APIC_TDR_DIV_2 0x0 #define APIC_TDR_DIV_4 0x1 @@ -92,4 +104,255 @@ #define MAX_IO_APICS 8 +/* + * the local APIC register structure, memory mapped. Not terribly well + * tested, but we might eventually use this one in the future - the + * problem why we cannot use it right now is the P5 APIC, it has an + * errata which cannot take 8-bit reads and writes, only 32-bit ones ... + */ +#define u32 unsigned int + +#define lapic ((volatile struct local_apic *)APIC_BASE) + +struct local_apic { + +/*000*/ struct { u32 __reserved[4]; } __reserved_01; + +/*010*/ struct { u32 __reserved[4]; } __reserved_02; + +/*020*/ struct { /* APIC ID Register */ + u32 __reserved_1 : 24, + phys_apic_id : 4, + __reserved_2 : 4; + u32 __reserved[3]; + } id; + +/*030*/ const + struct { /* APIC Version Register */ + u32 version : 8, + __reserved_1 : 8, + max_lvt : 8, + __reserved_2 : 8; + u32 __reserved[3]; + } version; + +/*040*/ struct { u32 __reserved[4]; } __reserved_03; + +/*050*/ struct { u32 __reserved[4]; } __reserved_04; + +/*060*/ struct { u32 __reserved[4]; } __reserved_05; + +/*070*/ struct { u32 __reserved[4]; } __reserved_06; + +/*080*/ struct { /* Task Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } tpr; + +/*090*/ const + struct { /* Arbitration Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } apr; + +/*0A0*/ const + struct { /* Processor Priority Register */ + u32 priority : 8, + __reserved_1 : 24; + u32 __reserved_2[3]; + } ppr; + +/*0B0*/ struct { /* End Of Interrupt Register */ + u32 eoi; + u32 __reserved[3]; + } eoi; + +/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; + +/*0D0*/ struct { /* Logical Destination Register */ + u32 __reserved_1 : 24, + logical_dest : 8; + u32 __reserved_2[3]; + } ldr; + +/*0E0*/ struct { /* Destination Format Register */ + u32 __reserved_1 : 28, + model : 4; + u32 __reserved_2[3]; + } dfr; + +/*0F0*/ struct { /* Spurious Interrupt Vector Register */ + u32 spurious_vector : 8, + apic_enabled : 1, + focus_cpu : 1, + __reserved_2 : 22; + u32 __reserved_3[3]; + } svr; + +/*100*/ struct { /* In Service Register */ +/*170*/ u32 bitfield; + u32 __reserved[3]; + } isr [8]; + +/*180*/ struct { /* Trigger Mode Register */ +/*1F0*/ u32 bitfield; + u32 __reserved[3]; + } tmr [8]; + +/*200*/ struct { /* Interrupt Request Register */ +/*270*/ u32 bitfield; + u32 __reserved[3]; + } irr [8]; + +/*280*/ union { /* Error Status Register */ + struct { + u32 send_cs_error : 1, + receive_cs_error : 1, + send_accept_error : 1, + receive_accept_error : 1, + __reserved_1 : 1, + send_illegal_vector : 1, + receive_illegal_vector : 1, + illegal_register_address : 1, + __reserved_2 : 24; + u32 __reserved_3[3]; + } error_bits; + struct { + u32 errors; + u32 __reserved_3[3]; + } all_errors; + } esr; + +/*290*/ struct { u32 __reserved[4]; } __reserved_08; + +/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; + +/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; + +/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; + +/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; + +/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; + +/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; + +/*300*/ struct { /* Interrupt Command Register 1 */ + u32 vector : 8, + delivery_mode : 3, + destination_mode : 1, + delivery_status : 1, + __reserved_1 : 1, + level : 1, + trigger : 1, + __reserved_2 : 2, + shorthand : 2, + __reserved_3 : 12; + u32 __reserved_4[3]; + } icr1; + +/*310*/ struct { /* Interrupt Command Register 2 */ + union { + u32 __reserved_1 : 24, + phys_dest : 4, + __reserved_2 : 4; + u32 __reserved_3 : 24, + logical_dest : 8; + } dest; + u32 __reserved_4[3]; + } icr2; + +/*320*/ struct { /* LVT - Timer */ + u32 vector : 8, + __reserved_1 : 4, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + timer_mode : 1, + __reserved_3 : 14; + u32 __reserved_4[3]; + } lvt_timer; + +/*330*/ struct { u32 __reserved[4]; } __reserved_15; + +/*340*/ struct { /* LVT - Performance Counter */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_pc; + +/*350*/ struct { /* LVT - LINT0 */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + polarity : 1, + remote_irr : 1, + trigger : 1, + mask : 1, + __reserved_2 : 15; + u32 __reserved_3[3]; + } lvt_lint0; + +/*360*/ struct { /* LVT - LINT1 */ + u32 vector : 8, + delivery_mode : 3, + __reserved_1 : 1, + delivery_status : 1, + polarity : 1, + remote_irr : 1, + trigger : 1, + mask : 1, + __reserved_2 : 15; + u32 __reserved_3[3]; + } lvt_lint1; + +/*370*/ struct { /* LVT - Error */ + u32 vector : 8, + __reserved_1 : 4, + delivery_status : 1, + __reserved_2 : 3, + mask : 1, + __reserved_3 : 15; + u32 __reserved_4[3]; + } lvt_error; + +/*380*/ struct { /* Timer Initial Count Register */ + u32 initial_count; + u32 __reserved_2[3]; + } timer_icr; + +/*390*/ const + struct { /* Timer Current Count Register */ + u32 curr_count; + u32 __reserved_2[3]; + } timer_ccr; + +/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; + +/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; + +/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; + +/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; + +/*3E0*/ struct { /* Timer Divide Configuration Register */ + u32 divisor : 4, + __reserved_1 : 28; + u32 __reserved_2[3]; + } timer_dcr; + +/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; + +} __attribute__ ((packed)); + +#undef u32 + #endif diff --git a/include/asm-i386/hw_irq.h b/include/asm-i386/hw_irq.h index 8cce40151..894055a7d 100644 --- a/include/asm-i386/hw_irq.h +++ b/include/asm-i386/hw_irq.h @@ -27,33 +27,40 @@ */ /* - * Special IRQ vectors used by the SMP architecture: + * Special IRQ vectors used by the SMP architecture, 0x30-0x4f * - * (some of the following vectors are 'rare', they are merged - * into a single vector (FUNCTION_VECTOR) to save vector space. - * TLB, reschedule and local APIC vectors are performance-critical.) + * some of the following vectors are 'rare', they are merged + * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. + * TLB, reschedule and local APIC vectors are performance-critical. */ -#define RESCHEDULE_VECTOR 0x30 -#define INVALIDATE_TLB_VECTOR 0x31 -#define STOP_CPU_VECTOR 0x40 -#define LOCAL_TIMER_VECTOR 0x41 -#define CALL_FUNCTION_VECTOR 0x50 +#define INVALIDATE_TLB_VECTOR 0x30 +#define LOCAL_TIMER_VECTOR 0x31 +#define RESCHEDULE_VECTOR 0x40 + +/* 'rare' vectors: */ +#define CALL_FUNCTION_VECTOR 0x41 /* - * First APIC vector available to drivers: (vectors 0x51-0xfe) + * These IRQs should never really happen on perfect hardware running + * a perfect kernel, but we nevertheless print a message to catch the + * rest ;) Subtle, the APIC architecture mandates the spurious vector + * to have bits 0-3 set to 1. Note that these vectors do not occur + * normally, so we violate the 'only 2 vectors per priority level' + * rule here. */ -#define IRQ0_TRAP_VECTOR 0x51 +#define SPURIOUS_APIC_VECTOR 0x3f +#define ERROR_APIC_VECTOR 0x43 /* - * This IRQ should never happen, but we print a message nevertheless. + * First APIC vector available to drivers: (vectors 0x51-0xfe) + * we start at 0x51 to spread out vectors between priority levels + * evenly. (note that 0x80 is the syscall vector) */ -#define SPURIOUS_APIC_VECTOR 0xff +#define IRQ0_TRAP_VECTOR 0x51 extern int irq_vector[NR_IRQS]; #define IO_APIC_VECTOR(irq) irq_vector[irq] -extern void init_IRQ_SMP(void); - /* * Various low-level irq details needed by irq.c, process.c, * time.c, io_apic.c and smp.c @@ -65,18 +72,20 @@ extern void no_action(int cpl, void *dev_id, struct pt_regs *regs); extern void mask_irq(unsigned int irq); extern void unmask_irq(unsigned int irq); extern void disable_8259A_irq(unsigned int irq); +extern void enable_8259A_irq(unsigned int irq); extern int i8259A_irq_pending(unsigned int irq); -extern void ack_APIC_irq(void); +extern void make_8259A_irq(unsigned int irq); +extern void init_8259A(int aeoi); extern void FASTCALL(send_IPI_self(int vector)); extern void init_VISWS_APIC_irqs(void); extern void setup_IO_APIC(void); extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn); -extern void make_8259A_irq(unsigned int irq); extern void send_IPI(int dest, int vector); extern void init_pic_mode(void); extern void print_IO_APIC(void); extern unsigned long io_apic_irqs; +extern volatile unsigned long irq_err_count; extern char _stext, _etext; @@ -214,6 +223,7 @@ static inline void x86_do_profile (unsigned long eip) #ifdef __SMP__ /*more of this file should probably be ifdefed SMP */ static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) { + if (IO_APIC_IRQ(i)) send_IPI_self(IO_APIC_VECTOR(i)); } #else diff --git a/include/asm-i386/irq.h b/include/asm-i386/irq.h index 436ad1d21..9b8f64a3c 100644 --- a/include/asm-i386/irq.h +++ b/include/asm-i386/irq.h @@ -13,7 +13,7 @@ #define TIMER_IRQ 0 /* - * 16 8259A IRQ's, 240 potential APIC interrupt sources. + * 16 8259A IRQ's, 208 potential APIC interrupt sources. * Right now the APIC is mostly only used for SMP. * 256 vectors is an architectural limit. (we can have * more than 256 devices theoretically, but they will diff --git a/include/asm-i386/keyboard.h b/include/asm-i386/keyboard.h index 2a7effa3c..4b308f746 100644 --- a/include/asm-i386/keyboard.h +++ b/include/asm-i386/keyboard.h @@ -2,8 +2,6 @@ * linux/include/asm-i386/keyboard.h * * Created 3 Nov 1996 by Geert Uytterhoeven - * - * $Id: keyboard.h,v 1.8 1999/06/10 08:02:38 ralf Exp $ */ /* @@ -16,6 +14,7 @@ #ifdef __KERNEL__ #include <linux/kernel.h> +#include <linux/ioport.h> #include <asm/io.h> #define KEYBOARD_IRQ 1 @@ -40,6 +39,11 @@ extern unsigned char pckbd_sysrq_xlate[128]; #define SYSRQ_KEY 0x54 +/* resource allocation */ +#define kbd_request_region() +#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \ + "keyboard", NULL) + /* How to access the keyboard macros on this platform. */ #define kbd_read_input() inb(KBD_DATA_REG) #define kbd_read_status() inb(KBD_STATUS_REG) @@ -47,13 +51,7 @@ extern unsigned char pckbd_sysrq_xlate[128]; #define kbd_write_command(val) outb(val, KBD_CNTL_REG) /* Some stoneage hardware needs delays after some operations. */ -#define kbd_pause() do { SLOW_DOWN_IO; } while(0) - -/* Get the keyboard controller registers (incomplete decode) */ -#define kbd_request_region() request_region(0x60, 16, "keyboard") - -#define kbd_request_irq() request_irq(KEYBOARD_IRQ, keyboard_interrupt, 0, \ - "keyboard", NULL); +#define kbd_pause() do { } while(0) /* * Machine specific bits for the PS/2 driver @@ -61,8 +59,10 @@ extern unsigned char pckbd_sysrq_xlate[128]; #define AUX_IRQ 12 -#define aux_free_irq(dev_id) free_irq(AUX_IRQ, AUX_DEV) -request_irq(AUX_IRQ, keyboard_interrupt, SA_SHIRQ, "PS/2 Mouse", AUX_DEV) +#define aux_request_irq(hand, dev_id) \ + request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS/2 Mouse", dev_id) + +#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) #endif /* __KERNEL__ */ -#endif /* __ASM_i386_KEYBOARD_H */ +#endif /* _I386_KEYBOARD_H */ diff --git a/include/asm-i386/mmx.h b/include/asm-i386/mmx.h new file mode 100644 index 000000000..721a8e933 --- /dev/null +++ b/include/asm-i386/mmx.h @@ -0,0 +1,14 @@ +#ifndef _ASM_MMX_H +#define _ASM_MMX_H + +/* + * MMX 3Dnow! helper operations + */ + +#include <linux/types.h> + +extern void *_mmx_memcpy(void *to, const void *from, size_t size); +extern void mmx_clear_page(long page); +extern void mmx_copy_page(long to, long from); + +#endif diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index 1ed8ea851..515a8dc5c 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -23,6 +23,8 @@ #define rdtscll(val) \ __asm__ __volatile__ ("rdtsc" : "=A" (val)) +#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) + #define rdpmc(counter,low,high) \ __asm__ __volatile__("rdpmc" \ : "=a" (low), "=d" (high) \ diff --git a/include/asm-i386/page.h b/include/asm-i386/page.h index 2e5006f4a..c3719d5d9 100644 --- a/include/asm-i386/page.h +++ b/include/asm-i386/page.h @@ -11,9 +11,27 @@ #define STRICT_MM_TYPECHECKS +#include <linux/config.h> + +#ifdef CONFIG_X86_USE_3DNOW + +#include <asm/mmx.h> + +#define clear_page(page) mmx_clear_page(page) +#define copy_page(to,from) mmx_copy_page(to,from) + +#else + +/* + * On older X86 processors its not a win to use MMX here it seems. + * Maybe the K6-III ? + */ + #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) #define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) +#endif + #ifdef STRICT_MM_TYPECHECKS /* * These are used to make use of C type-checking.. diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 99b291d40..939ca0b31 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -106,6 +106,9 @@ extern struct cpuinfo_x86 cpu_data[]; #define current_cpu_data boot_cpu_data #endif +#define cpu_has_tsc \ + (cpu_data[smp_processor_id()].x86_capability & X86_FEATURE_TSC) + extern char ignore_irq13; extern void identify_cpu(struct cpuinfo_x86 *); diff --git a/include/asm-i386/smp.h b/include/asm-i386/smp.h index 91199de7f..52c27bead 100644 --- a/include/asm-i386/smp.h +++ b/include/asm-i386/smp.h @@ -123,17 +123,19 @@ struct mpc_config_intsrc unsigned char mpc_dstirq; }; -#define MP_INT_VECTORED 0 -#define MP_INT_NMI 1 -#define MP_INT_SMI 2 -#define MP_INT_EXTINT 3 +enum mp_irq_source_types { + mp_INT = 0, + mp_NMI = 1, + mp_SMI = 2, + mp_ExtINT = 3 +}; #define MP_IRQDIR_DEFAULT 0 #define MP_IRQDIR_HIGH 1 #define MP_IRQDIR_LOW 3 -struct mpc_config_intlocal +struct mpc_config_lintsrc { unsigned char mpc_type; unsigned char mpc_irqtype; @@ -150,7 +152,7 @@ struct mpc_config_intlocal * Default configurations * * 1 2 CPU ISA 82489DX - * 2 2 CPU EISA 82489DX no IRQ 8 or timer chaining + * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining * 3 2 CPU EISA 82489DX * 4 2 CPU MCA 82489DX * 5 2 CPU ISA+PCI @@ -165,21 +167,19 @@ struct mpc_config_intlocal extern int smp_found_config; extern void init_smp_config(void); extern unsigned long smp_alloc_memory(unsigned long mem_base); -extern unsigned char boot_cpu_id; extern unsigned long cpu_present_map; extern unsigned long cpu_online_map; -extern volatile int cpu_number_map[NR_CPUS]; extern volatile unsigned long smp_invalidate_needed; +extern int pic_mode; extern void smp_flush_tlb(void); - -extern volatile unsigned long cpu_callin_map[NR_CPUS]; +extern int get_maxlvt(void); extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs); extern void smp_send_reschedule(int cpu); -extern unsigned long ipi_count; extern void smp_invalidate_rcv(void); /* Process an NMI */ extern void smp_local_timer_interrupt(struct pt_regs * regs); extern void (*mtrr_hook) (void); -extern void setup_APIC_clock (void); +extern void setup_APIC_clocks(void); +extern volatile int cpu_number_map[NR_CPUS]; extern volatile int __cpu_logical_map[NR_CPUS]; extern inline int cpu_logical_map(int cpu) { @@ -196,12 +196,35 @@ extern __inline unsigned long apic_read(unsigned long reg) return *((volatile unsigned long *)(APIC_BASE+reg)); } +extern unsigned int apic_timer_irqs [NR_CPUS]; + +#ifdef CONFIG_X86_GOOD_APIC +# define FORCE_READ_AROUND_WRITE 0 +# define apic_readaround(x) +#else +# define FORCE_READ_AROUND_WRITE 1 +# define apic_readaround(x) apic_read(x) +#endif + +#define apic_write_around(x,y) \ + do { apic_readaround(x); apic_write(x,y); } while (0) + +extern inline void ack_APIC_irq(void) +{ + /* Clear the IPI */ + + apic_readaround(APIC_EOI); + /* + * on P6+ cores (CONFIG_X86_GOOD_APIC) ack_APIC_irq() actually + * gets compiled as a single instruction ... yummie. + */ + apic_write(APIC_EOI, 0); /* Docs say use 0 for future compatibility */ +} /* * General functions that each host system must provide. */ -extern void smp_callin(void); extern void smp_boot_cpus(void); extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */ diff --git a/include/asm-i386/string-486.h b/include/asm-i386/string-486.h index 34f5c16b1..4b5c5fe25 100644 --- a/include/asm-i386/string-486.h +++ b/include/asm-i386/string-486.h @@ -14,6 +14,8 @@ * 1994/03/15 by Alberto Vignani/Davide Parodi @crf.it * * Split into 2 CPU specific files by Alan Cox to keep #ifdef noise down. + * + * 99/9/15 Proper reg args for newer gcc/egcs - Petkan (petkan@spct.net) */ #define __HAVE_ARCH_STRCPY @@ -180,6 +182,7 @@ return __res; #define __HAVE_ARCH_STRRCHR extern inline char * strrchr(const char * s, int c) { +int d0, d1; register char * __res; __asm__ __volatile__( "cld\n\t" @@ -190,17 +193,19 @@ __asm__ __volatile__( "leal -1(%%esi),%0\n" "2:\ttestb %%al,%%al\n\t" "jne 1b" - :"=d" (__res):"0" (0),"S" (s),"a" (c):"ax","si"); + :"=d" (__res), "=&S" (d0), "=&a" (d1) + :"0" (0), "1" (s), "2" (c)); return __res; } #define __HAVE_ARCH_STRSPN extern inline size_t strspn(const char * cs, const char * ct) { +int d0, d1; register char * __res; __asm__ __volatile__( "cld\n\t" - "movl %4,%%edi\n\t" + "movl %6,%%edi\n\t" "repne\n\t" "scasb\n\t" "notl %%ecx\n\t" @@ -209,24 +214,26 @@ __asm__ __volatile__( "1:\tlodsb\n\t" "testb %%al,%%al\n\t" "je 2f\n\t" - "movl %4,%%edi\n\t" + "movl %6,%%edi\n\t" "movl %%edx,%%ecx\n\t" "repne\n\t" "scasb\n\t" "je 1b\n" "2:\tdecl %0" - :"=S" (__res):"a" (0),"c" (0xffffffff),"0" (cs),"g" (ct) - :"ax","cx","dx","di"); + :"=S" (__res), "=&a" (d0), "=&c" (d1) + :"0" (cs), "1" (0), "2" (0xffffffff), "g" (ct) + :"dx", "di"); return __res-cs; } #define __HAVE_ARCH_STRCSPN extern inline size_t strcspn(const char * cs, const char * ct) { +int d0, d1; register char * __res; __asm__ __volatile__( "cld\n\t" - "movl %4,%%edi\n\t" + "movl %6,%%edi\n\t" "repne\n\t" "scasb\n\t" "notl %%ecx\n\t" @@ -235,20 +242,22 @@ __asm__ __volatile__( "1:\tlodsb\n\t" "testb %%al,%%al\n\t" "je 2f\n\t" - "movl %4,%%edi\n\t" + "movl %6,%%edi\n\t" "movl %%edx,%%ecx\n\t" "repne\n\t" "scasb\n\t" "jne 1b\n" "2:\tdecl %0" - :"=S" (__res):"a" (0),"c" (0xffffffff),"0" (cs),"g" (ct) - :"ax","cx","dx","di"); + :"=S" (__res), "=&a" (d0), "=&c" (d1) + :"0" (cs), "1" (0), "2" (0xffffffff), "g" (ct) + :"dx", "di"); return __res-cs; } #define __HAVE_ARCH_STRPBRK extern inline char * strpbrk(const char * cs,const char * ct) { +int d0, d1; register char * __res; __asm__ __volatile__( "cld\n\t" @@ -270,14 +279,16 @@ __asm__ __volatile__( "jmp 3f\n" "2:\txorl %0,%0\n" "3:" - :"=S" (__res):"a" (0),"c" (0xffffffff),"0" (cs),"g" (ct) - :"ax","cx","dx","di"); + :"=S" (__res), "=&a" (d0), "=&c" (d1) + :"0" (cs), "1" (0), "2" (0xffffffff), "g" (ct) + :"dx", "di"); return __res; } #define __HAVE_ARCH_STRSTR extern inline char * strstr(const char * cs,const char * ct) { +int d0, d1; register char * __res; __asm__ __volatile__( "cld\n\t" \ @@ -299,8 +310,9 @@ __asm__ __volatile__( "jne 1b\n\t" "xorl %%eax,%%eax\n\t" "2:" - :"=a" (__res):"0" (0),"c" (0xffffffff),"S" (cs),"g" (ct) - :"cx","dx","di","si"); + :"=a" (__res), "=&c" (d0), "=&S" (d1) + :"0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) + :"dx", "di"); return __res; } @@ -328,6 +340,7 @@ return (tmp-s-1); #define __HAVE_ARCH_STRNLEN extern inline size_t strnlen(const char * s, size_t count) { +int d0; register int __res; __asm__ __volatile__( "movl %1,%0\n\t" @@ -339,9 +352,8 @@ __asm__ __volatile__( "cmpl $-1,%2\n\t" "jne 1b\n" "3:\tsubl %1,%0" - :"=a" (__res) - :"c" (s),"d" (count) - :"dx"); + :"=a" (__res), "=&d" (d0) + :"1" (count), "c" (s)); return __res; } /* end of additional stuff */ @@ -464,6 +476,7 @@ return (to); extern inline void * __memcpy_g(void * to, const void * from, size_t n) { +int d0, d1, d2; register void *tmp = (void *)to; __asm__ __volatile__ ( "cld\n\t" @@ -475,9 +488,9 @@ __asm__ __volatile__ ( "movsw\n" "2:\trep\n\t" "movsl" - : /* no output */ - :"c" (n),"D" ((long) tmp),"S" ((long) from) - :"cx","di","si","memory"); + :"=&c" (d0), "=&D" (d1), "=&S" (d2) + :"0" (n), "1" ((long) tmp), "2" ((long) from) + :"memory"); return (to); } @@ -485,29 +498,31 @@ return (to); #define __HAVE_ARCH_MEMMOVE extern inline void * memmove(void * dest,const void * src, size_t n) { +int d0, d1, d2; register void *tmp = (void *)dest; if (dest<src) __asm__ __volatile__ ( "cld\n\t" "rep\n\t" "movsb" - : /* no output */ - :"c" (n),"S" (src),"D" (tmp) - :"cx","si","di"); + :"=&c" (d0), "=&S" (d1), "=&D" (d2) + :"0" (n), "1" (src), "2" (tmp) + :"memory"); else __asm__ __volatile__ ( "std\n\t" "rep\n\t" "movsb\n\t" "cld" - : /* no output */ - :"c" (n), "S" (n-1+(const char *)src), "D" (n-1+(char *)tmp) - :"cx","si","di","memory"); + :"=&c" (d0), "=&S" (d1), "=&D" (d2) + :"0" (n), "1" (n-1+(const char *)src), "2" (n-1+(char *)tmp) + :"memory"); return dest; } extern inline int memcmp(const void * cs,const void * ct,size_t count) { +int d0, d1, d2; register int __res; __asm__ __volatile__( "cld\n\t" @@ -517,14 +532,15 @@ __asm__ __volatile__( "sbbl %0,%0\n\t" "orb $1,%b0\n" "1:" - :"=abd" (__res):"0" (0),"S" (cs),"D" (ct),"c" (count) - :"si","di","cx"); + :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2) + :"0" (0), "1" (cs), "2" (ct), "3" (count)); return __res; } #define __HAVE_ARCH_MEMCHR extern inline void * memchr(const void * cs,int c,size_t count) { +int d0; register void * __res; if (!count) return NULL; @@ -535,8 +551,8 @@ __asm__ __volatile__( "je 1f\n\t" "movl $1,%0\n" "1:\tdecl %0" - :"=D" (__res):"a" (c),"D" (cs),"c" (count) - :"cx"); + :"=D" (__res), "=&c" (d0) + :"a" (c), "0" (cs), "1" (count)); return __res; } @@ -643,6 +659,7 @@ return s; extern inline void * __memset_cg(void * s, char c, size_t count) { +int d0, d1; register void *tmp = (void *)s; __asm__ __volatile__ ( "shrl $1,%%ecx\n\t" @@ -651,14 +668,15 @@ __asm__ __volatile__ ( "jnc 1f\n\t" "movb %%al,(%%edi)\n" "1:" - : /* no output */ - :"c" (count),"D" (tmp), "a" (0x0101U * (unsigned char) c) - :"cx","di","memory"); + :"=&c" (d0), "=&D" (d1) + :"a" (0x0101U * (unsigned char) c), "0" (count), "1" (tmp) + :"memory"); return s; } extern inline void * __memset_gg(void * s,char c,size_t count) { +int d0, d1, d2; register void *tmp = (void *)s; __asm__ __volatile__ ( "movb %%al,%%ah\n\t" @@ -668,9 +686,9 @@ __asm__ __volatile__ ( "jnc 1f\n\t" "movb %%al,(%%edi)\n" "1:" - : /* no output */ - :"c" (count),"D" (tmp), "a" (c) - :"cx","di","memory"); + :"=&c" (d0), "=&D" (d1), "=&D" (d2) + :"0" (count), "1" (tmp), "2" (c) + :"memory"); return s; } diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h index 8417d4aba..e03928ede 100644 --- a/include/asm-i386/string.h +++ b/include/asm-i386/string.h @@ -293,11 +293,55 @@ __asm__ __volatile__( \ } #define __HAVE_ARCH_MEMCPY + +#include <linux/config.h> + +#ifdef CONFIG_X86_USE_3DNOW + +/* All this just for in_interrupt() ... */ + +#include <asm/system.h> +#include <asm/ptrace.h> +#include <linux/smp.h> +#include <linux/interrupt.h> +#include <asm/mmx.h> + +/* + * This CPU favours 3DNow strongly (eg AMD Athlon) + */ + +extern inline void * __constant_memcpy3d(void * to, const void * from, size_t len) +{ + if(len<512 || in_interrupt()) + return __constant_memcpy(to, from, len); + return _mmx_memcpy(to, from, len); +} + +extern __inline__ void *__memcpy3d(void *to, const void *from, size_t len) +{ + if(len<512 || in_interrupt()) + return __memcpy(to, from, len); + return _mmx_memcpy(to, from, len); +} + +#define memcpy(t, f, n) \ +(__builtin_constant_p(n) ? \ + __constant_memcpy3d((t),(f),(n)) : \ + __memcpy3d((t),(f),(n))) + +#else + +/* + * No 3D Now! + */ + #define memcpy(t, f, n) \ (__builtin_constant_p(n) ? \ __constant_memcpy((t),(f),(n)) : \ __memcpy((t),(f),(n))) +#endif + #define __HAVE_ARCH_MEMMOVE extern inline void * memmove(void * dest,const void * src, size_t n) { diff --git a/include/asm-i386/uaccess.h b/include/asm-i386/uaccess.h index 2b1b3d7f4..7546159f6 100644 --- a/include/asm-i386/uaccess.h +++ b/include/asm-i386/uaccess.h @@ -597,7 +597,8 @@ __constant_copy_from_user_nocheck(void *to, const void *from, unsigned long n) long strncpy_from_user(char *dst, const char *src, long count); long __strncpy_from_user(char *dst, const char *src, long count); -long strlen_user(const char *str); +#define strlen_user(str) strnlen_user(str, ~0UL >> 1) +long strnlen_user(const char *str, long n); unsigned long clear_user(void *mem, unsigned long len); unsigned long __clear_user(void *mem, unsigned long len); diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 1149bc03f..41ffde38d 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -1,4 +1,4 @@ -/* $Id: mmu_context.h,v 1.4 1999/08/09 19:43:17 harald Exp $ +/* $Id: mmu_context.h,v 1.5 1999/10/09 00:01:43 ralf Exp $ * * Switch a MMU context. * @@ -16,6 +16,7 @@ /* Fuck. The f-word is here so you can grep for it :-) */ extern unsigned long asid_cache; +extern pgd_t *current_pgd; #if defined(CONFIG_CPU_R3000) @@ -47,19 +48,6 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long asid) mm->context = asid_cache = asid; } -extern inline void -get_mmu_context(struct task_struct *p) -{ - struct mm_struct *mm = p->mm; - - if (mm) { - unsigned long asid = asid_cache; - /* Check if our ASID is of an older version and thus invalid */ - if ((mm->context ^ asid) & ASID_VERSION_MASK) - get_new_mmu_context(mm, asid); - } -} - /* * Initialize the context related info for a new mm_struct * instance. @@ -73,13 +61,13 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm) extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk, unsigned cpu) { - if (next) { - unsigned long asid = asid_cache; - /* Check if our ASID is of an older version and thus invalid */ - if ((next->context ^ asid) & ASID_VERSION_MASK) - get_new_mmu_context(next, asid); - } + unsigned long asid = asid_cache; + + /* Check if our ASID is of an older version and thus invalid */ + if ((next->context ^ asid) & ASID_VERSION_MASK) + get_new_mmu_context(next, asid); + current_pgd = next->pgd; set_entryhi(next->context); } @@ -99,9 +87,10 @@ extern inline void destroy_context(struct mm_struct *mm) extern inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) { - /* Unconditionally get an new ASID. */ + /* Unconditionally get a new ASID. */ get_new_mmu_context(next, asid_cache); + current_pgd = next->pgd; set_entryhi(next->context); } diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index ca561233e..b21f9d874 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -1,4 +1,4 @@ -/* $Id: processor.h,v 1.20 1999/10/09 00:01:43 ralf Exp $ +/* $Id: processor.h,v 1.21 1999/10/12 17:33:50 harald Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -196,13 +196,13 @@ extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); */ extern inline unsigned long thread_saved_pc(struct thread_struct *t) { - extern void ret_from_sys_call(void); + extern void ret_from_fork(void); /* New born processes are a special case */ - if (t->reg31 == (unsigned long) ret_from_sys_call) + if (t->reg31 == (unsigned long) ret_from_fork) return t->reg31; - return ((unsigned long*)t->reg29)[17]; + return ((unsigned long *)t->reg29)[10]; } /* diff --git a/include/asm-mips/segment.h b/include/asm-mips/segment.h index 0453d97da..92ac001fc 100644 --- a/include/asm-mips/segment.h +++ b/include/asm-mips/segment.h @@ -1,6 +1,6 @@ -#ifndef __ALPHA_SEGMENT_H -#define __ALPHA_SEGMENT_H +#ifndef _ASM_SEGMENT_H +#define _ASM_SEGMENT_H /* Only here because we have some old header files that expect it.. */ -#endif +#endif /* _ASM_SEGMENT_H */ diff --git a/include/asm-mips/softirq.h b/include/asm-mips/softirq.h index f225e87ba..a7e7a074a 100644 --- a/include/asm-mips/softirq.h +++ b/include/asm-mips/softirq.h @@ -1,13 +1,14 @@ -/* $Id: softirq.h,v 1.8 1999/08/13 17:07:27 harald Exp $ +/* $Id: softirq.h,v 1.9 1999/11/19 20:35:48 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1997, 1998, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_MIPS_SOFTIRQ_H -#define __ASM_MIPS_SOFTIRQ_H +#ifndef _ASM_SOFTIRQ_H +#define _ASM_SOFTIRQ_H #include <linux/config.h> @@ -106,4 +107,4 @@ extern inline void end_bh_atomic(void) #define softirq_endlock(cpu) (cpu_bh_endlock(cpu)) #define synchronize_bh() barrier() -#endif /* __ASM_MIPS_SOFTIRQ_H */ +#endif /* _ASM_SOFTIRQ_H */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 1c02b93d9..490724b21 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -3,7 +3,7 @@ * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Paul M. Antoine. * - * $Id: stackframe.h,v 1.9 1999/07/26 19:42:44 harald Exp $ + * $Id: stackframe.h,v 1.10 1999/08/13 17:07:27 harald Exp $ */ #ifndef __ASM_MIPS_STACKFRAME_H #define __ASM_MIPS_STACKFRAME_H @@ -13,7 +13,10 @@ #include <linux/config.h> #define SAVE_AT \ - sw $1, PT_R1(sp) + .set push; \ + .set noat; \ + sw $1, PT_R1(sp); \ + .set pop #define SAVE_TEMP \ mfhi v1; \ @@ -101,7 +104,10 @@ SAVE_STATIC #define RESTORE_AT \ + .set push; \ + .set noat; \ lw $1, PT_R1(sp); \ + .set pop; #define RESTORE_TEMP \ lw $24, PT_LO(sp); \ diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index fa0e78feb..1f8c2722a 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -1,14 +1,15 @@ -/* $Id: system.h,v 1.17 1999/10/12 17:33:50 harald Exp $ +/* $Id: system.h,v 1.18 1999/11/17 22:48:12 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle - * Modified further for R[236]000 by Paul M. Antoine, 1996 + * Copyright (C) 1994 - 1999 by Ralf Baechle + * Copyright (C) 1996 by Paul M. Antoine + * Copyright (C) 1994 - 1999 by Ralf Baechle */ -#ifndef __ASM_MIPS_SYSTEM_H -#define __ASM_MIPS_SYSTEM_H +#ifndef _ASM_SYSTEM_H +#define _ASM_SYSTEM_H #include <linux/config.h> #include <linux/kernel.h> @@ -186,7 +187,7 @@ extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) "1:\tmove\t$1,%2\n\t" "sc\t$1,(%1)\n\t" "beqzl\t$1,1b\n\t" - "ll\t%0,(%1)\n\t" + "lld\t%0,(%1)\n\t" ".set\tat\n\t" ".set\treorder" : "=r" (val), "=r" (m), "=r" (dummy) @@ -260,4 +261,14 @@ static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int extern void set_except_vector(int n, void *addr); -#endif /* __ASM_MIPS_SYSTEM_H */ +extern void __die(const char *, struct pt_regs *, const char *where, + unsigned long line) __attribute__((noreturn)); +extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, + unsigned long line); + +#define die(msg, regs) \ + __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) +#define die_if_kernel(msg, regs) do { \ + __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + +#endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index a9b759313..62432d9b4 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -1,16 +1,14 @@ -/* - * include/asm-mips/uaccess.h +/* $Id: uaccess.h,v 1.9 1999/10/09 00:01:43 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 1998 by Ralf Baechle - * - * $Id: uaccess.h,v 1.8 1999/01/04 16:09:27 ralf Exp $ + * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ -#ifndef __ASM_MIPS_UACCESS_H -#define __ASM_MIPS_UACCESS_H +#ifndef _ASM_UACCESS_H +#define _ASM_UACCESS_H #include <linux/errno.h> #include <linux/sched.h> @@ -25,8 +23,8 @@ * * For historical reasons, these macros are grossly misnamed. */ -#define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { 1UL }) +#define KERNEL_DS ((mm_segment_t) { (unsigned long) 0L }) +#define USER_DS ((mm_segment_t) { (unsigned long) -1L }) #define VERIFY_READ 0 #define VERIFY_WRITE 1 @@ -50,7 +48,7 @@ */ #define __access_ok(addr,size,mask) \ (((__signed__ long)((mask)&(addr | size | (addr+size)))) >= 0) -#define __access_mask (-(long)(get_fs().seg)) +#define __access_mask ((long)(get_fs().seg)) #define access_ok(type,addr,size) \ __access_ok(((unsigned long)(addr)),(size),__access_mask) @@ -449,7 +447,6 @@ strncpy_from_user(char *__to, const char *__from, long __len) return res; } - /* Returns: 0 if bad, string length+1 (memory size) of string if ok */ extern inline long __strlen_user(const char *s) { @@ -481,6 +478,39 @@ extern inline long strlen_user(const char *s) return res; } +/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ +extern inline long __strnlen_user(const char *s, long n) +{ + long res; + + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", "$8", "$31"); + + return res; +} + +extern inline long strnlen_user(const char *s, long n) +{ + long res; + + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strnlen_user_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", "$8", "$31"); + + return res; +} + struct exception_table_entry { unsigned long insn; @@ -496,4 +526,4 @@ extern unsigned long search_exception_table(unsigned long addr); fixup_unit; \ }) -#endif /* __ASM_MIPS_UACCESS_H */ +#endif /* _ASM_UACCESS_H */ diff --git a/include/asm-mips64/addrspace.h b/include/asm-mips64/addrspace.h index dacd948da..d8d5a90a5 100644 --- a/include/asm-mips64/addrspace.h +++ b/include/asm-mips64/addrspace.h @@ -1,10 +1,11 @@ -/* $Id$ +/* $Id: addrspace.h,v 1.2 1999/10/19 20:51:53 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996 by Ralf Baechle + * Copyright (C) 1996, 1999 by Ralf Baechle + * Copyright (C) 1999 by Silicon Graphics, Inc. */ #ifndef _ASM_ADDRSPACE_H #define _ASM_ADDRSPACE_H @@ -12,11 +13,11 @@ /* * Memory segments (32bit kernel mode addresses) */ -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 +#define KUSEG 0x0000000000000000 +#define KSEG0 0xffffffff80000000 +#define KSEG1 0xffffffffa0000000 +#define KSEG2 0xffffffffc0000000 +#define KSEG3 0xffffffffe0000000 /* * Returns the kernel segment base of a given address diff --git a/include/asm-mips64/arc/types.h b/include/asm-mips64/arc/types.h index b1d72e10e..685580411 100644 --- a/include/asm-mips64/arc/types.h +++ b/include/asm-mips64/arc/types.h @@ -22,6 +22,18 @@ typedef unsigned short USHORT; typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__))); typedef void VOID; +/* The pointer types. Note that we're using a 64-bit compiler but all + pointer in the ARC structures are only 32-bit, so we need some disgusting + workarounds. Keep your vomit bag handy. */ +typedef LONG _PCHAR; +typedef LONG _PSHORT; +typedef LONG _PLARGE_INTEGER; +typedef LONG _PLONG; +typedef LONG _PUCHAR; +typedef LONG _PUSHORT; +typedef LONG _PULONG; +typedef LONG _PVOID; + #endif /* CONFIG_ARC32 */ #ifdef CONFIG_ARC64 @@ -35,6 +47,26 @@ typedef unsigned short USHORT; typedef unsigned long ULONG __attribute__ (__mode__ (__DI__)); typedef void VOID; +/* The pointer types. We're 64-bit and the firmware is also 64-bit, so + live is sane ... */ +typedef CHAR *_PCHAR; +typedef SHORT *_PSHORT; +typedef LARGE_INTEGER *_PLARGE_INTEGER; +typedef LONG *_PLONG; +typedef UCHAR *_PUCHAR; +typedef USHORT *_PUSHORT; +typedef ULONG *_PULONG; +typedef VOID *_PVOID; + #endif /* CONFIG_ARC64 */ +typedef CHAR *PCHAR; +typedef SHORT *PSHORT; +typedef LARGE_INTEGER *PLARGE_INTEGER; +typedef LONG *PLONG; +typedef UCHAR *PUCHAR; +typedef USHORT *PUSHORT; +typedef ULONG *PULONG; +typedef VOID *PVOID; + #endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips64/asm.h b/include/asm-mips64/asm.h index c25e118a8..fe616eb08 100644 --- a/include/asm-mips64/asm.h +++ b/include/asm-mips64/asm.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: asm.h,v 1.1 1999/08/18 23:37:50 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -96,6 +96,17 @@ symbol = value .set pop; \ TEXT(string) +/* + * Print formated string + */ +#define PROM_PRINT(string) \ + .set push; \ + .set reorder; \ + la a0,8f; \ + jal prom_printf; \ + .set pop; \ + TEXT(string) + #define TEXT(msg) \ .data; \ 8: .asciiz msg; \ diff --git a/include/asm-mips64/asmmacro.h b/include/asm-mips64/asmmacro.h new file mode 100644 index 000000000..240bde270 --- /dev/null +++ b/include/asm-mips64/asmmacro.h @@ -0,0 +1,193 @@ +/* $Id: asmmacro.h,v 1.2 1999/10/19 20:51:53 ralf Exp $ + * + * asmmacro.h: Assembler macros to make things easier to read. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1998, 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_ASMMACRO_H +#define _ASM_ASMMACRO_H + +#include <asm/offset.h> + + .macro fpu_save_16even thread tmp + cfc1 \tmp, fcr31 + sdc1 $f2, (THREAD_FPU + 0x010)(\thread) + sdc1 $f4, (THREAD_FPU + 0x020)(\thread) + sdc1 $f6, (THREAD_FPU + 0x030)(\thread) + sdc1 $f8, (THREAD_FPU + 0x040)(\thread) + sdc1 $f10, (THREAD_FPU + 0x050)(\thread) + sdc1 $f12, (THREAD_FPU + 0x060)(\thread) + sdc1 $f14, (THREAD_FPU + 0x070)(\thread) + sdc1 $f16, (THREAD_FPU + 0x080)(\thread) + sdc1 $f18, (THREAD_FPU + 0x090)(\thread) + sdc1 $f20, (THREAD_FPU + 0x0a0)(\thread) + sdc1 $f22, (THREAD_FPU + 0x0b0)(\thread) + sdc1 $f24, (THREAD_FPU + 0x0c0)(\thread) + sdc1 $f26, (THREAD_FPU + 0x0d0)(\thread) + sdc1 $f28, (THREAD_FPU + 0x0e0)(\thread) + sdc1 $f30, (THREAD_FPU + 0x0f0)(\thread) + sw \tmp, (THREAD_FPU + 0x100)(\thread) + .endm + + .macro fpu_save_16odd thread + sdc1 $f1, (THREAD_FPU + 0x08)(\thread) + sdc1 $f3, (THREAD_FPU + 0x18)(\thread) + sdc1 $f5, (THREAD_FPU + 0x28)(\thread) + sdc1 $f7, (THREAD_FPU + 0x38)(\thread) + sdc1 $f9, (THREAD_FPU + 0x48)(\thread) + sdc1 $f11, (THREAD_FPU + 0x58)(\thread) + sdc1 $f13, (THREAD_FPU + 0x68)(\thread) + sdc1 $f15, (THREAD_FPU + 0x78)(\thread) + sdc1 $f17, (THREAD_FPU + 0x88)(\thread) + sdc1 $f19, (THREAD_FPU + 0x98)(\thread) + sdc1 $f21, (THREAD_FPU + 0xa8)(\thread) + sdc1 $f23, (THREAD_FPU + 0xb8)(\thread) + sdc1 $f25, (THREAD_FPU + 0xc8)(\thread) + sdc1 $f27, (THREAD_FPU + 0xd8)(\thread) + sdc1 $f29, (THREAD_FPU + 0xe8)(\thread) + sdc1 $f31, (THREAD_FPU + 0xf8)(\thread) + .endm + + .macro fpu_save thread tmp + cfc1 \tmp, fcr31 + swc1 $f0, (THREAD_FPU + 0x000)(\thread) + swc1 $f1, (THREAD_FPU + 0x008)(\thread) + swc1 $f2, (THREAD_FPU + 0x010)(\thread) + swc1 $f3, (THREAD_FPU + 0x018)(\thread) + swc1 $f4, (THREAD_FPU + 0x020)(\thread) + swc1 $f5, (THREAD_FPU + 0x028)(\thread) + swc1 $f6, (THREAD_FPU + 0x030)(\thread) + swc1 $f7, (THREAD_FPU + 0x038)(\thread) + swc1 $f8, (THREAD_FPU + 0x040)(\thread) + swc1 $f9, (THREAD_FPU + 0x048)(\thread) + swc1 $f10, (THREAD_FPU + 0x050)(\thread) + swc1 $f11, (THREAD_FPU + 0x058)(\thread) + swc1 $f12, (THREAD_FPU + 0x060)(\thread) + swc1 $f13, (THREAD_FPU + 0x068)(\thread) + swc1 $f14, (THREAD_FPU + 0x070)(\thread) + swc1 $f15, (THREAD_FPU + 0x078)(\thread) + swc1 $f16, (THREAD_FPU + 0x080)(\thread) + swc1 $f17, (THREAD_FPU + 0x088)(\thread) + swc1 $f18, (THREAD_FPU + 0x090)(\thread) + swc1 $f19, (THREAD_FPU + 0x098)(\thread) + swc1 $f20, (THREAD_FPU + 0x0a0)(\thread) + swc1 $f21, (THREAD_FPU + 0x0a8)(\thread) + swc1 $f22, (THREAD_FPU + 0x0b0)(\thread) + swc1 $f23, (THREAD_FPU + 0x0b8)(\thread) + swc1 $f24, (THREAD_FPU + 0x0c0)(\thread) + swc1 $f25, (THREAD_FPU + 0x0c8)(\thread) + swc1 $f26, (THREAD_FPU + 0x0d0)(\thread) + swc1 $f27, (THREAD_FPU + 0x0d8)(\thread) + swc1 $f28, (THREAD_FPU + 0x0e0)(\thread) + swc1 $f29, (THREAD_FPU + 0x0e8)(\thread) + swc1 $f30, (THREAD_FPU + 0x0f0)(\thread) + swc1 $f31, (THREAD_FPU + 0x0f8)(\thread) + sw \tmp, (THREAD_FPU + 0x100)(\thread) + .endm + + .macro fpu_restore_16even thread tmp + lw \tmp, (THREAD_FPU + 0x100)(\thread) + ldc1 $f2, (THREAD_FPU + 0x010)(\thread) + ldc1 $f4, (THREAD_FPU + 0x020)(\thread) + ldc1 $f6, (THREAD_FPU + 0x030)(\thread) + ldc1 $f8, (THREAD_FPU + 0x040)(\thread) + ldc1 $f10, (THREAD_FPU + 0x050)(\thread) + ldc1 $f12, (THREAD_FPU + 0x060)(\thread) + ldc1 $f14, (THREAD_FPU + 0x070)(\thread) + ldc1 $f16, (THREAD_FPU + 0x080)(\thread) + ldc1 $f18, (THREAD_FPU + 0x090)(\thread) + ldc1 $f20, (THREAD_FPU + 0x0a0)(\thread) + ldc1 $f22, (THREAD_FPU + 0x0b0)(\thread) + ldc1 $f24, (THREAD_FPU + 0x0c0)(\thread) + ldc1 $f26, (THREAD_FPU + 0x0d0)(\thread) + ldc1 $f28, (THREAD_FPU + 0x0e0)(\thread) + ldc1 $f30, (THREAD_FPU + 0x0f0)(\thread) + ctc1 \tmp, fcr31 + .endm + + .macro fpu_restore_16odd thread + ldc1 $f1, (THREAD_FPU + 0x08)(\thread) + ldc1 $f3, (THREAD_FPU + 0x18)(\thread) + ldc1 $f5, (THREAD_FPU + 0x28)(\thread) + ldc1 $f7, (THREAD_FPU + 0x38)(\thread) + ldc1 $f9, (THREAD_FPU + 0x48)(\thread) + ldc1 $f11, (THREAD_FPU + 0x58)(\thread) + ldc1 $f13, (THREAD_FPU + 0x68)(\thread) + ldc1 $f15, (THREAD_FPU + 0x78)(\thread) + ldc1 $f17, (THREAD_FPU + 0x88)(\thread) + ldc1 $f19, (THREAD_FPU + 0x98)(\thread) + ldc1 $f21, (THREAD_FPU + 0xa8)(\thread) + ldc1 $f23, (THREAD_FPU + 0xb8)(\thread) + ldc1 $f25, (THREAD_FPU + 0xc8)(\thread) + ldc1 $f27, (THREAD_FPU + 0xd8)(\thread) + ldc1 $f29, (THREAD_FPU + 0xe8)(\thread) + ldc1 $f31, (THREAD_FPU + 0xf8)(\thread) + .endm + + .macro fpu_restore thread tmp + lw \tmp, (THREAD_FPU + 0x100)(\thread) + lwc1 $f0, (THREAD_FPU + 0x000)(\thread) + lwc1 $f1, (THREAD_FPU + 0x008)(\thread) + lwc1 $f2, (THREAD_FPU + 0x010)(\thread) + lwc1 $f3, (THREAD_FPU + 0x018)(\thread) + lwc1 $f4, (THREAD_FPU + 0x020)(\thread) + lwc1 $f5, (THREAD_FPU + 0x028)(\thread) + lwc1 $f6, (THREAD_FPU + 0x030)(\thread) + lwc1 $f7, (THREAD_FPU + 0x038)(\thread) + lwc1 $f8, (THREAD_FPU + 0x040)(\thread) + lwc1 $f9, (THREAD_FPU + 0x048)(\thread) + lwc1 $f10, (THREAD_FPU + 0x050)(\thread) + lwc1 $f11, (THREAD_FPU + 0x058)(\thread) + lwc1 $f12, (THREAD_FPU + 0x060)(\thread) + lwc1 $f13, (THREAD_FPU + 0x068)(\thread) + lwc1 $f14, (THREAD_FPU + 0x070)(\thread) + lwc1 $f15, (THREAD_FPU + 0x078)(\thread) + lwc1 $f16, (THREAD_FPU + 0x080)(\thread) + lwc1 $f17, (THREAD_FPU + 0x088)(\thread) + lwc1 $f18, (THREAD_FPU + 0x090)(\thread) + lwc1 $f19, (THREAD_FPU + 0x098)(\thread) + lwc1 $f20, (THREAD_FPU + 0x0a0)(\thread) + lwc1 $f21, (THREAD_FPU + 0x0a8)(\thread) + lwc1 $f22, (THREAD_FPU + 0x0b0)(\thread) + lwc1 $f23, (THREAD_FPU + 0x0b8)(\thread) + lwc1 $f24, (THREAD_FPU + 0x0c0)(\thread) + lwc1 $f25, (THREAD_FPU + 0x0c8)(\thread) + lwc1 $f26, (THREAD_FPU + 0x0d0)(\thread) + lwc1 $f27, (THREAD_FPU + 0x0d8)(\thread) + lwc1 $f28, (THREAD_FPU + 0x0e0)(\thread) + lwc1 $f29, (THREAD_FPU + 0x0e8)(\thread) + lwc1 $f30, (THREAD_FPU + 0x0f0)(\thread) + lwc1 $f31, (THREAD_FPU + 0x0f8)(\thread) + ctc1 \tmp, fcr31 + .endm + + .macro cpu_save_nonscratch thread + sd s0, THREAD_REG16(\thread) + sd s1, THREAD_REG17(\thread) + sd s2, THREAD_REG18(\thread) + sd s3, THREAD_REG19(\thread) + sd s4, THREAD_REG20(\thread) + sd s5, THREAD_REG21(\thread) + sd s6, THREAD_REG22(\thread) + sd s7, THREAD_REG23(\thread) + sd sp, THREAD_REG29(\thread) + sd fp, THREAD_REG30(\thread) + .endm + + .macro cpu_restore_nonscratch thread + ld s0, THREAD_REG16(\thread) + ld s1, THREAD_REG17(\thread) + ld s2, THREAD_REG18(\thread) + ld s3, THREAD_REG19(\thread) + ld s4, THREAD_REG20(\thread) + ld s5, THREAD_REG21(\thread) + ld s6, THREAD_REG22(\thread) + ld s7, THREAD_REG23(\thread) + ld sp, THREAD_REG29(\thread) + ld fp, THREAD_REG30(\thread) + ld ra, THREAD_REG31(\thread) + .endm + +#endif /* !(_ASM_ASMMACRO_H) */ diff --git a/include/asm-mips64/bitops.h b/include/asm-mips64/bitops.h index e6e675a5c..380adf616 100644 --- a/include/asm-mips64/bitops.h +++ b/include/asm-mips64/bitops.h @@ -1,4 +1,4 @@ -/* $Id: bitops.h,v 1.2 1999/08/19 22:56:34 ralf Exp $ +/* $Id: bitops.h,v 1.3 1999/08/20 21:59:08 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,95 +13,13 @@ #include <linux/types.h> #include <linux/byteorder/swab.h> /* sigh ... */ -#ifdef __KERNEL__ +#ifndef __KERNEL__ +#error "Don't do this, sucker ..." +#endif + #include <asm/system.h> #include <asm/sgidefs.h> #include <asm/mipsregs.h> -#endif - -/* - * This gets exported to userland, so we need to have a MIPS I versions - * as well. Userland always get the non-thread / signal safe variants. - */ - -#ifndef __KERNEL__ - -extern __inline__ void -set_bit(unsigned long nr, void * addr) -{ - int mask; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a |= mask; -} - -extern __inline__ void -clear_bit(unsigned long nr, void * addr) -{ - int mask; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a &= ~mask; -} - -extern __inline__ void -change_bit(unsigned long nr, void * addr) -{ - int mask; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - *a ^= mask; -} - -extern __inline__ unsigned long -test_and_set_bit(unsigned long nr, void * addr) -{ - int mask, retval; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a |= mask; - - return retval; -} - -extern __inline__ unsigned long -test_and_clear_bit(unsigned long nr, void * addr) -{ - int mask, retval; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a &= ~mask; - - return retval; -} - -extern __inline__ unsigned long -test_and_change_bit(unsigned long nr, void * addr) -{ - int mask, retval; - int *a = addr; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - retval = (mask & *a) != 0; - *a ^= mask; - - return retval; -} - -#else /* __KERNEL__ */ /* * These functions for MIPS ISA > 1 are interrupt and SMP proof and @@ -111,73 +29,64 @@ test_and_change_bit(unsigned long nr, void * addr) extern __inline__ void set_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp; __asm__ __volatile__( - ".set\tnoreorder\t\t# set_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\t\t# set_bit\n\t" "or\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqzl\t%0,1b\n\t" - " ll\t%0, %1\n\t" - ".set\treorder" + "scd\t%0, %1\n\t" + "beqz\t%0, 1b" :"=&r" (temp), "=m" (*m) - :"ir" (1UL << (nr & 31)), "m" (*m)); + :"ir" (1UL << (nr & 0x3f)), "m" (*m)); } extern __inline__ void clear_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp; __asm__ __volatile__( - ".set\tnoreorder\t\t# clear_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\t\t# clear_bit\n\t" "and\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqzl\t%0,1b\n\t" - " ll\t%0, %1\n\t" - ".set\treorder" + "scd\t%0, %1\n\t" + "beqz\t%0, 1b\n\t" :"=&r" (temp), "=m" (*m) - :"ir" (~(1UL << (nr & 31))), "m" (*m)); + :"ir" (~(1UL << (nr & 0x3f))), "m" (*m)); } extern __inline__ void change_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp; __asm__ __volatile__( - ".set\tnoreorder\t\t# change_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\t\t# change_bit\n\t" "xor\t%0, %2\n\t" - "sc\t%0, %1\n\t" - "beqzl\t%0,1b\n\t" - " ll\t%0, %1\n\t" - ".set\treorder" + "scd\t%0, %1\n\t" + "beqz\t%0, 1b" :"=&r" (temp), "=m" (*m) - :"ir" (1UL << (nr & 31)), "m" (*m)); + :"ir" (1UL << (nr & 0x3f)), "m" (*m)); } extern __inline__ unsigned long test_and_set_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_set_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\n\t" "or\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2,1b\n\t" + "scd\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" ".set\treorder" :"=&r" (temp), "=m" (*m), "=&r" (res) - :"r" (1UL << (nr & 31)), "m" (*m)); + :"r" (1UL << (nr & 0x3f)), "m" (*m)); return res != 0; } @@ -185,20 +94,20 @@ test_and_set_bit(unsigned long nr, void *addr) extern __inline__ unsigned long test_and_clear_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_clear_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\n\t" "or\t%2, %0, %3\n\t" "xor\t%2, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2,1b\n\t" + "scd\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" ".set\treorder" :"=&r" (temp), "=m" (*m), "=&r" (res) - :"r" (1UL << (nr & 31)), "m" (*m)); + :"r" (1UL << (nr & 0x3f)), "m" (*m)); return res != 0; } @@ -206,29 +115,27 @@ test_and_clear_bit(unsigned long nr, void *addr) extern __inline__ unsigned long test_and_change_bit(unsigned long nr, void *addr) { - unsigned int *m = ((unsigned int *) addr) + (nr >> 5); + unsigned long *m = ((unsigned long *) addr) + (nr >> 6); unsigned long temp, res; __asm__ __volatile__( ".set\tnoreorder\t\t# test_and_change_bit\n" - "1:\tll\t%0, %1\n\t" + "1:\tlld\t%0, %1\n\t" "xor\t%2, %0, %3\n\t" - "sc\t%2, %1\n\t" - "beqz\t%2,1b\n\t" + "scd\t%2, %1\n\t" + "beqz\t%2, 1b\n\t" " and\t%2, %0, %3\n\t" ".set\treorder" :"=&r" (temp), "=m" (*m), "=&r" (res) - :"r" (1UL << (nr & 31)), "m" (*m)); + :"r" (1UL << (nr & 0x3f)), "m" (*m)); return res != 0; } -#endif /* __KERNEL__ */ - extern __inline__ unsigned long test_bit(int nr, volatile void * addr) { - return 1UL & (((const int *) addr)[nr >> 5] >> (nr & 31)); + return 1UL & (((const long *) addr)[nr >> 6] >> (nr & 0x3f)); } #ifndef __MIPSEB__ @@ -332,29 +239,20 @@ find_next_zero_bit (void * addr, int size, int offset) * ffz = Find First Zero in word. Undefined if no zero exists, * so code should check against ~0UL first.. */ -extern __inline__ unsigned long -ffz(unsigned long word) +extern __inline__ unsigned long ffz(unsigned long word) { - unsigned int __res; - unsigned int mask = 1; - - __asm__ ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - "move\t%0,$0\n" - "1:\tand\t$1,%2,%1\n\t" - "beqz\t$1,2f\n\t" - "sll\t%1,1\n\t" - "bnez\t%1,1b\n\t" - "addiu\t%0,1\n\t" - ".set\tat\n\t" - ".set\treorder\n" - "2:\n\t" - : "=&r" (__res), "=r" (mask) - : "r" (word), "1" (mask) - : "$1"); - - return __res; + unsigned long k; + + word = ~word; + k = 63; + if (word & 0x00000000ffffffffUL) { k -= 32; word <<= 32; } + if (word & 0x0000ffff00000000UL) { k -= 16; word <<= 16; } + if (word & 0x00ff000000000000UL) { k -= 8; word <<= 8; } + if (word & 0x0f00000000000000UL) { k -= 4; word <<= 4; } + if (word & 0x3000000000000000UL) { k -= 2; word <<= 2; } + if (word & 0x4000000000000000UL) { k -= 1; } + + return k; } #ifdef __KERNEL__ @@ -386,32 +284,32 @@ ffz(unsigned long word) * on Linus's ALPHA routines, which are pretty portable BTW. */ -extern __inline__ int -find_next_zero_bit(void *addr, int size, int offset) +extern __inline__ unsigned long +find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; + unsigned long *p = ((unsigned long *) addr) + (offset >> 6); + unsigned long result = offset & ~63UL; unsigned long tmp; if (offset >= size) return size; size -= result; - offset &= 31UL; + offset &= 63UL; if (offset) { tmp = *(p++); - tmp |= ~0UL >> (32-offset); - if (size < 32) + tmp |= ~0UL >> (64-offset); + if (size < 64) goto found_first; if (~tmp) goto found_middle; - size -= 32; - result += 32; + size -= 64; + result += 64; } - while (size & ~31UL) { + while (size & ~63UL) { if (~(tmp = *(p++))) goto found_middle; - result += 32; - size -= 32; + result += 64; + size -= 64; } if (!size) return result; @@ -428,6 +326,8 @@ found_middle: #endif /* (__MIPSEB__) */ +#ifdef __KERNEL__ + /* Now for the ext2 filesystem bit operations and helper routines. */ #ifdef __MIPSEB__ @@ -548,4 +448,6 @@ found_middle: #define minix_test_bit(nr,addr) test_bit(nr,addr) #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) +#endif /* __KERNEL__ */ + #endif /* _ASM_BITOPS_H */ diff --git a/include/asm-mips64/cpu.h b/include/asm-mips64/cpu.h new file mode 100644 index 000000000..9378e18ab --- /dev/null +++ b/include/asm-mips64/cpu.h @@ -0,0 +1,45 @@ +/* $Id: cpu.h,v 1.1 1999/10/19 20:51:53 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * cpu.h: Values of the PRId register used to match up + * various MIPS cpu types. + * + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + */ +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* + * Assigned values for the product ID register. In order to detect a + * certain CPU type exactly eventually additional registers may need to + * be examined. + */ +#define PRID_IMP_R2000 0x0100 +#define PRID_IMP_R3000 0x0200 +#define PRID_IMP_R6000 0x0300 +#define PRID_IMP_R4000 0x0400 +#define PRID_IMP_R6000A 0x0600 +#define PRID_IMP_R10000 0x0900 +#define PRID_IMP_R4300 0x0b00 +#define PRID_IMP_R8000 0x1000 +#define PRID_IMP_R4600 0x2000 +#define PRID_IMP_R4700 0x2100 +#define PRID_IMP_R4640 0x2200 +#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ +#define PRID_IMP_R5000 0x2300 +#define PRID_IMP_SONIC 0x2400 +#define PRID_IMP_MAGIC 0x2500 +#define PRID_IMP_RM7000 0x2700 +#define PRID_IMP_NEVADA 0x2800 + +#define PRID_IMP_UNKNOWN 0xff00 + +#define PRID_REV_R4400 0x0040 +#define PRID_REV_R3000A 0x0030 +#define PRID_REV_R3000 0x0020 +#define PRID_REV_R2000A 0x0010 + +#endif /* _ASM_CPU_H */ diff --git a/include/asm-mips64/current.h b/include/asm-mips64/current.h index 0293e6ad8..0afc8cad4 100644 --- a/include/asm-mips64/current.h +++ b/include/asm-mips64/current.h @@ -1,4 +1,4 @@ -/* $Id: current.h,v 1.1 1999/08/18 21:46:54 ralf Exp $ +/* $Id: current.h,v 1.2 1999/09/28 22:27:19 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -27,8 +27,8 @@ register struct task_struct *current asm("$28"); .set noreorder; \ lw reg, %lo(kernelsp)(reg); \ .set pop; \ - ori reg, 8191; \ - xori reg, 8191 + ori reg, 0x3fff; \ + xori reg, 0x3fff #endif diff --git a/include/asm-mips64/dma.h b/include/asm-mips64/dma.h index 169698ba5..00da1fb9f 100644 --- a/include/asm-mips64/dma.h +++ b/include/asm-mips64/dma.h @@ -15,7 +15,7 @@ #include <linux/config.h> #include <asm/io.h> /* need byte IO */ -#include <asm/spinlock.h> /* And spinlocks */ +#include <linux/spinlock.h> /* And spinlocks */ #include <linux/delay.h> #include <asm/system.h> diff --git a/include/asm-mips64/elf.h b/include/asm-mips64/elf.h index e9b755277..f6f8785d4 100644 --- a/include/asm-mips64/elf.h +++ b/include/asm-mips64/elf.h @@ -7,6 +7,7 @@ #ifndef _ASM_ELF_H #define _ASM_ELF_H +#ifndef ELF_ARCH /* ELF register definitions */ #define ELF_NGREG 45 #define ELF_NFPREG 33 @@ -32,6 +33,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_DATA ELFDATA2LSB #endif #define ELF_ARCH EM_MIPS +#endif /* !defined(ELF_ARCH) */ #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 @@ -75,7 +77,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; the loader. We need to make sure that it is out of the way of the program that it will "exec", and that there is sufficient room for the brk. */ +#ifndef ELF_ET_DYN_BASE #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) +#endif #ifdef __KERNEL__ #define SET_PERSONALITY(ex,ibcs2) \ diff --git a/include/asm-mips64/hardirq.h b/include/asm-mips64/hardirq.h index 3bcdae01a..ed8895b7e 100644 --- a/include/asm-mips64/hardirq.h +++ b/include/asm-mips64/hardirq.h @@ -10,7 +10,7 @@ #ifndef _ASM_HARDIRQ_H #define _ASM_HARDIRQ_H -#include <linux/tasks.h> +#include <linux/threads.h> extern unsigned int local_irq_count[NR_CPUS]; diff --git a/include/asm-mips64/inst.h b/include/asm-mips64/inst.h new file mode 100644 index 000000000..0a484592f --- /dev/null +++ b/include/asm-mips64/inst.h @@ -0,0 +1,305 @@ +/* $Id: inst.h,v 1.1 1999/10/09 20:55:09 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Format of an instruction in memory. + * + * Copyright (C) 1996 by Ralf Baechle + */ +#ifndef _ASM_INST_H +#define _ASM_INST_H + +/* + * Major opcodes; before MIPS IV cop1x was called cop3. + */ +enum major_op { + spec_op, bcond_op, j_op, jal_op, + beq_op, bne_op, blez_op, bgtz_op, + addi_op, addiu_op, slti_op, sltiu_op, + andi_op, ori_op, xori_op, lui_op, + cop0_op, cop1_op, cop2_op, cop1x_op, + beql_op, bnel_op, blezl_op, bgtzl_op, + daddi_op, daddiu_op, ldl_op, ldr_op, + major_1c_op, major_1d_op, major_1e_op, major_1f_op, + lb_op, lh_op, lwl_op, lw_op, + lbu_op, lhu_op, lwr_op, lwu_op, + sb_op, sh_op, swl_op, sw_op, + sdl_op, sdr_op, swr_op, cache_op, + ll_op, lwc1_op, lwc2_op, pref_op, + lld_op, ldc1_op, ldc2_op, ld_op, + sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */ + scd_op, sdc1_op, sdc2_op, sd_op +}; + +/* + * func field of spec opcode. + */ +enum spec_op { + sll_op, movc_op, srl_op, sra_op, + sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ + jr_op, jalr_op, movz_op, movn_op, + syscall_op, break_op, spim_op, sync_op, + mfhi_op, mthi_op, mflo_op, mtlo_op, + dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, + mult_op, multu_op, div_op, divu_op, + dmult_op, dmultu_op, ddiv_op, ddivu_op, + add_op, addu_op, sub_op, subu_op, + and_op, or_op, xor_op, nor_op, + spec3_unused_op, spec4_unused_op, slt_op, sltu_op, + dadd_op, daddu_op, dsub_op, dsubu_op, + tge_op, tgeu_op, tlt_op, tltu_op, + teq_op, spec5_unused_op, tne_op, spec6_unused_op, + dsll_op, spec7_unused_op, dsrl_op, dsra_op, + dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op +}; + +/* + * rt field of bcond opcodes. + */ +enum rt_op { + bltz_op, bgez_op, bltzl_op, bgezl_op, + spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, + tgei_op, tgeiu_op, tlti_op, tltiu_op, + teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, + bltzal_op, bgezal_op, bltzall_op, bgezall_op + /* + * The others (0x14 - 0x1f) are unused. + */ +}; + +/* + * rs field of cop opcodes. + */ +enum cop_op { + mfc_op = 0x00, dmfc_op = 0x01, + cfc_op = 0x02, mtc_op = 0x04, + dmtc_op = 0x05, ctc_op = 0x06, + bc_op = 0x08, cop_op = 0x10, + copm_op = 0x18 +}; + +/* + * func field of cop0 coi opcodes. + */ +enum cop0_coi_func { + tlbr_op = 0x01, tlbwi_op = 0x02, + tlbwr_op = 0x06, tlbp_op = 0x08, + rfe_op = 0x10, eret_op = 0x18 +}; + +/* + * func field of cop0 com opcodes. + */ +enum cop0_com_func { + tlbr1_op = 0x01, tlbw_op = 0x02, + tlbp1_op = 0x08, dctr_op = 0x09, + dctw_op = 0x0a +}; + +/* + * fmt field of cop1 opcodes. + */ +enum cop1_fmt { + s_fmt, d_fmt, e_fmt, q_fmt, + w_fmt, l_fmt +}; + +/* + * func field of cop1 instructions using d, s or w format. + */ +enum cop1_sdw_func { + fadd_op = 0x00, fsub_op = 0x01, + fmul_op = 0x02, fdiv_op = 0x03, + fsqrt_op = 0x04, fabs_op = 0x05, + fmov_op = 0x06, fneg_op = 0x07, + froundl_op = 0x08, ftruncl_op = 0x09, + fceill_op = 0x0a, ffloorl_op = 0x0b, + fround_op = 0x0c, ftrunc_op = 0x0d, + fceil_op = 0x0e, ffloor_op = 0x0f, + fmovc_op = 0x11, fmovz_op = 0x12, + fmovn_op = 0x13, frecip_op = 0x15, + frsqrt_op = 0x16, fcvts_op = 0x20, + fcvtd_op = 0x21, fcvte_op = 0x22, + fcvtw_op = 0x24, fcvtl_op = 0x25, + fcmp_op = 0x30 +}; + +/* + * func field of cop1x opcodes (MIPS IV). + */ +enum cop1x_func { + lwxc1_op = 0x00, ldxc1_op = 0x01, + pfetch_op = 0x07, swxc1_op = 0x08, + sdxc1_op = 0x09, madd_s_op = 0x20, + madd_d_op = 0x21, madd_e_op = 0x22, + msub_s_op = 0x28, msub_d_op = 0x29, + msub_e_op = 0x2a, nmadd_s_op = 0x30, + nmadd_d_op = 0x31, nmadd_e_op = 0x32, + nmsub_s_op = 0x38, nmsub_d_op = 0x39, + nmsub_e_op = 0x3a +}; + +/* + * func field for mad opcodes (MIPS IV). + */ +enum mad_func { + madd_op = 0x08, msub_op = 0x0a, + nmadd_op = 0x0c, nmsub_op = 0x0e +}; + +/* + * Damn ... bitfields depend from byteorder :-( + */ +#ifdef __MIPSEB__ +struct j_format { /* Jump format */ + unsigned int opcode : 6; + unsigned int target : 26; +}; + +struct i_format { /* Immediate format (addi, lw, ...) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + signed int simmediate : 16; +}; + +struct u_format { /* Unsigned immediate format (ori, xori, ...) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int uimmediate : 16; +}; + +struct c_format { /* Cache (>= R6000) format */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int c_op : 3; + unsigned int cache : 2; + unsigned int simmediate : 16; +}; + +struct r_format { /* Register format */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct p_format { /* Performance counter format (R10000) */ + unsigned int opcode : 6; + unsigned int rs : 5; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct f_format { /* FPU register format */ + unsigned int opcode : 6; + unsigned int : 1; + unsigned int fmt : 4; + unsigned int rt : 5; + unsigned int rd : 5; + unsigned int re : 5; + unsigned int func : 6; +}; + +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int opcode : 6; + unsigned int fr : 5; + unsigned int ft : 5; + unsigned int fs : 5; + unsigned int fd : 5; + unsigned int func : 4; + unsigned int fmt : 2; +}; + +#elif defined(__MIPSEL__) + +struct j_format { /* Jump format */ + unsigned int target : 26; + unsigned int opcode : 6; +}; + +struct i_format { /* Immediate format */ + signed int simmediate : 16; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct u_format { /* Unsigned immediate format */ + unsigned int uimmediate : 16; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct c_format { /* Cache (>= R6000) format */ + unsigned int simmediate : 16; + unsigned int cache : 2; + unsigned int c_op : 3; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct r_format { /* Register format */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct p_format { /* Performance counter format (R10000) */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int rs : 5; + unsigned int opcode : 6; +}; + +struct f_format { /* FPU register format */ + unsigned int func : 6; + unsigned int re : 5; + unsigned int rd : 5; + unsigned int rt : 5; + unsigned int fmt : 4; + unsigned int : 1; + unsigned int opcode : 6; +}; + +struct ma_format { /* FPU multipy and add format (MIPS IV) */ + unsigned int fmt : 2; + unsigned int func : 4; + unsigned int fd : 5; + unsigned int fs : 5; + unsigned int ft : 5; + unsigned int fr : 5; + unsigned int opcode : 6; +}; + +#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ +#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" +#endif + +union mips_instruction { + unsigned int word; + unsigned short halfword[2]; + unsigned char byte[4]; + struct j_format j_format; + struct i_format i_format; + struct u_format u_format; + struct c_format c_format; + struct r_format r_format; + struct f_format f_format; + struct ma_format ma_format; +}; + +#endif /* _ASM_INST_H */ diff --git a/include/asm-mips64/ipc.h b/include/asm-mips64/ipc.h new file mode 100644 index 000000000..b3888d353 --- /dev/null +++ b/include/asm-mips64/ipc.h @@ -0,0 +1,32 @@ +#ifndef _ASM_IPC_H +#define _ASM_IPC_H + +/* + * These are used to wrap system calls on MIPS32. + * + * See arch/mips/kernel/sysmips.c for ugly details.. + * FIXME: split up into ordinary syscalls ... + */ +struct ipc_kludge { + struct msgbuf *msgp; + long msgtyp; +}; + +#define SEMOP 1 +#define SEMGET 2 +#define SEMCTL 3 +#define MSGSND 11 +#define MSGRCV 12 +#define MSGGET 13 +#define MSGCTL 14 +#define SHMAT 21 +#define SHMDT 22 +#define SHMGET 23 +#define SHMCTL 24 + +/* Used by the DIPC package, try and avoid reusing it */ +#define DIPC 25 + +#define IPCCALL(version,op) ((version)<<16 | (op)) + +#endif /* _ASM_IPC_H */ diff --git a/include/asm-mips64/mmu_context.h b/include/asm-mips64/mmu_context.h index 70f3bab5d..03df39e4b 100644 --- a/include/asm-mips64/mmu_context.h +++ b/include/asm-mips64/mmu_context.h @@ -1,64 +1,88 @@ -/* $Id$ +/* $Id: mmu_context.h,v 1.3 1999/11/19 20:35:49 ralf Exp $ + * + * Switch a MMU context. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996 - 1999 by Ralf Baechle + * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_MMU_CONTEXT_H #define _ASM_MMU_CONTEXT_H -#define MAX_ASID 255 +#include <linux/config.h> +/* Fuck. The f-word is here so you can grep for it :-) */ extern unsigned long asid_cache; +extern pgd_t *current_pgd; -#define ASID_VERSION_SHIFT 16 -#define ASID_VERSION_MASK ((~0UL) << ASID_VERSION_SHIFT) -#define ASID_FIRST_VERSION (1UL << ASID_VERSION_SHIFT) +#define ASID_INC 0x1 +#define ASID_MASK 0xff -extern inline void get_new_mmu_context(struct mm_struct *mm, unsigned long asid) -{ - /* check if it's legal.. */ - if ((asid & ~ASID_VERSION_MASK) > MAX_ASID) { - /* start a new version, invalidate all old asid's */ - flush_tlb_all(); - asid = (asid & ASID_VERSION_MASK) + ASID_FIRST_VERSION; - if (!asid) - asid = ASID_FIRST_VERSION; - } - asid_cache = asid + 1; - mm->context = asid; /* full version + asid */ -} +/* + * All unused by hardware upper bits will be considered + * as a software asid extension. + */ +#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) +#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) -extern inline void get_mmu_context(struct task_struct *p) +extern inline void +get_new_mmu_context(struct mm_struct *mm, unsigned long asid) { - struct mm_struct *mm = p->mm; - - if (mm) { - unsigned long asid = asid_cache; - /* Check if our ASID is of an older version and thus invalid */ - if ((mm->context ^ asid) & ASID_VERSION_MASK) - get_new_mmu_context(mm, asid); + if (! ((asid += ASID_INC) & ASID_MASK) ) { + flush_tlb_all(); /* start new asid cycle */ + if (!asid) /* fix version if needed */ + asid = ASID_FIRST_VERSION; } + mm->context = asid_cache = asid; } /* * Initialize the context related info for a new mm_struct * instance. */ -extern inline void init_new_context(struct mm_struct *mm) +extern inline void +init_new_context(struct task_struct *tsk, struct mm_struct *mm) { mm->context = 0; } +extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, + struct task_struct *tsk, unsigned cpu) +{ + unsigned long asid = asid_cache; + + /* Check if our ASID is of an older version and thus invalid */ + if ((next->context ^ asid) & ASID_VERSION_MASK) + get_new_mmu_context(next, asid); + + current_pgd = next->pgd; + set_entryhi(next->context); +} + /* * Destroy context related info for an mm_struct that is about * to be put to rest. */ extern inline void destroy_context(struct mm_struct *mm) { - mm->context = 0; + /* Nothing to do. */ +} + +/* + * After we have set current->mm to a new value, this activates + * the context for the new mm so we see the new mappings. + */ +extern inline void +activate_mm(struct mm_struct *prev, struct mm_struct *next) +{ + /* Unconditionally get a new ASID. */ + get_new_mmu_context(next, asid_cache); + + current_pgd = next->pgd; + set_entryhi(next->context); } #endif /* _ASM_MMU_CONTEXT_H */ diff --git a/include/asm-mips64/offset.h b/include/asm-mips64/offset.h index e37b353aa..f2451394c 100644 --- a/include/asm-mips64/offset.h +++ b/include/asm-mips64/offset.h @@ -4,45 +4,45 @@ #define _MIPS_OFFSET_H /* MIPS pt_regs offsets. */ -#define PT_R0 64 -#define PT_R1 72 -#define PT_R2 80 -#define PT_R3 88 -#define PT_R4 96 -#define PT_R5 104 -#define PT_R6 112 -#define PT_R7 120 -#define PT_R8 128 -#define PT_R9 136 -#define PT_R10 144 -#define PT_R11 152 -#define PT_R12 160 -#define PT_R13 168 -#define PT_R14 176 -#define PT_R15 184 -#define PT_R16 192 -#define PT_R17 200 -#define PT_R18 208 -#define PT_R19 216 -#define PT_R20 224 -#define PT_R21 232 -#define PT_R22 240 -#define PT_R23 248 -#define PT_R24 256 -#define PT_R25 264 -#define PT_R26 272 -#define PT_R27 280 -#define PT_R28 288 -#define PT_R29 296 -#define PT_R30 304 -#define PT_R31 312 -#define PT_LO 320 -#define PT_HI 328 -#define PT_EPC 336 -#define PT_BVADDR 344 -#define PT_STATUS 352 -#define PT_CAUSE 360 -#define PT_SIZE 368 +#define PT_R0 0 +#define PT_R1 8 +#define PT_R2 16 +#define PT_R3 24 +#define PT_R4 32 +#define PT_R5 40 +#define PT_R6 48 +#define PT_R7 56 +#define PT_R8 64 +#define PT_R9 72 +#define PT_R10 80 +#define PT_R11 88 +#define PT_R12 96 +#define PT_R13 104 +#define PT_R14 112 +#define PT_R15 120 +#define PT_R16 128 +#define PT_R17 136 +#define PT_R18 144 +#define PT_R19 152 +#define PT_R20 160 +#define PT_R21 168 +#define PT_R22 176 +#define PT_R23 184 +#define PT_R24 192 +#define PT_R25 200 +#define PT_R26 208 +#define PT_R27 216 +#define PT_R28 224 +#define PT_R29 232 +#define PT_R30 240 +#define PT_R31 248 +#define PT_LO 256 +#define PT_HI 264 +#define PT_EPC 272 +#define PT_BVADDR 280 +#define PT_STATUS 288 +#define PT_CAUSE 296 +#define PT_SIZE 304 /* MIPS task_struct offsets. */ #define TASK_STATE 0 @@ -51,37 +51,36 @@ #define TASK_NEED_RESCHED 40 #define TASK_COUNTER 48 #define TASK_PRIORITY 56 -#define TASK_MM 1400 -#define TASK_STRUCT_SIZE 1480 +#define TASK_MM 1304 +#define TASK_STRUCT_SIZE 1392 /* MIPS specific thread_struct offsets. */ -#define THREAD_REG16 1080 -#define THREAD_REG17 1088 -#define THREAD_REG18 1096 -#define THREAD_REG19 1104 -#define THREAD_REG20 1112 -#define THREAD_REG21 1120 -#define THREAD_REG22 1128 -#define THREAD_REG23 1136 -#define THREAD_REG29 1144 -#define THREAD_REG30 1152 -#define THREAD_REG31 1160 -#define THREAD_STATUS 1168 -#define THREAD_FPU 1176 -#define THREAD_BVADDR 1312 -#define THREAD_BUADDR 1320 -#define THREAD_ECODE 1328 -#define THREAD_TRAPNO 1336 -#define THREAD_PGDIR 1344 -#define THREAD_MFLAGS 1352 -#define THREAD_CURDS 1360 -#define THREAD_TRAMP 1368 -#define THREAD_OLDCTX 1376 +#define THREAD_REG16 864 +#define THREAD_REG17 872 +#define THREAD_REG18 880 +#define THREAD_REG19 888 +#define THREAD_REG20 896 +#define THREAD_REG21 904 +#define THREAD_REG22 912 +#define THREAD_REG23 920 +#define THREAD_REG29 928 +#define THREAD_REG30 936 +#define THREAD_REG31 944 +#define THREAD_STATUS 952 +#define THREAD_FPU 960 +#define THREAD_BVADDR 1224 +#define THREAD_BUADDR 1232 +#define THREAD_ECODE 1240 +#define THREAD_TRAPNO 1248 +#define THREAD_MFLAGS 1256 +#define THREAD_CURDS 1264 +#define THREAD_TRAMP 1272 +#define THREAD_OLDCTX 1280 /* Linux mm_struct offsets. */ -#define MM_COUNT 32 +#define MM_USERS 32 #define MM_PGD 24 -#define MM_CONTEXT 88 +#define MM_CONTEXT 96 /* Linux sigcontext offsets. */ #define SC_REGS 0 diff --git a/include/asm-mips64/page.h b/include/asm-mips64/page.h index 5a97a951f..4471bb273 100644 --- a/include/asm-mips64/page.h +++ b/include/asm-mips64/page.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: page.h,v 1.1 1999/08/18 23:37:51 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -6,8 +6,6 @@ * * Copyright (C) 1994 - 1999 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. - * - * XXX This is all complete bullshit on MIPS64. */ #ifndef _ASM_PAGE_H #define _ASM_PAGE_H @@ -78,7 +76,7 @@ typedef unsigned long pgprot_t; * This handles the memory map. * We handle pages at KSEG0 for kernels with 32 bit address space. */ -#define PAGE_OFFSET 0x80000000UL +#define PAGE_OFFSET 0xffffffff80000000UL #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) #define MAP_NR(addr) (__pa(addr) >> PAGE_SHIFT) diff --git a/include/asm-mips64/pci.h b/include/asm-mips64/pci.h new file mode 100644 index 000000000..89eca5bf3 --- /dev/null +++ b/include/asm-mips64/pci.h @@ -0,0 +1,16 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef _ASM_PCI_H +#define _ASM_PCI_H + +/* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + +#define pcibios_assign_all_busses() 0 + +#endif /* _ASM_PCI_H */ diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h index fd1e5c063..02ca0e208 100644 --- a/include/asm-mips64/pgtable.h +++ b/include/asm-mips64/pgtable.h @@ -58,26 +58,25 @@ extern void (*flush_tlb_page)(struct vm_area_struct *vma, unsigned long page); #endif /* !defined (_LANGUAGE_ASSEMBLY) */ /* PMD_SHIFT determines the size of the area a second-level page table can map */ -#define PMD_SHIFT 22 +#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#define PGDIR_SHIFT 22 +#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3)) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) -/* Entries per page directory level: we use two-level, so - * we don't really have any PMD directory physically. - */ -#define PTRS_PER_PTE 1024 -#define PTRS_PER_PMD 1 +/* Entries per page directory level: we use two-level, so we don't really + have any PMD directory physically. */ #define PTRS_PER_PGD 1024 +#define PTRS_PER_PMD 1024 +#define PTRS_PER_PTE 512 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define VMALLOC_START KSEG2 +#define VMALLOC_START XKSEG #define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define VMALLOC_END KSEG3 +#define VMALLOC_END (KSEG3 + (1UL << 40)) /* 1 TB */ /* Note that we shift the lower 32bits of each EntryLo[01] entry * 6 bits to the left. That way we can convert the PFN into the @@ -173,11 +172,13 @@ extern void (*flush_tlb_page)(struct vm_area_struct *vma, unsigned long page); */ extern pte_t __bad_page(void); extern pte_t *__bad_pagetable(void); +extern pmd_t *__bad_pmd_table(void); extern unsigned long empty_zero_page; extern unsigned long zero_page_mask; #define BAD_PAGETABLE __bad_pagetable() +#define BAD_PMDTABLE __bad_pmd_table() #define BAD_PAGE __bad_page() #define ZERO_PAGE(__vaddr) \ (empty_zero_page + (((unsigned long)(__vaddr)) & zero_page_mask)) @@ -191,7 +192,7 @@ extern unsigned long zero_page_mask; /* * sizeof(void*) == (1 << SIZEOF_PTR_LOG2) */ -#define SIZEOF_PTR_LOG2 2 +#define SIZEOF_PTR_LOG2 3 /* to find an entry in a page-table */ #define PAGE_PTR(address) \ @@ -199,7 +200,8 @@ extern unsigned long zero_page_mask; extern void (*load_pgd)(unsigned long pg_dir); -extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)]; +extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; +extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)]; /* * Conversion functions: convert a page and protection to a page entry, @@ -215,13 +217,30 @@ extern inline unsigned long pmd_page(pmd_t pmd) return pmd_val(pmd); } +extern inline unsigned long pgd_page(pgd_t pgd) +{ + return pgd_val(pgd); +} + extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep) { pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK); } -extern inline int pte_none(pte_t pte) { return !pte_val(pte); } -extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; } +extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp) +{ + pgd_val(*pgdp) = (((unsigned long) pmdp) & PAGE_MASK); +} + +extern inline int pte_none(pte_t pte) +{ + return !pte_val(pte); +} + +extern inline int pte_present(pte_t pte) +{ + return pte_val(pte) & _PAGE_PRESENT; +} /* Certain architectures need to do special things when pte's * within a page table are directly modified. Thus, the following @@ -238,7 +257,7 @@ extern inline void pte_clear(pte_t *ptep) } /* - * Empty pgd/pmd entries point to the invalid_pte_table. + * Empty pmd entries point to the invalid_pte_table. */ extern inline int pmd_none(pmd_t pmd) { @@ -253,7 +272,7 @@ extern inline int pmd_bad(pmd_t pmd) extern inline int pmd_present(pmd_t pmd) { - return pmd_val(pmd); + return pmd_val(pmd) != (unsigned long) invalid_pte_table; } extern inline void pmd_clear(pmd_t *pmdp) @@ -262,23 +281,52 @@ extern inline void pmd_clear(pmd_t *pmdp) } /* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) + * Empty pgd entries point to the invalid_pmd_table. */ -extern inline int pgd_none(pgd_t pgd) { return 0; } -extern inline int pgd_bad(pgd_t pgd) { return 0; } -extern inline int pgd_present(pgd_t pgd) { return 1; } -extern inline void pgd_clear(pgd_t *pgdp) { } +extern inline int pgd_none(pgd_t pgd) +{ + return pgd_val(pgd) == (unsigned long) invalid_pmd_table; +} + +extern inline int pgd_bad(pgd_t pgd) +{ + return ((pgd_page(pgd) > (unsigned long) high_memory) || + (pgd_page(pgd) < PAGE_OFFSET)); +} + +extern inline int pgd_present(pgd_t pgd) +{ + return pgd_val(pgd) != (unsigned long) invalid_pmd_table; +} + +extern inline void pgd_clear(pgd_t *pgdp) +{ + pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); +} /* * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } -extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } +extern inline int pte_read(pte_t pte) +{ + return pte_val(pte) & _PAGE_READ; +} + +extern inline int pte_write(pte_t pte) +{ + return pte_val(pte) & _PAGE_WRITE; +} + +extern inline int pte_dirty(pte_t pte) +{ + return pte_val(pte) & _PAGE_MODIFIED; +} + +extern inline int pte_young(pte_t pte) +{ + return pte_val(pte) & _PAGE_ACCESSED; +} extern inline pte_t pte_wrprotect(pte_t pte) { @@ -361,13 +409,14 @@ extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot) /* to find an entry in a page-table-directory */ extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address) { - return mm->pgd + (address >> PGDIR_SHIFT); + return mm->pgd + ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)); } /* Find an entry in the second-level page table.. */ -extern inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) +extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) { - return (pmd_t *) dir; + return (pmd_t *) pgd_page(*dir) + + ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)); } /* Find an entry in the third-level page table.. */ @@ -378,9 +427,11 @@ extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address) } /* - * Initialize new page directory with pointers to invalid ptes + * Initialize a new pgd / pmd table with invalid pointers. */ -extern void (*pgd_init)(unsigned long page); +extern void pte_init(unsigned long page); +extern void pgd_init(unsigned long page); +extern void pmd_init(unsigned long page); /* * Allocate and free page tables. The xxx_kernel() versions are @@ -389,24 +440,13 @@ extern void (*pgd_init)(unsigned long page); */ #define pgd_quicklist (current_cpu_data.pgd_quick) -#define pmd_quicklist ((unsigned long *)0) +#define pmd_quicklist (current_cpu_data.pmd_quick) #define pte_quicklist (current_cpu_data.pte_quick) #define pgtable_cache_size (current_cpu_data.pgtable_cache_sz) -extern __inline__ pgd_t *get_pgd_slow(void) -{ - pgd_t *ret = (pgd_t *)__get_free_page(GFP_KERNEL), *init; - - if (ret) { - init = pgd_offset(&init_mm, 0); - pgd_init((unsigned long)ret); - memcpy (ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, - (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); - } - return ret; -} +extern pgd_t *get_pgd_slow(void); -extern __inline__ pgd_t *get_pgd_fast(void) +extern inline pgd_t *get_pgd_fast(void) { unsigned long *ret; @@ -414,27 +454,29 @@ extern __inline__ pgd_t *get_pgd_fast(void) pgd_quicklist = (unsigned long *)(*ret); ret[0] = ret[1]; pgtable_cache_size--; - } else - ret = (unsigned long *)get_pgd_slow(); + return (pgd_t *)ret; + } + + ret = (unsigned long *) get_pgd_slow(); return (pgd_t *)ret; } -extern __inline__ void free_pgd_fast(pgd_t *pgd) +extern inline void free_pgd_fast(pgd_t *pgd) { *(unsigned long *)pgd = (unsigned long) pgd_quicklist; pgd_quicklist = (unsigned long *) pgd; pgtable_cache_size++; } -extern __inline__ void free_pgd_slow(pgd_t *pgd) +extern inline void free_pgd_slow(pgd_t *pgd) { - free_page((unsigned long)pgd); + free_pages((unsigned long)pgd, 1); } extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted); extern pte_t *get_pte_kernel_slow(pmd_t *pmd, unsigned long address_preadjusted); -extern __inline__ pte_t *get_pte_fast(void) +extern inline pte_t *get_pte_fast(void) { unsigned long *ret; @@ -446,37 +488,55 @@ extern __inline__ pte_t *get_pte_fast(void) return (pte_t *)ret; } -extern __inline__ void free_pte_fast(pte_t *pte) +extern inline void free_pte_fast(pte_t *pte) { *(unsigned long *)pte = (unsigned long) pte_quicklist; pte_quicklist = (unsigned long *) pte; pgtable_cache_size++; } -extern __inline__ void free_pte_slow(pte_t *pte) +extern inline void free_pte_slow(pte_t *pte) { - free_page((unsigned long)pte); + free_pages((unsigned long)pte, 0); } -/* We don't use pmd cache, so these are dummy routines */ -extern __inline__ pmd_t *get_pmd_fast(void) +extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long address_preadjusted); +extern pmd_t *get_pmd_kernel_slow(pgd_t *pgd, unsigned long address_preadjusted); + +extern inline pmd_t *get_pmd_fast(void) { - return (pmd_t *)0; + unsigned long *ret; + + if ((ret = (unsigned long *)pte_quicklist) != NULL) { + pte_quicklist = (unsigned long *)(*ret); + ret[0] = ret[1]; + pgtable_cache_size--; + return (pmd_t *)ret; + } + + return (pmd_t *)ret; } -extern __inline__ void free_pmd_fast(pmd_t *pmd) +extern inline void free_pmd_fast(pmd_t *pmd) { + *(unsigned long *)pmd = (unsigned long) pte_quicklist; + pte_quicklist = (unsigned long *) pmd; + pgtable_cache_size++; } -extern __inline__ void free_pmd_slow(pmd_t *pmd) +extern inline void free_pmd_slow(pmd_t *pmd) { + free_pages((unsigned long)pmd, 1); } extern void __bad_pte(pmd_t *pmd); extern void __bad_pte_kernel(pmd_t *pmd); +extern void __bad_pmd(pgd_t *pgd); #define pte_free_kernel(pte) free_pte_fast(pte) #define pte_free(pte) free_pte_fast(pte) +#define pmd_free_kernel(pte) free_pmd_fast(pte) +#define pmd_free(pte) free_pmd_fast(pte) #define pgd_free(pgd) free_pgd_fast(pgd) #define pgd_alloc() get_pgd_fast() @@ -487,7 +547,7 @@ extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address) if (pmd_none(*pmd)) { pte_t *page = get_pte_fast(); if (page) { - pmd_val(*pmd) = (unsigned long)page; + pmd_val(*pmd) = (unsigned long) page; return page + address; } return get_pte_kernel_slow(pmd, address); @@ -506,7 +566,7 @@ extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address) if (pmd_none(*pmd)) { pte_t *page = get_pte_fast(); if (page) { - pmd_val(*pmd) = (unsigned long)page; + pmd_val(*pmd) = (unsigned long) page; return page + address; } return get_pte_slow(pmd, address); @@ -518,20 +578,24 @@ extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address) return (pte_t *) pmd_page(*pmd) + address; } -/* - * allocating and freeing a pmd is trivial: the 1-entry pmd is - * inside the pgd, so has no extra memory associated with it. - */ -extern inline void pmd_free(pmd_t * pmd) +extern inline pmd_t *pmd_alloc(pgd_t * pgd, unsigned long address) { -} + address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); + if (pgd_none(*pgd)) { + pmd_t *page = get_pmd_fast(); -extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address) -{ - return (pmd_t *) pgd; + if (!page) + return get_pmd_slow(pgd, address); + pgd_set(pgd, page); + return page + address; + } + if (pgd_bad(*pgd)) { + __bad_pmd(pgd); + return NULL; + } + return (pmd_t *) pgd_page(*pgd) + address; } -#define pmd_free_kernel pmd_free #define pmd_alloc_kernel pmd_alloc extern int do_check_pgt_cache(int, int); @@ -548,7 +612,7 @@ extern inline void set_pgdir(unsigned long address, pgd_t entry) for_each_task(p) { if (!p->mm) continue; - *pgd_offset(p->mm,address) = entry; + *pgd_offset(p->mm, address) = entry; } read_unlock(&tasklist_lock); #ifndef __SMP__ @@ -569,11 +633,18 @@ extern void (*update_mmu_cache)(struct vm_area_struct *vma, unsigned long address, pte_t pte); /* - * Kernel with 32 bit address space + * Non-present pages: high 24 bits are offset, next 8 bits type, + * low 32 bits zero. */ -#define SWP_TYPE(entry) (((entry) >> 1) & 0x3f) -#define SWP_OFFSET(entry) ((entry) >> 8) -#define SWP_ENTRY(type,offset) (((type) << 1) | ((offset) << 8)) +extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) +{ + pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); + return pte; +} + +#define SWP_TYPE(entry) (((entry) >> 32) & 0xff) +#define SWP_OFFSET(entry) ((entry) >> 40) +#define SWP_ENTRY(type,offset) pte_val(mk_swap_pte((type),(offset))) #define module_map vmalloc #define module_unmap vfree @@ -624,9 +695,7 @@ extern inline unsigned long get_pagemask(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $5\n\t" - ".set mips0\n\t" ".set reorder" : "=r" (val)); return val; @@ -636,9 +705,7 @@ extern inline void set_pagemask(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $5\n\t" - ".set mips0\n\t" ".set reorder" : : "r" (val)); } @@ -650,9 +717,7 @@ extern inline unsigned long get_entrylo0(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mfc0 %0, $2\n\t" - ".set mips0\n\t" + "dmfc0 %0, $2\n\t" ".set reorder" : "=r" (val)); return val; @@ -662,9 +727,7 @@ extern inline void set_entrylo0(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mtc0 %0, $2\n\t" - ".set mips0\n\t" + "dmtc0 %0, $2\n\t" ".set reorder" : : "r" (val)); } @@ -675,9 +738,7 @@ extern inline unsigned long get_entrylo1(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mfc0 %0, $3\n\t" - ".set mips0\n\t" + "dmfc0 %0, $3\n\t" ".set reorder" : "=r" (val)); return val; @@ -687,9 +748,7 @@ extern inline void set_entrylo1(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mtc0 %0, $3\n\t" - ".set mips0\n\t" + "dmtc0 %0, $3\n\t" ".set reorder" : : "r" (val)); } @@ -701,9 +760,7 @@ extern inline unsigned long get_entryhi(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mfc0 %0, $10\n\t" - ".set mips0\n\t" + "dmfc0 %0, $10\n\t" ".set reorder" : "=r" (val)); @@ -714,9 +771,7 @@ extern inline void set_entryhi(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" - "mtc0 %0, $10\n\t" - ".set mips0\n\t" + "dmtc0 %0, $10\n\t" ".set reorder" : : "r" (val)); } @@ -728,9 +783,7 @@ extern inline unsigned long get_index(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $0\n\t" - ".set mips0\n\t" ".set reorder" : "=r" (val)); return val; @@ -740,9 +793,7 @@ extern inline void set_index(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $0\n\t" - ".set mips0\n\t" ".set reorder\n\t" : : "r" (val)); } @@ -754,9 +805,7 @@ extern inline unsigned long get_wired(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $6\n\t" - ".set mips0\n\t" ".set reorder\n\t" : "=r" (val)); return val; @@ -766,9 +815,7 @@ extern inline void set_wired(unsigned long val) { __asm__ __volatile__( "\n\t.set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $6\n\t" - ".set mips0\n\t" ".set reorder" : : "r" (val)); } @@ -780,9 +827,7 @@ extern inline unsigned long get_taglo(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $28\n\t" - ".set mips0\n\t" ".set reorder" : "=r" (val)); return val; @@ -792,9 +837,7 @@ extern inline void set_taglo(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $28\n\t" - ".set mips0\n\t" ".set reorder" : : "r" (val)); } @@ -805,9 +848,7 @@ extern inline unsigned long get_taghi(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $29\n\t" - ".set mips0\n\t" ".set reorder" : "=r" (val)); return val; @@ -817,9 +858,7 @@ extern inline void set_taghi(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $29\n\t" - ".set mips0\n\t" ".set reorder" : : "r" (val)); } @@ -831,9 +870,7 @@ extern inline unsigned long get_context(void) __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mfc0 %0, $4\n\t" - ".set mips0\n\t" ".set reorder" : "=r" (val)); @@ -844,9 +881,7 @@ extern inline void set_context(unsigned long val) { __asm__ __volatile__( ".set noreorder\n\t" - ".set mips3\n\t" "mtc0 %0, $4\n\t" - ".set mips0\n\t" ".set reorder" : : "r" (val)); } diff --git a/include/asm-mips64/posix_types.h b/include/asm-mips64/posix_types.h index b00f393b1..45d9961b5 100644 --- a/include/asm-mips64/posix_types.h +++ b/include/asm-mips64/posix_types.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: posix_types.h,v 1.1 1999/08/18 23:37:51 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -20,21 +20,21 @@ * assume GCC is being used. */ -typedef unsigned long __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned long __kernel_mode_t; -typedef unsigned long __kernel_nlink_t; +typedef unsigned int __kernel_dev_t; +typedef unsigned int __kernel_ino_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned int __kernel_nlink_t; typedef long __kernel_off_t; -typedef long __kernel_pid_t; -typedef long __kernel_ipc_pid_t; -typedef long __kernel_uid_t; -typedef long __kernel_gid_t; +typedef int __kernel_pid_t; +typedef int __kernel_ipc_pid_t; +typedef int __kernel_uid_t; +typedef int __kernel_gid_t; typedef __SIZE_TYPE__ __kernel_size_t; typedef __SSIZE_TYPE__ __kernel_ssize_t; typedef __PTRDIFF_TYPE__ __kernel_ptrdiff_t; -typedef long __kernel_time_t; +typedef int __kernel_time_t; typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; +typedef int __kernel_clock_t; typedef long __kernel_daddr_t; typedef char * __kernel_caddr_t; @@ -43,7 +43,7 @@ typedef long long __kernel_loff_t; #endif typedef struct { - long val[2]; + int val[2]; } __kernel_fsid_t; #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) diff --git a/include/asm-mips64/processor.h b/include/asm-mips64/processor.h index d4251affc..7c1c76b8d 100644 --- a/include/asm-mips64/processor.h +++ b/include/asm-mips64/processor.h @@ -1,4 +1,4 @@ -/* $Id: processor.h,v 1.3 1999/09/27 20:56:47 ralf Exp $ +/* $Id: processor.h,v 1.3 1999/09/28 22:27:19 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -27,6 +27,7 @@ struct mips_cpuinfo { unsigned long udelay_val; unsigned long *pgd_quick; + unsigned long *pmd_quick; unsigned long *pte_quick; unsigned long pgtable_cache_sz; }; @@ -39,6 +40,7 @@ extern char wait_available; /* only available on R4[26]00 */ extern char cyclecounter_available; /* only available from R4000 upwards. */ extern char dedicated_iv_available; /* some embedded MIPS like Nevada */ extern char vce_available; /* Supports VCED / VCEI exceptions */ +extern char mips4_available; /* CPU has MIPS IV ISA or better */ extern struct mips_cpuinfo boot_cpu_data; extern unsigned int vced_count, vcei_count; @@ -72,12 +74,13 @@ extern int EISA_bus; extern struct task_struct *last_task_used_math; /* - * User space process size: 2GB. This is hardcoded into a few places, + * User space process size: 1TB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. TASK_SIZE - * for a 64 bit kernel expandable to 8192EB, of which the current MIPS - * implementations will "only" be able to use 1TB ... + * is limited to 1TB by the R4000 architecture; R10000 and better do + * support 16TB. +#define TASK_SIZE 0x80000000UL */ -#define TASK_SIZE (0x80000000UL) +#define TASK_SIZE 0x10000000000UL /* This decides where the kernel will search for a free chunk of vm * space during mmap's. @@ -92,9 +95,9 @@ extern struct task_struct *last_task_used_math; #define NUM_FPU_REGS 32 struct mips_fpu_hard_struct { - unsigned int fp_regs[NUM_FPU_REGS]; + unsigned long fp_regs[NUM_FPU_REGS]; unsigned int control; -} __attribute__((aligned(8))); +}; /* * FIXME: no fpu emulator yet (but who cares anyway?) @@ -136,7 +139,6 @@ struct thread_struct { unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; - unsigned long pg_dir; /* used in tlb refill */ #define MF_FIXADE 1 /* Fix address errors in software */ #define MF_LOGADE 2 /* Log address errors to syslog */ unsigned long mflags; @@ -150,7 +152,7 @@ struct thread_struct { #define INIT_MMAP { &init_mm, KSEG0, KSEG1, NULL, PAGE_SHARED, \ VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } -#define INIT_TSS { \ +#define INIT_THREAD { \ /* \ * saved main processor registers \ */ \ @@ -167,7 +169,7 @@ struct thread_struct { /* \ * Other stuff associated with the process \ */ \ - 0, 0, 0, 0, (unsigned long) swapper_pg_dir, \ + 0, 0, 0, 0, \ /* \ * For now the default is to fix address errors \ */ \ @@ -176,16 +178,18 @@ struct thread_struct { #ifdef __KERNEL__ -#define KERNEL_STACK_SIZE 8192 +/* Linus sez 16kb is good for you ... */ +#define KERNEL_STACK_SIZE 0x4000 #if !defined (_LANGUAGE_ASSEMBLY) /* Free all resources held by a thread. */ -extern void release_thread(struct task_struct *); +#define release_thread(thread) do { } while(0) + extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); /* Copy and release all segment info associated with a VM */ -#define copy_segments(nr, p, mm) do { } while(0) +#define copy_segments(p, mm) do { } while(0) #define release_segments(mm) do { } while(0) #define forget_segments() do { } while (0) @@ -214,16 +218,17 @@ extern int (*user_mode)(struct pt_regs *); regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KSU_USER;\ regs->cp0_epc = new_pc; \ regs->regs[29] = new_sp; \ - current->tss.current_ds = USER_DS; \ + current->thread.current_ds = USER_DS; \ } while (0) /* Allocation and freeing of basic task resources. */ /* * NOTE! The task struct and the stack go together */ +#define THREAD_SIZE (2*PAGE_SIZE) #define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) + ((struct task_struct *) __get_free_pages(GFP_KERNEL, 2)) +#define free_task_struct(p) free_pages((unsigned long)(p), 2) #define init_task (init_task_union.task) #define init_stack (init_task_union.stack) diff --git a/include/asm-mips64/ptrace.h b/include/asm-mips64/ptrace.h index 23c76b6b3..3e61613ca 100644 --- a/include/asm-mips64/ptrace.h +++ b/include/asm-mips64/ptrace.h @@ -1,4 +1,4 @@ -/* $Id: ptrace.h,v 1.1 1999/08/18 21:46:55 ralf Exp $ +/* $Id: ptrace.h,v 1.2 1999/09/28 22:27:19 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -23,14 +23,22 @@ #define FPC_EIR 70 #ifndef __ASSEMBLY__ + +#define abi64_no_regargs \ + unsigned long __dummy0, \ + unsigned long __dummy1, \ + unsigned long __dummy2, \ + unsigned long __dummy3, \ + unsigned long __dummy4, \ + unsigned long __dummy5, \ + unsigned long __dummy6, \ + unsigned long __dummy7 + /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { - /* Pad bytes for argument save space on the stack. */ - unsigned long pad0[8]; - /* Saved main processor registers. */ unsigned long regs[32]; diff --git a/include/asm-mips64/reboot.h b/include/asm-mips64/reboot.h deleted file mode 100644 index 217c4a828..000000000 --- a/include/asm-mips64/reboot.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1997, 1999 by Ralf Baechle - * - * Declare variables for rebooting. - */ -#ifndef _ASM_REBOOT_H -#define _ASM_REBOOT_H - -void (*_machine_restart)(char *command); -void (*_machine_halt)(void); -void (*_machine_power_off)(void); - -#endif /* _ASM_REBOOT_H */ diff --git a/include/asm-mips64/segment.h b/include/asm-mips64/segment.h new file mode 100644 index 000000000..92ac001fc --- /dev/null +++ b/include/asm-mips64/segment.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SEGMENT_H +#define _ASM_SEGMENT_H + +/* Only here because we have some old header files that expect it.. */ + +#endif /* _ASM_SEGMENT_H */ diff --git a/include/asm-mips64/semaphore-helper.h b/include/asm-mips64/semaphore-helper.h index 908d16c4b..fa2f70645 100644 --- a/include/asm-mips64/semaphore-helper.h +++ b/include/asm-mips64/semaphore-helper.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: semaphore-helper.h,v 1.2 1999/10/20 18:10:32 ralf Exp $ * * SMP- and interrupt-safe semaphores helper functions. * diff --git a/include/asm-mips64/semaphore.h b/include/asm-mips64/semaphore.h index b28d9999f..870975480 100644 --- a/include/asm-mips64/semaphore.h +++ b/include/asm-mips64/semaphore.h @@ -1,4 +1,4 @@ -/* $Id: semaphore.h,v 1.1 1999/08/18 23:37:52 ralf Exp $ +/* $Id: semaphore.h,v 1.3 1999/10/20 18:10:32 ralf Exp $ * * License. See the file "COPYING" in the main directory of this archive * for more details. diff --git a/include/asm-mips64/sgi/sgi.h b/include/asm-mips64/sgi/sgi.h index 1606e8d5a..0e6840aed 100644 --- a/include/asm-mips64/sgi/sgi.h +++ b/include/asm-mips64/sgi/sgi.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sgi.h,v 1.1 1999/08/20 21:13:37 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/include/asm-mips64/sgi/sgihpc.h b/include/asm-mips64/sgi/sgihpc.h index d862d9dc9..ab9ede57e 100644 --- a/include/asm-mips64/sgi/sgihpc.h +++ b/include/asm-mips64/sgi/sgihpc.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sgihpc.h,v 1.2 1999/10/19 20:51:54 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -22,8 +22,8 @@ extern int sgi_boardid; /* Board revision. */ /* An HPC dma descriptor. */ struct hpc_dma_desc { - unsigned long pbuf; /* physical address of data buffer */ - unsigned long cntinfo; /* counter and info bits */ + int pbuf; /* physical address of data buffer */ + int cntinfo; /* counter and info bits */ #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */ #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */ #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */ @@ -35,10 +35,10 @@ struct hpc_dma_desc { #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */ #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */ - unsigned long pnext; /* paddr of next hpc_dma_desc if any */ + int pnext; /* paddr of next hpc_dma_desc if any */ }; -typedef volatile unsigned long hpcreg; +typedef volatile unsigned int hpcreg; /* HPC1 stuff. */ @@ -332,7 +332,7 @@ extern struct hpc3_miscregs *hpc3mregs; #define HPC3_MREGS_PBASE 0x1fbd9800 /* physical */ /* We need software copies of these because they are write only. */ -extern unsigned long sgi_hpc_write1, sgi_hpc_write2; +extern unsigned int sgi_hpc_write1, sgi_hpc_write2; #define SGI_KEYBOARD_IRQ 20 diff --git a/include/asm-mips64/sgi/sgimc.h b/include/asm-mips64/sgi/sgimc.h index 9e236a564..56b5b5d19 100644 --- a/include/asm-mips64/sgi/sgimc.h +++ b/include/asm-mips64/sgi/sgimc.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sgimc.h,v 1.2 1999/10/19 20:51:54 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -8,13 +8,15 @@ * SGI IP20, IP22, IP26, and IP28 machines. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1999 Ralf Baechle + * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_SGI_SGIMC_H #define _ASM_SGI_SGIMC_H struct sgimc_misc_ctrl { - unsigned long _unused1; - volatile unsigned long cpuctrl0; /* CPU control register 0, readwrite */ + u32 _unused1; + volatile u32 cpuctrl0; /* CPU control register 0, readwrite */ #define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ #define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ @@ -35,8 +37,8 @@ struct sgimc_misc_ctrl { #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ #define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ - unsigned long _unused2; - volatile unsigned long cpuctrl1; /* CPU control register 1, readwrite */ + u32 _unused2; + volatile u32 cpuctrl1; /* CPU control register 1, readwrite */ #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ #define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ #define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ @@ -45,18 +47,18 @@ struct sgimc_misc_ctrl { #define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ #define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ - unsigned long _unused3; - volatile unsigned long watchdogt; /* Watchdog reg rdonly, write clears */ + u32 _unused3; + volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ - unsigned long _unused4; - volatile unsigned long systemid; /* MC system ID register, readonly */ + u32 _unused4; + volatile u32 systemid; /* MC system ID register, readonly */ #define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ #define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ - unsigned long _unused5[3]; - volatile unsigned long divider; /* Divider reg for RPSS */ + u32 _unused5[3]; + volatile u32 divider; /* Divider reg for RPSS */ - unsigned long _unused6; + u32 _unused6; volatile unsigned char eeprom; /* EEPROM byte reg for r4k */ #define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ #define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ @@ -65,16 +67,16 @@ struct sgimc_misc_ctrl { #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ unsigned char _unused7[3]; - unsigned long _unused8[3]; + u32 _unused8[3]; volatile unsigned short rcntpre; /* Preload refresh counter */ unsigned short _unused9; - unsigned long _unused9a; + u32 _unused9a; volatile unsigned short rcounter; /* Readonly refresh counter */ unsigned short _unused10; - unsigned long _unused11[13]; - volatile unsigned long gioparm; /* Parameter word for GIO64 */ + u32 _unused11[13]; + volatile u32 gioparm; /* Parameter word for GIO64 */ #define SGIMC_GIOPARM_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ #define SGIMC_GIOPARM_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ #define SGIMC_GIOPARM_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ @@ -92,18 +94,18 @@ struct sgimc_misc_ctrl { #define SGIMC_GIOPARM_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ #define SGIMC_GIOPARM_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ - unsigned long _unused13; + u32 _unused13; volatile unsigned short cputp; /* CPU bus arb time period */ unsigned short _unused14; - unsigned long _unused15[3]; + u32 _unused15[3]; volatile unsigned short lbursttp; /* Time period for long bursts */ unsigned short _unused16; - unsigned long _unused17[9]; - volatile unsigned long mconfig0; /* Memory config register zero */ - unsigned long _unused18; - volatile unsigned long mconfig1; /* Memory config register one */ + u32 _unused17[9]; + volatile u32 mconfig0; /* Memory config register zero */ + u32 _unused18; + volatile u32 mconfig1; /* Memory config register one */ /* These defines apply to both mconfig registers above. */ #define SGIMC_MCONFIG_FOURMB 0x00000000 /* Physical ram = 4megs */ @@ -114,99 +116,99 @@ struct sgimc_misc_ctrl { #define SGIMC_MCONFIG_OTEIGHTMB 0x00001f00 /* Physical ram = 128megs */ #define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ - unsigned long _unused19; - volatile unsigned long cmacc; /* Mem access config for CPU */ - unsigned long _unused20; - volatile unsigned long gmacc; /* Mem access config for GIO */ + u32 _unused19; + volatile u32 cmacc; /* Mem access config for CPU */ + u32 _unused20; + volatile u32 gmacc; /* Mem access config for GIO */ /* This define applies to both cmacc and gmacc registers above. */ #define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ /* Error address/status regs from GIO and CPU perspectives. */ - unsigned long _unused21; - volatile unsigned long cerr; /* Error address reg for CPU */ - unsigned long _unused22; - volatile unsigned long cstat; /* Status reg for CPU */ - unsigned long _unused23; - volatile unsigned long gerr; /* Error address reg for GIO */ - unsigned long _unused24; - volatile unsigned long gstat; /* Status reg for GIO */ + u32 _unused21; + volatile u32 cerr; /* Error address reg for CPU */ + u32 _unused22; + volatile u32 cstat; /* Status reg for CPU */ + u32 _unused23; + volatile u32 gerr; /* Error address reg for GIO */ + u32 _unused24; + volatile u32 gstat; /* Status reg for GIO */ /* Special hard bus locking registers. */ - unsigned long _unused25; + u32 _unused25; volatile unsigned char syssembit; /* Uni-bit system semaphore */ unsigned char _unused26[3]; - unsigned long _unused27; + u32 _unused27; volatile unsigned char mlock; /* Global GIO memory access lock */ unsigned char _unused28[3]; - unsigned long _unused29; + u32 _unused29; volatile unsigned char elock; /* Locks EISA from GIO accesses */ /* GIO dma control registers. */ unsigned char _unused30[3]; - unsigned long _unused31[14]; - volatile unsigned long gio_dma_trans;/* DMA mask to translation GIO addrs */ - unsigned long _unused32; - volatile unsigned long gio_dma_sbits;/* DMA GIO addr substitution bits */ - unsigned long _unused33; - volatile unsigned long dma_intr_cause; /* DMA IRQ cause indicator bits */ - unsigned long _unused34; - volatile unsigned long dma_ctrl; /* Main DMA control reg */ + u32 _unused31[14]; + volatile u32 gio_dma_trans;/* DMA mask to translation GIO addrs */ + u32 _unused32; + volatile u32 gio_dma_sbits;/* DMA GIO addr substitution bits */ + u32 _unused33; + volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */ + u32 _unused34; + volatile u32 dma_ctrl; /* Main DMA control reg */ /* DMA TLB entry 0 */ - unsigned long _unused35; - volatile unsigned long dtlb_hi0; - unsigned long _unused36; - volatile unsigned long dtlb_lo0; + u32 _unused35; + volatile u32 dtlb_hi0; + u32 _unused36; + volatile u32 dtlb_lo0; /* DMA TLB entry 1 */ - unsigned long _unused37; - volatile unsigned long dtlb_hi1; - unsigned long _unused38; - volatile unsigned long dtlb_lo1; + u32 _unused37; + volatile u32 dtlb_hi1; + u32 _unused38; + volatile u32 dtlb_lo1; /* DMA TLB entry 2 */ - unsigned long _unused39; - volatile unsigned long dtlb_hi2; - unsigned long _unused40; - volatile unsigned long dtlb_lo2; + u32 _unused39; + volatile u32 dtlb_hi2; + u32 _unused40; + volatile u32 dtlb_lo2; /* DMA TLB entry 3 */ - unsigned long _unused41; - volatile unsigned long dtlb_hi3; - unsigned long _unused42; - volatile unsigned long dtlb_lo3; + u32 _unused41; + volatile u32 dtlb_hi3; + u32 _unused42; + volatile u32 dtlb_lo3; }; /* MC misc control registers live at physical 0x1fa00000. */ extern struct sgimc_misc_ctrl *mcmisc_regs; -extern unsigned long *rpsscounter; /* Chirps at 100ns */ +extern u32 *rpsscounter; /* Chirps at 100ns */ struct sgimc_dma_ctrl { - unsigned long _unused1; - volatile unsigned long maddronly; /* Address DMA goes at */ - unsigned long _unused2; - volatile unsigned long maddrpdeflts; /* Same as above, plus set defaults */ - unsigned long _unused3; - volatile unsigned long dmasz; /* DMA count */ - unsigned long _unused4; - volatile unsigned long ssize; /* DMA stride size */ - unsigned long _unused5; - volatile unsigned long gmaddronly; /* Set GIO DMA but do not start trans */ - unsigned long _unused6; - volatile unsigned long dmaddnpgo; /* Set GIO DMA addr + start transfer */ - unsigned long _unused7; - volatile unsigned long dmamode; /* DMA mode config bit settings */ - unsigned long _unused8; - volatile unsigned long dmacount; /* Zoom and byte count for DMA */ - unsigned long _unused9; - volatile unsigned long dmastart; /* Pedal to the metal. */ - unsigned long _unused10; - volatile unsigned long dmarunning; /* DMA op is in progress */ - unsigned long _unused11; + u32 _unused1; + volatile u32 maddronly; /* Address DMA goes at */ + u32 _unused2; + volatile u32 maddrpdeflts; /* Same as above, plus set defaults */ + u32 _unused3; + volatile u32 dmasz; /* DMA count */ + u32 _unused4; + volatile u32 ssize; /* DMA stride size */ + u32 _unused5; + volatile u32 gmaddronly; /* Set GIO DMA but do not start trans */ + u32 _unused6; + volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */ + u32 _unused7; + volatile u32 dmamode; /* DMA mode config bit settings */ + u32 _unused8; + volatile u32 dmacount; /* Zoom and byte count for DMA */ + u32 _unused9; + volatile u32 dmastart; /* Pedal to the metal. */ + u32 _unused10; + volatile u32 dmarunning; /* DMA op is in progress */ + u32 _unused11; /* Set dma addr, defaults, and kick it */ - volatile unsigned long maddr_defl_go; /* go go go! -lm */ + volatile u32 maddr_defl_go; /* go go go! -lm */ }; /* MC controller dma regs live at physical 0x1fa02000. */ @@ -217,7 +219,7 @@ extern struct sgimc_dma_ctrl *dmactrlregs; #define SGIMC_SEG1_BADDR 0x20000000 /* Maximum size of the above banks are per machine. */ -extern unsigned long sgimc_seg0_size, sgimc_seg1_size; +extern u32 sgimc_seg0_size, sgimc_seg1_size; #define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ #define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ #define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ diff --git a/include/asm-mips64/sgi/sgint23.h b/include/asm-mips64/sgi/sgint23.h index 1633345ef..83c465b62 100644 --- a/include/asm-mips64/sgi/sgint23.h +++ b/include/asm-mips64/sgi/sgint23.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sgint23.h,v 1.3 1999/10/20 18:10:32 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -25,6 +25,32 @@ #define SGINT_HPCDMA 41 /* INDY has 11 HPCDMA irq _sources_ */ #define SGINT_END 52 /* End of 'spaces' */ +/* Individual interrupt definitions for the INDY and Indigo2 + */ + +#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ +#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ +#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ + +#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ + +#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ +#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ +#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ + +/* Individual interrupt definitions for the INDY and Indigo2 + */ + +#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */ +#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */ +#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */ + +#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */ + +#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */ +#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */ +#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */ + /* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */ #define SGI_INT2_BASE 0x1fbd9000 /* physical */ #define SGI_INT3_BASE 0x1fbd9880 /* physical */ @@ -141,7 +167,7 @@ struct sgi_ioc_timers { struct sgi_int2_regs { struct sgi_ioc_ints ints; - volatile unsigned long ledbits; /* LED control bits */ + volatile u32 ledbits; /* LED control bits */ #define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */ #define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */ #define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */ @@ -160,8 +186,8 @@ struct sgi_int2_regs { /* I am guesing there are only two unused registers here * but I could be wrong... - andrewb */ -/* unsigned long _unused[3]; */ - unsigned long _unused[2]; +/* u32 _unused[3]; */ + u32 _unused[2]; struct sgi_ioc_timers timers; }; @@ -170,13 +196,13 @@ struct sgi_int3_regs { #ifdef __MIPSEB__ unsigned char _unused0[3]; - volatile unsigned char tclear; /* Timer clear strobe address */ + volatile unsigned char tclear; /* Timer clear strobe address */ #else - volatile unsigned char tclear; /* Timer clear strobe address */ + volatile unsigned char tclear; /* Timer clear strobe address */ unsigned char _unused0[3]; #endif - volatile unsigned long estatus; /* Error status reg */ - unsigned long _unused1[2]; + volatile u32 estatus; /* Error status reg */ + u32 _unused1[2]; struct sgi_ioc_timers timers; }; diff --git a/include/asm-mips64/sgialib.h b/include/asm-mips64/sgialib.h index 0aa83307a..cafa0aa1c 100644 --- a/include/asm-mips64/sgialib.h +++ b/include/asm-mips64/sgialib.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sgialib.h,v 1.2 1999/08/20 21:59:08 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,10 +13,16 @@ #include <asm/sgiarcs.h> -extern struct linux_promblock *sgi_pblock; +extern PSYSTEM_PARAMETER_BLOCK sgi_pblock; extern struct linux_romvec *romvec; extern int prom_argc; -extern char **prom_argv, **prom_envp; + +extern LONG *_prom_argv, *_prom_envp; + +/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer. + These macros take care of sign extension. */ +#define prom_argv(index) ((char *) (long) _prom_argv[(index)]) +#define prom_argc(index) ((char *) (long) _prom_argc[(index)]) extern int prom_flags; #define PROM_FLAG_ARCS 1 @@ -36,9 +42,9 @@ extern void prom_printf(char *fmt, ...); /* Memory descriptor management. */ #define PROM_MAX_PMEMBLOCKS 32 struct prom_pmemblock { - unsigned long base; /* Within KSEG0. */ - unsigned int size; /* In bytes. */ - unsigned int type; /* free or prom memory */ + LONG base; /* Within KSEG0. */ + ULONG size; /* In bytes. */ + ULONG type; /* free or prom memory */ }; /* Get next memory descriptor after CURR, returns first descriptor @@ -60,10 +66,10 @@ extern struct prom_pmemblock *prom_getpblock_array(void); #define PROM_NULL_COMPONENT ((pcomponent *) 0) /* Get sibling component of THIS. */ -extern pcomponent *prom_getsibling(pcomponent *this); +extern pcomponent *ArcGetPeer(pcomponent *this); /* Get child component of THIS. */ -extern pcomponent *prom_getchild(pcomponent *this); +extern pcomponent *ArcGetChild(pcomponent *this); /* Get parent component of CHILD. */ extern pcomponent *prom_getparent(pcomponent *child); @@ -85,8 +91,8 @@ extern pcomponent *prom_componentbypath(char *path); extern void prom_identify_arch(void); /* Environemt variable routines. */ -extern char *prom_getenv(char *name); -extern long prom_setenv(char *name, char *value); +extern PCHAR ArcGetEnvironmentVariable(PCHAR name); +extern LONG SetEnvironmentVariable(PCHAR name, PCHAR value); /* ARCS command line acquisition and parsing. */ extern char *prom_getcmdline(void); @@ -100,9 +106,9 @@ extern unsigned long prom_getrtime(void); extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt); extern long prom_open(char *name, enum linux_omode md, unsigned long *fd); extern long prom_close(unsigned long fd); -extern long prom_read(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt); +extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); extern long prom_getrstatus(unsigned long fd); -extern long prom_write(unsigned long fd, void *buf, unsigned long num, unsigned long *cnt); +extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm); extern long prom_mount(char *name, enum linux_mountops op); extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf); @@ -117,8 +123,8 @@ extern long prom_exec(char *name, long argc, char **argv, char **envp); extern void prom_halt(void) __attribute__((noreturn)); extern void prom_powerdown(void) __attribute__((noreturn)); extern void prom_restart(void) __attribute__((noreturn)); -extern void prom_reboot(void) __attribute__((noreturn)); -extern void prom_imode(void) __attribute__((noreturn)); +extern VOID ArcReboot(VOID) __attribute__((noreturn)); +extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); extern long prom_cfgsave(void); extern struct linux_sysid *prom_getsysid(void); extern void prom_cacheflush(void); diff --git a/include/asm-mips64/sgiarcs.h b/include/asm-mips64/sgiarcs.h index 8aed20dce..632920b3b 100644 --- a/include/asm-mips64/sgiarcs.h +++ b/include/asm-mips64/sgiarcs.h @@ -1,4 +1,4 @@ -/* $Id: sgiarcs.h,v 1.2 1999/08/20 21:59:08 ralf Exp $ +/* $Id: sgiarcs.h,v 1.3 1999/08/21 22:19:17 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,6 +13,8 @@ #ifndef _ASM_SGIARCS_H #define _ASM_SGIARCS_H +#include <asm/arc/types.h> + /* Various ARCS error codes. */ #define PROM_ESUCCESS 0x00 #define PROM_E2BIG 0x01 @@ -75,16 +77,16 @@ enum linux_identifier { /* A prom device tree component. */ struct linux_component { - enum linux_devclass class; /* node class */ - enum linux_devtypes type; /* node type */ - enum linux_identifier iflags; /* node flags */ - unsigned short vers; /* node version */ - unsigned short rev; /* node revision */ - unsigned long key; /* completely magic */ - unsigned long amask; /* XXX affinity mask??? */ - unsigned long cdsize; /* size of configuration data */ - unsigned long ilen; /* length of string identifier */ - char *iname; /* string identifier */ + enum linux_devclass class; /* node class */ + enum linux_devtypes type; /* node type */ + enum linux_identifier iflags; /* node flags */ + USHORT vers; /* node version */ + USHORT rev; /* node revision */ + ULONG key; /* completely magic */ + ULONG amask; /* XXX affinity mask??? */ + ULONG cdsize; /* size of configuration data */ + ULONG ilen; /* length of string identifier */ + _PULONG iname; /* string identifier */ }; typedef struct linux_component pcomponent; @@ -122,9 +124,9 @@ union linux_memtypes { }; struct linux_mdesc { - union linux_memtypes type; - unsigned long base; - unsigned long pages; + union linux_memtypes type; + ULONG base; + ULONG pages; }; /* Time of day descriptor. */ @@ -180,104 +182,91 @@ struct linux_finfo { char name[32]; /* XXX imperical, should be define */ }; +/* This describes the vector containing fuction pointers to the ARC + firmware functions. */ struct linux_romvec { - /* Load an executable image. */ - long (*load)(char *file, unsigned long end, - unsigned long *start_pc, - unsigned long *end_addr); - - /* Invoke a standalong image. */ - long (*invoke)(unsigned long startpc, unsigned long sp, - long argc, char **argv, char **envp); - - /* Load and begin execution of a standalong image. */ - long (*exec)(char *file, long argc, char **argv, char **envp); - - void (*halt)(void) __attribute__((noreturn)); /* Halt the machine. */ - void (*pdown)(void) __attribute__((noreturn)); /* Power down the machine. */ - void (*restart)(void) __attribute__((noreturn)); /* XXX soft reset??? */ - void (*reboot)(void) __attribute__((noreturn)); /* Reboot the machine. */ - void (*imode)(void) __attribute__((noreturn)); /* Enter PROM interactive mode. */ - int _unused1; /* padding */ + LONG load; /* Load an executable image. */ + LONG invoke; /* Invoke a standalong image. */ + LONG exec; /* Load and begin execution of a + standalone image. */ + LONG halt; /* Halt the machine. */ + LONG pdown; /* Power down the machine. */ + LONG restart; /* XXX soft reset??? */ + LONG reboot; /* Reboot the machine. */ + LONG imode; /* Enter PROM interactive mode. */ + LONG _unused1; /* Was ReturnFromMain(). */ /* PROM device tree interface. */ - pcomponent *(*next_component)(pcomponent *this); - pcomponent *(*child_component)(pcomponent *this); - pcomponent *(*parent_component)(pcomponent *this); - long (*component_data)(void *opaque_data, pcomponent *this); - pcomponent *(*child_add)(pcomponent *this, - pcomponent *tmp, - void *opaque_data); - long (*comp_del)(pcomponent *this); - pcomponent *(*component_by_path)(char *file); + LONG next_component; + LONG child_component; + LONG parent_component; + LONG component_data; + LONG child_add; + LONG comp_del; + LONG component_by_path; /* Misc. stuff. */ - long (*cfg_save)(void); - struct linux_sysid *(*get_sysid)(void); + LONG cfg_save; + LONG get_sysid; /* Probing for memory. */ - struct linux_mdesc *(*get_mdesc)(struct linux_mdesc *curr); - long _unused2; /* padding */ + LONG get_mdesc; + LONG _unused2; /* was Signal() */ - struct linux_tinfo *(*get_tinfo)(void); - unsigned long (*get_rtime)(void); + LONG get_tinfo; + LONG get_rtime; /* File type operations. */ - long (*get_vdirent)(unsigned long fd, struct linux_vdirent *entry, - unsigned long num, unsigned long *count); - long (*open)(char *file, enum linux_omode mode, unsigned long *fd); - long (*close)(unsigned long fd); - long (*read)(unsigned long fd, void *buffer, unsigned long num, - unsigned long *count); - long (*get_rstatus)(unsigned long fd); - long (*write)(unsigned long fd, void *buffer, unsigned long num, - unsigned long *count); - long (*seek)(unsigned long fd, struct linux_bigint *offset, - enum linux_seekmode smode); - long (*mount)(char *file, enum linux_mountops op); + LONG get_vdirent; + LONG open; + LONG close; + LONG read; + LONG get_rstatus; + LONG write; + LONG seek; + LONG mount; /* Dealing with firmware environment variables. */ - char *(*get_evar)(char *name); - long (*set_evar)(char *name, char *value); + LONG get_evar; + LONG set_evar; - long (*get_finfo)(unsigned long fd, struct linux_finfo *buf); - long (*set_finfo)(unsigned long fd, unsigned long flags, - unsigned long mask); + LONG get_finfo; + LONG set_finfo; /* Miscellaneous. */ - void (*cache_flush)(void); + LONG cache_flush; }; /* The SGI ARCS parameter block is in a fixed location for standalone * programs to access PROM facilities easily. */ -struct linux_promblock { - long magic; /* magic cookie */ +typedef struct _SYSTEM_PARAMETER_BLOCK { + ULONG magic; /* magic cookie */ #define PROMBLOCK_MAGIC 0x53435241 - unsigned long len; /* length of parm block */ - unsigned short ver; /* ARCS firmware version */ - unsigned short rev; /* ARCS firmware revision */ - long *rs_block; /* Restart block. */ - long *dbg_block; /* Debug block. */ - long *gevect; /* XXX General vector??? */ - long *utlbvect; /* XXX UTLB vector??? */ - unsigned long rveclen; /* Size of romvec struct. */ - struct linux_romvec *romvec; /* Function interface. */ - unsigned long pveclen; /* Length of private vector. */ - long *pvector; /* Private vector. */ - long adap_cnt; /* Adapter count. */ - long adap_typ0; /* First adapter type. */ - long adap_vcnt0; /* Adapter 0 vector count. */ - long *adap_vector; /* Adapter 0 vector ptr. */ - long adap_typ1; /* Second adapter type. */ - long adap_vcnt1; /* Adapter 1 vector count. */ - long *adap_vector1; /* Adapter 1 vector ptr. */ + ULONG len; /* length of parm block */ + USHORT ver; /* ARCS firmware version */ + USHORT rev; /* ARCS firmware revision */ + _PLONG rs_block; /* Restart block. */ + _PLONG dbg_block; /* Debug block. */ + _PLONG gevect; /* XXX General vector??? */ + _PLONG utlbvect; /* XXX UTLB vector??? */ + ULONG rveclen; /* Size of romvec struct. */ + _PVOID romvec; /* Function interface. */ + ULONG pveclen; /* Length of private vector. */ + _PVOID pvector; /* Private vector. */ + ULONG adap_cnt; /* Adapter count. */ + ULONG adap_typ0; /* First adapter type. */ + ULONG adap_vcnt0; /* Adapter 0 vector count. */ + _PVOID adap_vector; /* Adapter 0 vector ptr. */ + ULONG adap_typ1; /* Second adapter type. */ + ULONG adap_vcnt1; /* Adapter 1 vector count. */ + _PVOID adap_vector1; /* Adapter 1 vector ptr. */ /* More adapter vectors go here... */ -}; +} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK; -#define PROMBLOCK ((struct linux_promblock *)0xA0001000UL) -#define ROMVECTOR ((PROMBLOCK)->romvec) +#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000) +#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec) /* Cache layout parameter block. */ union linux_cache_key { @@ -381,7 +370,7 @@ struct linux_smonblock { #define ARC_CALL0(dest) \ ({ long __res; \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "jalr\t%1\n\t" \ @@ -396,7 +385,7 @@ struct linux_smonblock { #define ARC_CALL1(dest,a1) \ ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "jalr\t%1\n\t" \ @@ -412,7 +401,7 @@ struct linux_smonblock { ({ long __res; \ register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "jalr\t%1\n\t" \ @@ -429,7 +418,7 @@ struct linux_smonblock { register signed int __a1 __asm__("$4") = (int) (long) (a1); \ register signed int __a2 __asm__("$5") = (int) (long) (a2); \ register signed int __a3 __asm__("$6") = (int) (long) (a3); \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "jalr\t%1\n\t" \ @@ -447,7 +436,7 @@ struct linux_smonblock { register signed int __a2 __asm__("$5") = (int) (long) (a2); \ register signed int __a3 __asm__("$6") = (int) (long) (a3); \ register signed int __a4 __asm__("$7") = (int) (long) (a4); \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "jalr\t%1\n\t" \ @@ -467,7 +456,7 @@ struct linux_smonblock { register signed int __a3 __asm__("$6") = (int) (long) (a3); \ register signed int __a4 __asm__("$7") = (int) (long) (a4); \ register signed int __a5 = (a5); \ - unsigned long __vec = (unsigned long) romvec->dest; \ + long __vec = (long) romvec->dest; \ __asm__ __volatile__( \ "dsubu\t$29, 32\n\t" \ "sw\t%6, 16($29)\n\t" \ diff --git a/include/asm-mips64/softirq.h b/include/asm-mips64/softirq.h index 0c234fa50..f827649ed 100644 --- a/include/asm-mips64/softirq.h +++ b/include/asm-mips64/softirq.h @@ -9,12 +9,6 @@ #ifndef _ASM_SOFTIRQ_H #define _ASM_SOFTIRQ_H -/* The locking mechanism for base handlers, to prevent re-entrancy, - * is entirely private to an implementation, it should not be - * referenced at all outside of this file. - */ -extern atomic_t __mips_bh_counter; - extern unsigned int local_bh_count[NR_CPUS]; #define cpu_bh_disable(cpu) do { local_bh_count[(cpu)]++; barrier(); } while (0) @@ -33,9 +27,9 @@ static inline void clear_active_bhs(unsigned long x) unsigned long temp; __asm__ __volatile__( - "1:\tll\t%0,%1\n\t" + "1:\tlld\t%0,%1\n\t" "and\t%0,%2\n\t" - "sc\t%0,%1\n\t" + "scd\t%0,%1\n\t" "beqz\t%0,1b" :"=&r" (temp), "=m" (bh_active) diff --git a/include/asm-mips64/stackframe.h b/include/asm-mips64/stackframe.h index a9e62c232..5599593ce 100644 --- a/include/asm-mips64/stackframe.h +++ b/include/asm-mips64/stackframe.h @@ -21,15 +21,15 @@ #define save_static(frame) \ __asm__ __volatile__( \ - "sw\t$16,"__str(PT_R16)"(%0)\n\t" \ - "sw\t$17,"__str(PT_R17)"(%0)\n\t" \ - "sw\t$18,"__str(PT_R18)"(%0)\n\t" \ - "sw\t$19,"__str(PT_R19)"(%0)\n\t" \ - "sw\t$20,"__str(PT_R20)"(%0)\n\t" \ - "sw\t$21,"__str(PT_R21)"(%0)\n\t" \ - "sw\t$22,"__str(PT_R22)"(%0)\n\t" \ - "sw\t$23,"__str(PT_R23)"(%0)\n\t" \ - "sw\t$30,"__str(PT_R30)"(%0)\n\t" \ + "sd\t$16,"__str(PT_R16)"(%0)\n\t" \ + "sd\t$17,"__str(PT_R17)"(%0)\n\t" \ + "sd\t$18,"__str(PT_R18)"(%0)\n\t" \ + "sd\t$19,"__str(PT_R19)"(%0)\n\t" \ + "sd\t$20,"__str(PT_R20)"(%0)\n\t" \ + "sd\t$21,"__str(PT_R21)"(%0)\n\t" \ + "sd\t$22,"__str(PT_R22)"(%0)\n\t" \ + "sd\t$23,"__str(PT_R23)"(%0)\n\t" \ + "sd\t$30,"__str(PT_R30)"(%0)\n\t" \ : /* No outputs */ \ : "r" (frame)) @@ -38,35 +38,38 @@ #ifdef _LANGUAGE_ASSEMBLY .macro SAVE_AT - sw $1, PT_R1(sp) + .set push + .set noat + sd $1, PT_R1(sp) + .set pop .endm .macro SAVE_TEMP mfhi v1 - sw $8, PT_R8(sp) - sw $9, PT_R9(sp) - sw v1, PT_HI(sp) + sd $8, PT_R8(sp) + sd $9, PT_R9(sp) + sd v1, PT_HI(sp) mflo v1 - sw $10,PT_R10(sp) - sw $11, PT_R11(sp) - sw v1, PT_LO(sp) - sw $12, PT_R12(sp) - sw $13, PT_R13(sp) - sw $14, PT_R14(sp) - sw $15, PT_R15(sp) - sw $24, PT_R24(sp) + sd $10, PT_R10(sp) + sd $11, PT_R11(sp) + sd v1, PT_LO(sp) + sd $12, PT_R12(sp) + sd $13, PT_R13(sp) + sd $14, PT_R14(sp) + sd $15, PT_R15(sp) + sd $24, PT_R24(sp) .endm .macro SAVE_STATIC - sw $16, PT_R16(sp) - sw $17, PT_R17(sp) - sw $18, PT_R18(sp) - sw $19, PT_R19(sp) - sw $20, PT_R20(sp) - sw $21, PT_R21(sp) - sw $22, PT_R22(sp) - sw $23, PT_R23(sp) - sw $30, PT_R30(sp) + sd $16, PT_R16(sp) + sd $17, PT_R17(sp) + sd $18, PT_R18(sp) + sd $19, PT_R19(sp) + sd $20, PT_R20(sp) + sd $21, PT_R21(sp) + sd $22, PT_R22(sp) + sd $23, PT_R23(sp) + sd $30, PT_R30(sp) .endm .macro SAVE_SOME @@ -80,28 +83,28 @@ .set reorder /* Called from user mode, new stack. */ lui k1, %hi(kernelsp) - lw k1, %lo(kernelsp)(k1) + ld k1, %lo(kernelsp)(k1) 8: move k0, sp - subu sp, k1, PT_SIZE - sw k0, PT_R29(sp) - sw $3, PT_R3(sp) - sw $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - sw $2, PT_R2(sp) - sw v1, PT_STATUS(sp) - sw $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - sw $5, PT_R5(sp) - sw v1, PT_CAUSE(sp) - sw $6, PT_R6(sp) - mfc0 v1, CP0_EPC - sw $7, PT_R7(sp) - sw v1, PT_EPC(sp) - sw $25, PT_R25(sp) - sw $28, PT_R28(sp) - sw $31, PT_R31(sp) - ori $28, sp, 0x1fff - xori $28, 0x1fff + dsubu sp, k1, PT_SIZE + sd k0, PT_R29(sp) + sd $3, PT_R3(sp) + sd $0, PT_R0(sp) + dmfc0 v1, CP0_STATUS + sd $2, PT_R2(sp) + sd v1, PT_STATUS(sp) + sd $4, PT_R4(sp) + dmfc0 v1, CP0_CAUSE + sd $5, PT_R5(sp) + sd v1, PT_CAUSE(sp) + sd $6, PT_R6(sp) + dmfc0 v1, CP0_EPC + sd $7, PT_R7(sp) + sd v1, PT_EPC(sp) + sd $25, PT_R25(sp) + sd $28, PT_R28(sp) + sd $31, PT_R31(sp) + ori $28, sp, 0x3fff + xori $28, 0x3fff .set pop .endm @@ -113,39 +116,39 @@ .endm .macro RESTORE_AT - lw $1, PT_R1(sp) + ld $1, PT_R1(sp) .endm .macro RESTORE_SP - lw sp, PT_R29(sp) + ld sp, PT_R29(sp) .endm .macro RESTORE_TEMP - lw $24, PT_LO(sp) - lw $8, PT_R8(sp) - lw $9, PT_R9(sp) + ld $24, PT_LO(sp) + ld $8, PT_R8(sp) + ld $9, PT_R9(sp) mtlo $24 - lw $24, PT_HI(sp) - lw $10,PT_R10(sp) - lw $11, PT_R11(sp) + ld $24, PT_HI(sp) + ld $10, PT_R10(sp) + ld $11, PT_R11(sp) mthi $24 - lw $12, PT_R12(sp) - lw $13, PT_R13(sp) - lw $14, PT_R14(sp) - lw $15, PT_R15(sp) - lw $24, PT_R24(sp) + ld $12, PT_R12(sp) + ld $13, PT_R13(sp) + ld $14, PT_R14(sp) + ld $15, PT_R15(sp) + ld $24, PT_R24(sp) .endm .macro RESTORE_STATIC - lw $16, PT_R16(sp) - lw $17, PT_R17(sp) - lw $18, PT_R18(sp) - lw $19, PT_R19(sp) - lw $20, PT_R20(sp) - lw $21, PT_R21(sp) - lw $22, PT_R22(sp) - lw $23, PT_R23(sp) - lw $30, PT_R30(sp) + ld $16, PT_R16(sp) + ld $17, PT_R17(sp) + ld $18, PT_R18(sp) + ld $19, PT_R19(sp) + ld $20, PT_R20(sp) + ld $21, PT_R21(sp) + ld $22, PT_R22(sp) + ld $23, PT_R23(sp) + ld $30, PT_R30(sp) .endm .macro RESTORE_SOME @@ -158,22 +161,22 @@ mtc0 t0, CP0_STATUS li v1, 0xff00 and t0, v1 - lw v0, PT_STATUS(sp) + ld v0, PT_STATUS(sp) nor v1, $0, v1 and v0, v1 or v0, t0 - mtc0 v0, CP0_STATUS - lw v1, PT_EPC(sp) - mtc0 v1, CP0_EPC - lw $31, PT_R31(sp) - lw $28, PT_R28(sp) - lw $25, PT_R25(sp) - lw $7, PT_R7(sp) - lw $6, PT_R6(sp) - lw $5, PT_R5(sp) - lw $4, PT_R4(sp) - lw $3, PT_R3(sp) - lw $2, PT_R2(sp) + dmtc0 v0, CP0_STATUS + ld v1, PT_EPC(sp) + dmtc0 v1, CP0_EPC + ld $31, PT_R31(sp) + ld $28, PT_R28(sp) + ld $25, PT_R25(sp) + ld $7, PT_R7(sp) + ld $6, PT_R6(sp) + ld $5, PT_R5(sp) + ld $4, PT_R4(sp) + ld $3, PT_R3(sp) + ld $2, PT_R2(sp) .endm .macro RESTORE_ALL @@ -201,11 +204,11 @@ * Set cp0 enable bit as sign that we're running on the kernel stack */ .macro STI - mfc0 t0,CP0_STATUS - li t1,ST0_CU0|0x1f - or t0,t1 - xori t0,0x1e - mtc0 t0,CP0_STATUS + mfc0 t0, CP0_STATUS + li t1, ST0_CU0 | 0x1f + or t0, t1 + xori t0, 0x1e + mtc0 t0, CP0_STATUS .endm /* @@ -214,7 +217,7 @@ */ .macro KMODE mfc0 t0, CP0_STATUS - li t1, ST0_CU0|0x1e + li t1, ST0_CU0 | 0x1e or t0, t1 xori t0, 0x1e mtc0 t0, CP0_STATUS diff --git a/include/asm-mips64/string.h b/include/asm-mips64/string.h index 56205991b..5f0b4e68d 100644 --- a/include/asm-mips64/string.h +++ b/include/asm-mips64/string.h @@ -1,4 +1,4 @@ -/* $Id: string.h,v 1.1 1999/08/18 23:37:52 ralf Exp $ +/* $Id: string.h,v 1.2 1999/08/21 22:19:18 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -12,14 +12,14 @@ #ifndef _ASM_STRING_H #define _ASM_STRING_H -#define __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); +#undef __HAVE_ARCH_MEMSET +//extern void *memset(void *__s, int __c, size_t __count); -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); +#undef __HAVE_ARCH_MEMCPY +//extern void *memcpy(void *__to, __const__ void *__from, size_t __n); -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); +#undef __HAVE_ARCH_MEMMOVE +//extern void *memmove(void *__dest, __const__ void *__src, size_t __n); /* Don't build bcopy at all ... */ #define __HAVE_ARCH_BCOPY diff --git a/include/asm-mips64/sysmips.h b/include/asm-mips64/sysmips.h new file mode 100644 index 000000000..af69c6f6c --- /dev/null +++ b/include/asm-mips64/sysmips.h @@ -0,0 +1,25 @@ +/* $Id: sysmips.h,v 1.1 1999/10/08 21:07:57 ralf Exp $ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995, 1999 by Ralf Baechle + * Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef _ASM_SYSMIPS_H +#define _ASM_SYSMIPS_H + +/* + * Commands for the sysmips(2) call + * + * sysmips(2) is deprecated - though some existing software uses it. + * We only support the following commands. + */ +#define SETNAME 1 /* set hostname */ +#define FLUSH_CACHE 3 /* writeback and invalidate caches */ +#define MIPS_FIXADE 7 /* control address error fixing */ +#define MIPS_RDNVRAM 10 /* read NVRAM */ +#define MIPS_ATOMIC_SET 2001 /* atomically set variable */ + +#endif /* _ASM_SYSMIPS_H */ diff --git a/include/asm-mips64/system.h b/include/asm-mips64/system.h index 76924b7f4..26b797da2 100644 --- a/include/asm-mips64/system.h +++ b/include/asm-mips64/system.h @@ -1,4 +1,4 @@ -/* $Id: system.h,v 1.2 1999/10/09 00:01:43 ralf Exp $ +/* $Id: system.h,v 1.3 1999/11/17 22:48:12 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -150,9 +150,10 @@ do { var = value; wmb(); } while (0) * switch_to(n) should switch tasks to task nr n, first * checking that n isn't the current task, in which case it does nothing. */ -extern asmlinkage void *(*resume)(void *last, void *next); +extern asmlinkage void *resume(void *last, void *next); #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +#define prepare_to_switch() do { } while(0) #define switch_to(prev,next,last) \ do { \ (last) = resume(prev, next); \ @@ -169,7 +170,7 @@ extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) "1:\tmove\t$1,%2\n\t" "sc\t$1,(%1)\n\t" "beqzl\t$1,1b\n\t" - "ll\t%0,(%1)\n\t" + "lld\t%0,(%1)\n\t" ".set\tat\n\t" ".set\treorder" : "=r" (val), "=r" (m), "=r" (dummy) diff --git a/include/asm-mips64/types.h b/include/asm-mips64/types.h index 99b23a1e9..cc07bde05 100644 --- a/include/asm-mips64/types.h +++ b/include/asm-mips64/types.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: types.h,v 1.1 1999/08/18 23:37:53 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -10,7 +10,7 @@ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H -typedef unsigned long umode_t; +typedef unsigned int umode_t; /* * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the diff --git a/include/asm-mips64/uaccess.h b/include/asm-mips64/uaccess.h index 1522748ff..a1950af06 100644 --- a/include/asm-mips64/uaccess.h +++ b/include/asm-mips64/uaccess.h @@ -1,4 +1,4 @@ -/* $Id: uaccess.h,v 1.1 1999/08/18 23:37:53 ralf Exp $ +/* $Id: uaccess.h,v 1.2 1999/08/19 22:56:35 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -23,15 +23,15 @@ * * For historical reasons, these macros are grossly misnamed. */ -#define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { 1UL }) +#define KERNEL_DS ((mm_segment_t) { (unsigned long) 0L }) +#define USER_DS ((mm_segment_t) { (unsigned long) -1L }) #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define get_fs() (current->tss.current_ds) +#define get_fs() (current->thread.current_ds) #define get_ds() (KERNEL_DS) -#define set_fs(x) (current->tss.current_ds=(x)) +#define set_fs(x) (current->thread.current_ds=(x)) #define segment_eq(a,b) ((a).seg == (b).seg) @@ -48,7 +48,7 @@ */ #define __access_ok(addr,size,mask) \ (((__signed__ long)((mask)&(addr | size | (addr+size)))) >= 0) -#define __access_mask (-(long)(get_fs().seg)) +#define __access_mask ((long)(get_fs().seg)) #define access_ok(type,addr,size) \ __access_ok(((unsigned long)(addr)),(size),__access_mask) @@ -385,7 +385,6 @@ strncpy_from_user(char *__to, const char *__from, long __len) return res; } - /* Returns: 0 if bad, string length+1 (memory size) of string if ok */ extern inline long __strlen_user(const char *s) { @@ -417,6 +416,39 @@ extern inline long strlen_user(const char *s) return res; } +/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ +extern inline long __strnlen_user(const char *s, long n) +{ + long res; + + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strlen_user_nocheck_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", "$8", "$31"); + + return res; +} + +extern inline long strnlen_user(const char *s, long n) +{ + long res; + + __asm__ __volatile__( + "move\t$4, %1\n\t" + "move\t$5, %2\n\t" + __MODULE_JAL(__strlen_user_asm) + "move\t%0, $2" + : "=r" (res) + : "r" (s), "r" (n) + : "$2", "$4", "$5", "$8", "$31"); + + return res; +} + struct exception_table_entry { unsigned long insn; diff --git a/include/asm-mips64/unistd.h b/include/asm-mips64/unistd.h index c6e295e4c..4793d8864 100644 --- a/include/asm-mips64/unistd.h +++ b/include/asm-mips64/unistd.h @@ -1,4 +1,4 @@ -/* $Id: unistd.h,v 1.3 1999/09/28 22:27:20 ralf Exp $ +/* $Id: unistd.h,v 1.4 1999/10/09 00:01:43 ralf Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -982,11 +982,229 @@ #define __NR_POSIX_SGI_reserved26 (__NR_POSIX + 319) /* - * Linux syscalls are in the range from 4000 to 4999 - * Hopefully these syscall numbers are unused ... If not everyone using - * statically linked binaries is pretty upsh*t. You've been warned. + * Linux o32 style syscalls are in the range from 4000 to 4999. */ -#define __NR_Linux 4000 +#define __NR_Linux32 4000 +#define __NR_Linux32_syscall (__NR_Linux32 + 0) +#define __NR_Linux32_exit (__NR_Linux32 + 1) +#define __NR_Linux32_fork (__NR_Linux32 + 2) +#define __NR_Linux32_read (__NR_Linux32 + 3) +#define __NR_Linux32_write (__NR_Linux32 + 4) +#define __NR_Linux32_open (__NR_Linux32 + 5) +#define __NR_Linux32_close (__NR_Linux32 + 6) +#define __NR_Linux32_waitpid (__NR_Linux32 + 7) +#define __NR_Linux32_creat (__NR_Linux32 + 8) +#define __NR_Linux32_link (__NR_Linux32 + 9) +#define __NR_Linux32_unlink (__NR_Linux32 + 10) +#define __NR_Linux32_execve (__NR_Linux32 + 11) +#define __NR_Linux32_chdir (__NR_Linux32 + 12) +#define __NR_Linux32_time (__NR_Linux32 + 13) +#define __NR_Linux32_mknod (__NR_Linux32 + 14) +#define __NR_Linux32_chmod (__NR_Linux32 + 15) +#define __NR_Linux32_lchown (__NR_Linux32 + 16) +#define __NR_Linux32_break (__NR_Linux32 + 17) +#define __NR_Linux32_oldstat (__NR_Linux32 + 18) +#define __NR_Linux32_lseek (__NR_Linux32 + 19) +#define __NR_Linux32_getpid (__NR_Linux32 + 20) +#define __NR_Linux32_mount (__NR_Linux32 + 21) +#define __NR_Linux32_umount (__NR_Linux32 + 22) +#define __NR_Linux32_setuid (__NR_Linux32 + 23) +#define __NR_Linux32_getuid (__NR_Linux32 + 24) +#define __NR_Linux32_stime (__NR_Linux32 + 25) +#define __NR_Linux32_ptrace (__NR_Linux32 + 26) +#define __NR_Linux32_alarm (__NR_Linux32 + 27) +#define __NR_Linux32_oldfstat (__NR_Linux32 + 28) +#define __NR_Linux32_unused29 (__NR_Linux32 + 29) +#define __NR_Linux32_utime (__NR_Linux32 + 30) +#define __NR_Linux32_stty (__NR_Linux32 + 31) +#define __NR_Linux32_gtty (__NR_Linux32 + 32) +#define __NR_Linux32_access (__NR_Linux32 + 33) +#define __NR_Linux32_nice (__NR_Linux32 + 34) +#define __NR_Linux32_ftime (__NR_Linux32 + 35) +#define __NR_Linux32_sync (__NR_Linux32 + 36) +#define __NR_Linux32_kill (__NR_Linux32 + 37) +#define __NR_Linux32_rename (__NR_Linux32 + 38) +#define __NR_Linux32_mkdir (__NR_Linux32 + 39) +#define __NR_Linux32_rmdir (__NR_Linux32 + 40) +#define __NR_Linux32_dup (__NR_Linux32 + 41) +#define __NR_Linux32_pipe (__NR_Linux32 + 42) +#define __NR_Linux32_times (__NR_Linux32 + 43) +#define __NR_Linux32_prof (__NR_Linux32 + 44) +#define __NR_Linux32_brk (__NR_Linux32 + 45) +#define __NR_Linux32_setgid (__NR_Linux32 + 46) +#define __NR_Linux32_getgid (__NR_Linux32 + 47) +#define __NR_Linux32_signal (__NR_Linux32 + 48) +#define __NR_Linux32_geteuid (__NR_Linux32 + 49) +#define __NR_Linux32_getegid (__NR_Linux32 + 50) +#define __NR_Linux32_acct (__NR_Linux32 + 51) +#define __NR_Linux32_umount2 (__NR_Linux32 + 52) +#define __NR_Linux32_lock (__NR_Linux32 + 53) +#define __NR_Linux32_ioctl (__NR_Linux32 + 54) +#define __NR_Linux32_fcntl (__NR_Linux32 + 55) +#define __NR_Linux32_mpx (__NR_Linux32 + 56) +#define __NR_Linux32_setpgid (__NR_Linux32 + 57) +#define __NR_Linux32_ulimit (__NR_Linux32 + 58) +#define __NR_Linux32_oldolduname (__NR_Linux32 + 59) +#define __NR_Linux32_umask (__NR_Linux32 + 60) +#define __NR_Linux32_chroot (__NR_Linux32 + 61) +#define __NR_Linux32_ustat (__NR_Linux32 + 62) +#define __NR_Linux32_dup2 (__NR_Linux32 + 63) +#define __NR_Linux32_getppid (__NR_Linux32 + 64) +#define __NR_Linux32_getpgrp (__NR_Linux32 + 65) +#define __NR_Linux32_setsid (__NR_Linux32 + 66) +#define __NR_Linux32_sigaction (__NR_Linux32 + 67) +#define __NR_Linux32_sgetmask (__NR_Linux32 + 68) +#define __NR_Linux32_ssetmask (__NR_Linux32 + 69) +#define __NR_Linux32_setreuid (__NR_Linux32 + 70) +#define __NR_Linux32_setregid (__NR_Linux32 + 71) +#define __NR_Linux32_sigsuspend (__NR_Linux32 + 72) +#define __NR_Linux32_sigpending (__NR_Linux32 + 73) +#define __NR_Linux32_sethostname (__NR_Linux32 + 74) +#define __NR_Linux32_setrlimit (__NR_Linux32 + 75) +#define __NR_Linux32_getrlimit (__NR_Linux32 + 76) +#define __NR_Linux32_getrusage (__NR_Linux32 + 77) +#define __NR_Linux32_gettimeofday (__NR_Linux32 + 78) +#define __NR_Linux32_settimeofday (__NR_Linux32 + 79) +#define __NR_Linux32_getgroups (__NR_Linux32 + 80) +#define __NR_Linux32_setgroups (__NR_Linux32 + 81) +#define __NR_Linux32_reserved82 (__NR_Linux32 + 82) +#define __NR_Linux32_symlink (__NR_Linux32 + 83) +#define __NR_Linux32_oldlstat (__NR_Linux32 + 84) +#define __NR_Linux32_readlink (__NR_Linux32 + 85) +#define __NR_Linux32_uselib (__NR_Linux32 + 86) +#define __NR_Linux32_swapon (__NR_Linux32 + 87) +#define __NR_Linux32_reboot (__NR_Linux32 + 88) +#define __NR_Linux32_readdir (__NR_Linux32 + 89) +#define __NR_Linux32_mmap (__NR_Linux32 + 90) +#define __NR_Linux32_munmap (__NR_Linux32 + 91) +#define __NR_Linux32_truncate (__NR_Linux32 + 92) +#define __NR_Linux32_ftruncate (__NR_Linux32 + 93) +#define __NR_Linux32_fchmod (__NR_Linux32 + 94) +#define __NR_Linux32_fchown (__NR_Linux32 + 95) +#define __NR_Linux32_getpriority (__NR_Linux32 + 96) +#define __NR_Linux32_setpriority (__NR_Linux32 + 97) +#define __NR_Linux32_profil (__NR_Linux32 + 98) +#define __NR_Linux32_statfs (__NR_Linux32 + 99) +#define __NR_Linux32_fstatfs (__NR_Linux32 + 100) +#define __NR_Linux32_ioperm (__NR_Linux32 + 101) +#define __NR_Linux32_socketcall (__NR_Linux32 + 102) +#define __NR_Linux32_syslog (__NR_Linux32 + 103) +#define __NR_Linux32_setitimer (__NR_Linux32 + 104) +#define __NR_Linux32_getitimer (__NR_Linux32 + 105) +#define __NR_Linux32_stat (__NR_Linux32 + 106) +#define __NR_Linux32_lstat (__NR_Linux32 + 107) +#define __NR_Linux32_fstat (__NR_Linux32 + 108) +#define __NR_Linux32_olduname (__NR_Linux32 + 109) +#define __NR_Linux32_iopl (__NR_Linux32 + 110) +#define __NR_Linux32_vhangup (__NR_Linux32 + 111) +#define __NR_Linux32_idle (__NR_Linux32 + 112) +#define __NR_Linux32_vm86 (__NR_Linux32 + 113) +#define __NR_Linux32_wait4 (__NR_Linux32 + 114) +#define __NR_Linux32_swapoff (__NR_Linux32 + 115) +#define __NR_Linux32_sysinfo (__NR_Linux32 + 116) +#define __NR_Linux32_ipc (__NR_Linux32 + 117) +#define __NR_Linux32_fsync (__NR_Linux32 + 118) +#define __NR_Linux32_sigreturn (__NR_Linux32 + 119) +#define __NR_Linux32_clone (__NR_Linux32 + 120) +#define __NR_Linux32_setdomainname (__NR_Linux32 + 121) +#define __NR_Linux32_uname (__NR_Linux32 + 122) +#define __NR_Linux32_modify_ldt (__NR_Linux32 + 123) +#define __NR_Linux32_adjtimex (__NR_Linux32 + 124) +#define __NR_Linux32_mprotect (__NR_Linux32 + 125) +#define __NR_Linux32_sigprocmask (__NR_Linux32 + 126) +#define __NR_Linux32_create_module (__NR_Linux32 + 127) +#define __NR_Linux32_init_module (__NR_Linux32 + 128) +#define __NR_Linux32_delete_module (__NR_Linux32 + 129) +#define __NR_Linux32_get_kernel_syms (__NR_Linux32 + 130) +#define __NR_Linux32_quotactl (__NR_Linux32 + 131) +#define __NR_Linux32_getpgid (__NR_Linux32 + 132) +#define __NR_Linux32_fchdir (__NR_Linux32 + 133) +#define __NR_Linux32_bdflush (__NR_Linux32 + 134) +#define __NR_Linux32_sysfs (__NR_Linux32 + 135) +#define __NR_Linux32_personality (__NR_Linux32 + 136) +#define __NR_Linux32_afs_syscall (__NR_Linux32 + 137) /* Syscall for Andrew File System */ +#define __NR_Linux32_setfsuid (__NR_Linux32 + 138) +#define __NR_Linux32_setfsgid (__NR_Linux32 + 139) +#define __NR_Linux32__llseek (__NR_Linux32 + 140) +#define __NR_Linux32_getdents (__NR_Linux32 + 141) +#define __NR_Linux32__newselect (__NR_Linux32 + 142) +#define __NR_Linux32_flock (__NR_Linux32 + 143) +#define __NR_Linux32_msync (__NR_Linux32 + 144) +#define __NR_Linux32_readv (__NR_Linux32 + 145) +#define __NR_Linux32_writev (__NR_Linux32 + 146) +#define __NR_Linux32_cacheflush (__NR_Linux32 + 147) +#define __NR_Linux32_cachectl (__NR_Linux32 + 148) +#define __NR_Linux32_sysmips (__NR_Linux32 + 149) +#define __NR_Linux32_unused150 (__NR_Linux32 + 150) +#define __NR_Linux32_getsid (__NR_Linux32 + 151) +#define __NR_Linux32_fdatasync (__NR_Linux32 + 152) +#define __NR_Linux32__sysctl (__NR_Linux32 + 153) +#define __NR_Linux32_mlock (__NR_Linux32 + 154) +#define __NR_Linux32_munlock (__NR_Linux32 + 155) +#define __NR_Linux32_mlockall (__NR_Linux32 + 156) +#define __NR_Linux32_munlockall (__NR_Linux32 + 157) +#define __NR_Linux32_sched_setparam (__NR_Linux32 + 158) +#define __NR_Linux32_sched_getparam (__NR_Linux32 + 159) +#define __NR_Linux32_sched_setscheduler (__NR_Linux32 + 160) +#define __NR_Linux32_sched_getscheduler (__NR_Linux32 + 161) +#define __NR_Linux32_sched_yield (__NR_Linux32 + 162) +#define __NR_Linux32_sched_get_priority_max (__NR_Linux32 + 163) +#define __NR_Linux32_sched_get_priority_min (__NR_Linux32 + 164) +#define __NR_Linux32_sched_rr_get_interval (__NR_Linux32 + 165) +#define __NR_Linux32_nanosleep (__NR_Linux32 + 166) +#define __NR_Linux32_mremap (__NR_Linux32 + 167) +#define __NR_Linux32_accept (__NR_Linux32 + 168) +#define __NR_Linux32_bind (__NR_Linux32 + 169) +#define __NR_Linux32_connect (__NR_Linux32 + 170) +#define __NR_Linux32_getpeername (__NR_Linux32 + 171) +#define __NR_Linux32_getsockname (__NR_Linux32 + 172) +#define __NR_Linux32_getsockopt (__NR_Linux32 + 173) +#define __NR_Linux32_listen (__NR_Linux32 + 174) +#define __NR_Linux32_recv (__NR_Linux32 + 175) +#define __NR_Linux32_recvfrom (__NR_Linux32 + 176) +#define __NR_Linux32_recvmsg (__NR_Linux32 + 177) +#define __NR_Linux32_send (__NR_Linux32 + 178) +#define __NR_Linux32_sendmsg (__NR_Linux32 + 179) +#define __NR_Linux32_sendto (__NR_Linux32 + 180) +#define __NR_Linux32_setsockopt (__NR_Linux32 + 181) +#define __NR_Linux32_shutdown (__NR_Linux32 + 182) +#define __NR_Linux32_socket (__NR_Linux32 + 183) +#define __NR_Linux32_socketpair (__NR_Linux32 + 184) +#define __NR_Linux32_setresuid (__NR_Linux32 + 185) +#define __NR_Linux32_getresuid (__NR_Linux32 + 186) +#define __NR_Linux32_query_module (__NR_Linux32 + 187) +#define __NR_Linux32_poll (__NR_Linux32 + 188) +#define __NR_Linux32_nfsservctl (__NR_Linux32 + 189) +#define __NR_Linux32_setresgid (__NR_Linux32 + 190) +#define __NR_Linux32_getresgid (__NR_Linux32 + 191) +#define __NR_Linux32_prctl (__NR_Linux32 + 192) +#define __NR_Linux32_rt_sigreturn (__NR_Linux32 + 193) +#define __NR_Linux32_rt_sigaction (__NR_Linux32 + 194) +#define __NR_Linux32_rt_sigprocmask (__NR_Linux32 + 195) +#define __NR_Linux32_rt_sigpending (__NR_Linux32 + 196) +#define __NR_Linux32_rt_sigtimedwait (__NR_Linux32 + 197) +#define __NR_Linux32_rt_sigqueueinfo (__NR_Linux32 + 198) +#define __NR_Linux32_rt_sigsuspend (__NR_Linux32 + 199) +#define __NR_Linux32_pread (__NR_Linux32 + 200) +#define __NR_Linux32_pwrite (__NR_Linux32 + 201) +#define __NR_Linux32_chown (__NR_Linux32 + 202) +#define __NR_Linux32_getcwd (__NR_Linux32 + 203) +#define __NR_Linux32_capget (__NR_Linux32 + 204) +#define __NR_Linux32_capset (__NR_Linux32 + 205) +#define __NR_Linux32_sigaltstack (__NR_Linux32 + 206) +#define __NR_Linux32_sendfile (__NR_Linux32 + 207) +#define __NR_Linux32_getpmsg (__NR_Linux32 + 208) +#define __NR_Linux32_putpmsg (__NR_Linux32 + 209) + +/* + * Offset of the last Linux o32 flavoured syscall + */ +#define __NR_Linux_syscalls 209 + +/* + * Linux 64-bit syscalls are in the range from 5000 to 5999. + */ +#define __NR_Linux 5000 #define __NR_syscall (__NR_Linux + 0) #define __NR_exit (__NR_Linux + 1) #define __NR_fork (__NR_Linux + 2) @@ -1398,8 +1616,8 @@ return -1; \ #else /* not N32 or 64 ABI */ -/* These are here for sake of fucked lusercode that fucking believes to - fucking have to fuck around with the syscall interface themselfes. */ +/* These are here for sake of fucking lusercode living in the fucking believe + having to fuck around with the syscall interface themselfes. */ #define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ type name (atype a,btype b,ctype c,dtype d,etype e) \ diff --git a/include/asm-ppc/adb.h b/include/asm-ppc/adb.h deleted file mode 100644 index c13b67bb5..000000000 --- a/include/asm-ppc/adb.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Definitions for ADB (Apple Desktop Bus) support. - */ -#ifndef __PPC_ADB_H -#define __PPC_ADB_H - -/* ADB commands */ -#define ADB_BUSRESET 0 -#define ADB_FLUSH(id) (1 + ((id) << 4)) -#define ADB_WRITEREG(id, reg) (8 + (reg) + ((id) << 4)) -#define ADB_READREG(id, reg) (0xc + (reg) + ((id) << 4)) - -/* ADB default device IDs (upper 4 bits of ADB command byte) */ -#define ADB_DONGLE 1 /* "software execution control" devices */ -#define ADB_KEYBOARD 2 -#define ADB_MOUSE 3 -#define ADB_TABLET 4 -#define ADB_MODEM 5 -#define ADB_MISC 7 /* maybe a monitor */ - -#define ADB_RET_OK 0 -#define ADB_RET_TIMEOUT 3 - -/* The kind of ADB request. The controller may emulate some - of all of those CUDA/PMU packet kinds */ -#define ADB_PACKET 0 -#define CUDA_PACKET 1 -#define ERROR_PACKET 2 -#define TIMER_PACKET 3 -#define POWER_PACKET 4 -#define MACIIC_PACKET 5 -#define PMU_PACKET 6 - -#ifdef __KERNEL__ - -struct adb_request { - unsigned char data[32]; - int nbytes; - unsigned char reply[32]; - int reply_len; - unsigned char reply_expected; - unsigned char sent; - unsigned char complete; - void (*done)(struct adb_request *); - void *arg; - struct adb_request *next; -}; - -struct adb_ids { - int nids; - unsigned char id[16]; -}; - -/* Messages sent thru the client_list notifier. You should NOT stop - the operation, at least not with this version */ -enum adb_message { - ADB_MSG_POWERDOWN, /* Currently called before sleep only */ - ADB_MSG_PRE_RESET, /* Called before resetting the bus */ - ADB_MSG_POST_RESET /* Called after resetting the bus (re-do init & register) */ -}; -extern struct notifier_block *adb_client_list; - -/* Kind of ADB controller */ -enum adb_hw { - ADB_NONE, ADB_VIACUDA, ADB_VIAPMU, ADB_MACIO, ADB_UNKNOWN -}; - -/* Definition of a controller */ -extern struct adb_controller { - enum adb_hw kind; - - int (*send_request)(struct adb_request *req, int sync); - int (*autopoll)(int devs); - int (*reset_bus)(void); - void (*poll)(void); -} *adb_controller; -extern enum adb_hw adb_hardware; - -/* Values for adb_request flags */ -#define ADBREQ_REPLY 1 /* expect reply */ -#define ADBREQ_SYNC 2 /* poll until done */ - -void adb_init(void); - -int adb_request(struct adb_request *req, void (*done)(struct adb_request *), - int flags, int nbytes, ...); -int adb_register(int default_id,int handler_id,struct adb_ids *ids, - void (*handler)(unsigned char *, int, struct pt_regs *, int)); -void adb_input(unsigned char *, int, struct pt_regs *, int); - -int adb_try_handler_change(int address, int new_id); -int adb_get_infos(int address, int *original_address, int *handler_id); - -int adb_reset_bus(void); - -void adb_poll(void); - -#endif /* __KERNEL__ */ - -#endif /* __PPC_ADB_H */ diff --git a/include/asm-ppc/adb_mouse.h b/include/asm-ppc/adb_mouse.h deleted file mode 100644 index 3da07c813..000000000 --- a/include/asm-ppc/adb_mouse.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef _LINUX_ADB_MOUSE_H -#define _LINUX_ADB_MOUSE_H - -/* - * linux/include/linux/mac_mouse.h - * header file for Macintosh ADB mouse driver - * 27-10-97 Michael Schmitz - * copied from: - * header file for Atari Mouse driver - * by Robert de Vries (robert@and.nl) on 19Jul93 - */ - -struct mouse_status { - char buttons; - short dx; - short dy; - int ready; - int active; - wait_queue_head_t wait; - struct fasync_struct *fasyncptr; -}; - -#endif diff --git a/include/asm-ppc/amigahw.h b/include/asm-ppc/amigahw.h index 7fae6f85c..491547376 100644 --- a/include/asm-ppc/amigahw.h +++ b/include/asm-ppc/amigahw.h @@ -1 +1,15 @@ +#ifndef __ASMPPC_AMIGAHW_H +#define __ASMPPC_AMIGAHW_H + +#include <linux/config.h> #include <asm-m68k/amigahw.h> + +#undef CHIP_PHYSADDR +#ifdef CONFIG_APUS_FAST_EXCEPT +#define CHIP_PHYSADDR (0x000000) +#else +#define CHIP_PHYSADDR (0x004000) +#endif + + +#endif /* __ASMPPC_AMIGAHW_H */ diff --git a/include/asm-ppc/amigappc.h b/include/asm-ppc/amigappc.h index bea284b2d..96e5e8f09 100644 --- a/include/asm-ppc/amigappc.h +++ b/include/asm-ppc/amigappc.h @@ -16,31 +16,25 @@ #ifndef __ASSEMBLY__ -#ifndef iobarrier_rw /* Don't include io.h - avoid circular dependency */ -#define iobarrier_rw() eieio() -#endif +/* #include <asm/system.h> */ +#define mb() __asm__ __volatile__ ("sync" : : : "memory") #define APUS_WRITE(_a_, _v_) \ do { \ (*((volatile unsigned char *)(_a_)) = (_v_)); \ - iobarrier_rw (); \ + mb(); \ } while (0) -#define APUS_READ(_a_, _v_) \ +#define APUS_READ(_a_, _v_) \ do { \ (_v_) = (*((volatile unsigned char *)(_a_))); \ - iobarrier_rw (); \ + mb(); \ } while (0) #endif /* ndef __ASSEMBLY__ */ /* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */ #define zTwoBase (0x80000000) -/* At CYBERBASEp we find the following sum: - * -KERNELBASE+CyberStormMemoryBase - */ -#define CYBERBASEp (0xfff00000) - #define APUS_IPL_BASE (zTwoBase + 0x00f60000) #define APUS_REG_RESET (APUS_IPL_BASE + 0x00) #define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10) diff --git a/include/asm-ppc/amigayle.h b/include/asm-ppc/amigayle.h index d604cc668..1fe0b8785 100644 --- a/include/asm-ppc/amigayle.h +++ b/include/asm-ppc/amigayle.h @@ -1 +1 @@ -#include "../asm-m68k/amigayle.h" +#include <asm-m68k/amigayle.h> diff --git a/include/asm-ppc/amipcmcia.h b/include/asm-ppc/amipcmcia.h index 3be263bd0..3f65f63f5 100644 --- a/include/asm-ppc/amipcmcia.h +++ b/include/asm-ppc/amipcmcia.h @@ -1 +1 @@ -#include "../asm-m68k/amipcmcia.h" +#include <asm-m68k/amipcmcia.h> diff --git a/include/asm-ppc/bootx.h b/include/asm-ppc/bootx.h index ad69eaa54..5674bd0f9 100644 --- a/include/asm-ppc/bootx.h +++ b/include/asm-ppc/bootx.h @@ -11,6 +11,7 @@ #ifdef macintosh #include <Types.h> +#include "linux_type_defs.h" #endif #ifdef macintosh @@ -18,66 +19,118 @@ #pragma options align=power #endif -/* On boostrap entry: +/* On kernel entry: * - * r3 = 0x426f6f58 ('BooX') + * r3 = 0x426f6f58 ('BooX') * r4 = pointer to boot_infos * r5 = NULL + * + * Data and instruction translation disabled, interrupts + * disabled, kernel loaded at physical 0x00000000 on PCI + * machines (will be different on NuBus). + */ + +#define BOOT_INFO_VERSION 5 +#define BOOT_INFO_COMPATIBLE_VERSION 1 + +/* Bit in the architecture flag mask. More to be defined in + future versions. Note that either BOOT_ARCH_PCI or + BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are + set additionally when BOOT_ARCH_NUBUS is set. */ +#define BOOT_ARCH_PCI 0x00000001UL +#define BOOT_ARCH_NUBUS 0x00000002UL +#define BOOT_ARCH_NUBUS_PDM 0x00000010UL +#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL +#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL + +/* Maximum number of ranges in phys memory map */ +#define MAX_MEM_MAP_SIZE 26 + +/* This is the format of an element in the physical memory map. Note that + the map is optional and current BootX will only build it for pre-PCI + machines */ +typedef struct boot_info_map_entry +{ + __u32 physAddr; /* Physical starting address */ + __u32 size; /* Size in bytes */ +} boot_info_map_entry_t; -#define BOOT_INFO_VERSION 2 -#define BOOT_INFO_COMPATIBLE_VERSION 1 /* Here are the boot informations that are passed to the bootstrap * Note that the kernel arguments and the device tree are appended * at the end of this structure. */ typedef struct boot_infos { - /* Version of this structure */ - unsigned long version; - /* backward compatible down to version: */ - unsigned long compatible_version; - - /* NEW (vers. 2) this holds the current _logical_ base addr of - the frame buffer (for use by early boot message) */ - unsigned char* logicalDisplayBase; - - /* Set to 0 by current BootX */ - unsigned long unused[2]; - - /* The device tree (internal addresses relative to the beginning of the tree, - * device tree offset relative to the beginning of this structure). */ - unsigned long deviceTreeOffset; /* Device tree offset */ - unsigned long deviceTreeSize; /* Size of the device tree */ - - /* Some infos about the current MacOS display */ - unsigned long dispDeviceRect[4]; /* left,top,right,bottom */ - unsigned long dispDeviceDepth; /* (8, 16 or 32) */ - unsigned char* dispDeviceBase; /* base address (physical) */ - unsigned long dispDeviceRowBytes; /* rowbytes (in bytes) */ - unsigned long dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ - /* Optional offset in the registry to the current - * MacOS display. (Can be 0 when not detected) */ - unsigned long dispDeviceRegEntryOffset; - - /* Optional pointer to boot ramdisk (offset from this structure) */ - unsigned long ramDisk; - unsigned long ramDiskSize; /* size of ramdisk image */ - - /* Kernel command line arguments (offset from this structure) */ - unsigned long kernelParamsOffset; - + /* Version of this structure */ + __u32 version; + /* backward compatible down to version: */ + __u32 compatible_version; + + /* NEW (vers. 2) this holds the current _logical_ base addr of + the frame buffer (for use by early boot message) */ + __u8* logicalDisplayBase; + + /* NEW (vers. 4) Apple's machine identification */ + __u32 machineID; + + /* NEW (vers. 4) Detected hw architecture */ + __u32 architecture; + + /* The device tree (internal addresses relative to the beginning of the tree, + * device tree offset relative to the beginning of this structure). + * On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this + * field is 0. + */ + __u32 deviceTreeOffset; /* Device tree offset */ + __u32 deviceTreeSize; /* Size of the device tree */ + + /* Some infos about the current MacOS display */ + __u32 dispDeviceRect[4]; /* left,top,right,bottom */ + __u32 dispDeviceDepth; /* (8, 16 or 32) */ + __u8* dispDeviceBase; /* base address (physical) */ + __u32 dispDeviceRowBytes; /* rowbytes (in bytes) */ + __u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */ + /* Optional offset in the registry to the current + * MacOS display. (Can be 0 when not detected) */ + __u32 dispDeviceRegEntryOffset; + + /* Optional pointer to boot ramdisk (offset from this structure) */ + __u32 ramDisk; + __u32 ramDiskSize; /* size of ramdisk image */ + + /* Kernel command line arguments (offset from this structure) */ + __u32 kernelParamsOffset; + + /* ALL BELOW NEW (vers. 4) */ + + /* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag + (non-PCI) only. On PCI, memory is contiguous and it's size is in the + device-tree. */ + boot_info_map_entry_t + physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */ + __u32 physMemoryMapSize; /* How many entries in map */ + + + /* The framebuffer size (optional, currently 0) */ + __u32 frameBufferSize; /* Represents a max size, can be 0. */ + + /* NEW (vers. 5) */ + + /* Total params size (args + colormap + device tree + ramdisk) */ + __u32 totalParamsSize; + } boot_infos_t; /* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented * by 3 short words containing a 16 bits (unsigned) color component. * Later versions may contain the gamma table for direct-color devices here. */ -#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) +#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) #ifdef macintosh #pragma options align=reset #endif #endif - +
\ No newline at end of file diff --git a/include/asm-ppc/bseip.h b/include/asm-ppc/bseip.h new file mode 100644 index 000000000..af657c36e --- /dev/null +++ b/include/asm-ppc/bseip.h @@ -0,0 +1,41 @@ + +/* + * A collection of structures, addresses, and values associated with + * the Bright Star Engineering ip-Engine board. Copied from the MBX stuff. + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ +#ifndef __MACH_BSEIP_DEFS +#define __MACH_BSEIP_DEFS + +/* A Board Information structure that is given to a program when + * prom starts it up. + */ +typedef struct bd_info { + unsigned int bi_memstart; /* Memory start address */ + unsigned int bi_memsize; /* Memory (end) size in bytes */ + unsigned int bi_intfreq; /* Internal Freq, in Hz */ + unsigned int bi_busfreq; /* Bus Freq, in Hz */ + unsigned char bi_enetaddr[6]; + unsigned int bi_baudrate; +} bd_t; + +extern bd_t m8xx_board_info; + +/* Memory map is configured by the PROM startup. + * All we need to get started is the IMMR. + */ +#define IMAP_ADDR ((uint)0xff000000) +#define IMAP_SIZE ((uint)(64 * 1024)) +#define PCMCIA_MEM_ADDR ((uint)0x04000000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_bseip) + +#endif diff --git a/include/asm-ppc/cuda.h b/include/asm-ppc/cuda.h deleted file mode 100644 index 39506f64a..000000000 --- a/include/asm-ppc/cuda.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Definitions for talking to the CUDA. The CUDA is a microcontroller - * which controls the ADB, system power, RTC, and various other things. - * - * Copyright (C) 1996 Paul Mackerras. - */ - -/* CUDA commands (2nd byte) */ -#define CUDA_WARM_START 0 -#define CUDA_AUTOPOLL 1 -#define CUDA_GET_6805_ADDR 2 -#define CUDA_GET_TIME 3 -#define CUDA_GET_PRAM 7 -#define CUDA_SET_6805_ADDR 8 -#define CUDA_SET_TIME 9 -#define CUDA_POWERDOWN 0xa -#define CUDA_POWERUP_TIME 0xb -#define CUDA_SET_PRAM 0xc -#define CUDA_MS_RESET 0xd -#define CUDA_SEND_DFAC 0xe -#define CUDA_RESET_SYSTEM 0x11 -#define CUDA_SET_IPL 0x12 -#define CUDA_SET_AUTO_RATE 0x14 -#define CUDA_GET_AUTO_RATE 0x16 -#define CUDA_SET_DEVICE_LIST 0x19 -#define CUDA_GET_DEVICE_LIST 0x1a -#define CUDA_GET_SET_IIC 0x22 - -#ifdef __KERNEL__ - -void find_via_cuda(void); -void via_cuda_init(void); -int cuda_request(struct adb_request *req, - void (*done)(struct adb_request *), int nbytes, ...); -void cuda_poll(void); -int cuda_present(void); - -#endif /* __KERNEL */ diff --git a/include/asm-ppc/feature.h b/include/asm-ppc/feature.h index 28a31d945..07b10e8bc 100644 --- a/include/asm-ppc/feature.h +++ b/include/asm-ppc/feature.h @@ -36,6 +36,8 @@ enum system_feature { FEATURE_BMac_reset, FEATURE_BMac_IO_enable, FEATURE_Modem_Reset, + FEATURE_IDE_DiskPower, + FEATURE_IDE_Reset, FEATURE_last, }; diff --git a/include/asm-ppc/ide.h b/include/asm-ppc/ide.h index fffe270cb..8b50f862b 100644 --- a/include/asm-ppc/ide.h +++ b/include/asm-ppc/ide.h @@ -178,7 +178,11 @@ typedef union { /* * The following are not needed for the non-m68k ports */ +#ifdef CONFIG_APUS +#define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1) +#else #define ide_ack_intr(hwif) (1) +#endif #define ide_release_lock(lock) do {} while (0) #define ide_get_lock(lock, hdlr, data) do {} while (0) diff --git a/include/asm-ppc/init.h b/include/asm-ppc/init.h index beeb4baf9..106e57c1a 100644 --- a/include/asm-ppc/init.h +++ b/include/asm-ppc/init.h @@ -11,7 +11,7 @@ __argpmac #define __prep __attribute__ ((__section__ (".text.prep"))) -#define __prepdata /* __attribute__ ((__section__ (".data.prep")))*/ +#define __prepdata __attribute__ ((__section__ (".data.prep"))) #define __prepfunc(__argprep) \ __argprep __prep; \ __argprep diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 53455fe2f..fd8f1879c 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -19,11 +19,9 @@ #define PREP_ISA_MEM_BASE 0xc0000000 #define PREP_PCI_DRAM_OFFSET 0x80000000 -#ifdef CONFIG_MBX -#define _IO_BASE 0x80000000 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0x80000000 -#else /* CONFIG_MBX8xx */ +#ifdef CONFIG_8xx +#include <asm/mpc8xx.h> +#else #ifdef CONFIG_APUS #define _IO_BASE 0 #define _ISA_MEM_BASE 0 @@ -36,7 +34,7 @@ extern unsigned long pci_dram_offset; #define _ISA_MEM_BASE isa_mem_base #define PCI_DRAM_OFFSET pci_dram_offset #endif /* CONFIG_APUS */ -#endif /* CONFIG_MBX8xx */ +#endif /* CONFIG_8xx */ #define readb(addr) in_8((volatile unsigned char *)(addr)) #define writeb(b,addr) out_8((volatile unsigned char *)(addr), (b)) diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index 088468abe..40b372fe2 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -59,27 +59,42 @@ static __inline__ int irq_cannonicalize(int irq) * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. * There are eight external interrupts (IRQs) that can be configured * as either level or edge sensitive. - * On the MBX implementation, there is also the possibility of an 8259 + * + * The 82xx can have up to 64 interrupts on the internal controller. + * + * On some implementations, there is also the possibility of an 8259 * through the PCI and PCI-ISA bridges. */ -#define NR_IRQS (16+16) /* 8259 has 16, too -- Cort */ - -#define SIU_IRQ0 (0+16) /* Highest priority */ -#define SIU_LEVEL0 (1+16) -#define SIU_IRQ1 (2+16) -#define SIU_LEVEL1 (3+16) -#define SIU_IRQ2 (4+16) -#define SIU_LEVEL2 (5+16) -#define SIU_IRQ3 (6+16) -#define SIU_LEVEL3 (7+16) -#define SIU_IRQ4 (8+16) -#define SIU_LEVEL4 (9+16) -#define SIU_IRQ5 (10+16) -#define SIU_LEVEL5 (11+16) -#define SIU_IRQ6 (12+16) -#define SIU_LEVEL6 (13+16) -#define SIU_IRQ7 (14+16) -#define SIU_LEVEL7 (15+16) +#ifdef CONFIG_82xx +#define NR_SIU_INTS 64 +#else +#define NR_SIU_INTS 16 +#endif + +#define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) + +/* These values must be zero-based and map 1:1 with the SIU configuration. + * They are used throughout the 8xx/82xx I/O subsystem to generate + * interrupt masks, flags, and other control patterns. This is why the + * current kernel assumption of the 8259 as the base controller is such + * a pain in the butt. + */ +#define SIU_IRQ0 (0) /* Highest priority */ +#define SIU_LEVEL0 (1) +#define SIU_IRQ1 (2) +#define SIU_LEVEL1 (3) +#define SIU_IRQ2 (4) +#define SIU_LEVEL2 (5) +#define SIU_IRQ3 (6) +#define SIU_LEVEL3 (7) +#define SIU_IRQ4 (8) +#define SIU_LEVEL4 (9) +#define SIU_IRQ5 (10) +#define SIU_LEVEL5 (11) +#define SIU_IRQ6 (12) +#define SIU_LEVEL6 (13) +#define SIU_IRQ7 (14) +#define SIU_LEVEL7 (15) /* The internal interrupts we can configure as we see fit. * My personal preference is CPM at level 2, which puts it above the @@ -95,21 +110,11 @@ static __inline__ int irq_cannonicalize(int irq) */ #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) -#ifdef CONFIG_MBX -/* These are defined (and fixed) by the MBX hardware implementation.*/ -#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ -#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ -#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ -#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ -#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ -#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ -#endif /* CONFIG_MBX */ - -#ifdef CONFIG_FADS -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ -#endif +/* Now include the board configuration specific associations. +*/ +#include <asm/mpc8xx.h> -/* always the same on MBX -- Cort */ +/* always the same on 8xx -- Cort */ static __inline__ int irq_cannonicalize(int irq) { return irq; diff --git a/include/asm-ppc/irq_control.h b/include/asm-ppc/irq_control.h index 022cee7cc..6bb85f0f0 100644 --- a/include/asm-ppc/irq_control.h +++ b/include/asm-ppc/irq_control.h @@ -1,5 +1,5 @@ /* - * $Id: irq_control.h,v 1.2 1999/07/17 20:23:58 cort Exp $ + * $Id: irq_control.h,v 1.8 1999/09/15 23:58:48 cort Exp $ * * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> */ @@ -11,74 +11,52 @@ #include <asm/irq.h> #include <asm/atomic.h> -extern void do_lost_interrupts(unsigned long); -extern atomic_t ppc_n_lost_interrupts; - -#define __no_use_save_flags(flags) \ - ({__asm__ __volatile__ ("mfmsr %0" : "=r" ((flags)) : : "memory"); }) - -extern __inline__ void __no_use_restore_flags(unsigned long flags) -{ - if ((flags & MSR_EE) && atomic_read(&ppc_n_lost_interrupts) != 0) { - do_lost_interrupts(flags); - } else { - __asm__ __volatile__ ("sync; mtmsr %0; isync" - : : "r" (flags) : "memory"); - } -} - -extern __inline__ void __no_use_sti(void) -{ - unsigned long flags; - - __asm__ __volatile__ ("mfmsr %0": "=r" (flags)); - flags |= MSR_EE; - if ( atomic_read(&ppc_n_lost_interrupts) ) - do_lost_interrupts(flags); - __asm__ __volatile__ ("sync; mtmsr %0; isync":: "r" (flags)); -} - -extern __inline__ void __no_use_cli(void) +/* Structure describing interrupts */ +struct hw_interrupt_type { + const char * typename; + void (*startup)(unsigned int irq); + void (*shutdown)(unsigned int irq); + void (*enable)(unsigned int irq); + void (*disable)(unsigned int irq); + void (*mask_and_ack)(unsigned int irq); + int irq_offset; +}; + +struct irqdesc { + struct irqaction *action; + struct hw_interrupt_type *ctl; +}; + +extern struct irqdesc irq_desc[NR_IRQS]; + +struct int_control_struct { - unsigned long flags; - __asm__ __volatile__ ("mfmsr %0": "=r" (flags)); - flags &= ~MSR_EE; - __asm__ __volatile__ ("sync; mtmsr %0; isync":: "r" (flags)); -} + void (*int_cli)(void); + void (*int_sti)(void); + void (*int_restore_flags)(unsigned long); + void (*int_save_flags)(unsigned long *); +}; +extern struct int_control_struct int_control; +extern unsigned long timer_interrupt_intercept; +extern unsigned long do_IRQ_intercept; +void timer_interrupt(struct pt_regs *); + +extern void __no_use_sti(void); +extern void __no_use_cli(void); +extern void __no_use_restore_flags(unsigned long); +extern void __no_use_save_flags(unsigned long *); + +#define __cli() int_control.int_cli() +#define __sti() int_control.int_sti() +#define __save_flags(flags) int_control.int_save_flags(&flags) +#define __restore_flags(flags) int_control.int_restore_flags(flags) +#define __save_and_cli(flags) ({__save_flags(flags);__cli();}) -#define __no_use_mask_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->disable) irq_desc[irq].ctl->disable(irq);}) -#define __no_use_unmask_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->enable) irq_desc[irq].ctl->enable(irq);}) -#define __no_use_mask_and_ack_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->mask_and_ack) irq_desc[irq].ctl->mask_and_ack(irq);}) - -#ifdef CONFIG_RTL - -/* the rtl system provides these -- Cort */ -extern void __sti(void); -extern void __cli(void); -extern void __restore_flags(unsigned int); -extern unsigned int __return_flags(void); -#define __save_flags(flags) (flags = __return_flags()) - -#define rtl_hard_cli __no_use_cli -#define rtl_hard_sti __no_use_sti -#define rtl_hard_save_flags(flags) __no_use_save_flags(flags) -#define rtl_hard_restore_flags(flags) __no_use_restore_flags(flags) - -#define rtl_hard_mask_irq(irq) __no_use_mask_irq(irq) -#define rtl_hard_unmask_irq(irq) __no_use_unmask_irq(irq) -#define rtl_hard_mask_and_ack_irq(irq) __no_use_mask_and_ack_irq(irq) - -#else /* CONFIG_RTL */ - -#define __cli __no_use_cli -#define __sti __no_use_sti -#define __save_flags(flags) __no_use_save_flags(flags) -#define __restore_flags(flags) __no_use_restore_flags(flags) - -#define mask_irq(irq) __no_use_mask_irq(irq) -#define unmask_irq(irq) __no_use_unmask_irq(irq) -#define mask_and_ack_irq(irq) __no_use_mask_and_ack_irq(irq) +extern void do_lost_interrupts(unsigned long); +extern atomic_t ppc_n_lost_interrupts; -#endif /* CONFIG_RTL */ +#define mask_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->disable) irq_desc[irq].ctl->disable(irq);}) +#define unmask_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->enable) irq_desc[irq].ctl->enable(irq);}) +#define mask_and_ack_irq(irq) ({if (irq_desc[irq].ctl && irq_desc[irq].ctl->mask_and_ack) irq_desc[irq].ctl->mask_and_ack(irq);}) #endif /* _PPC_IRQ_CONTROL_H */ diff --git a/include/asm-ppc/keyboard.h b/include/asm-ppc/keyboard.h index b868fe20b..01f470377 100644 --- a/include/asm-ppc/keyboard.h +++ b/include/asm-ppc/keyboard.h @@ -16,11 +16,8 @@ #ifdef __KERNEL__ #include <linux/config.h> -#include <asm/adb.h> +#include <linux/adb.h> #include <asm/machdep.h> -#ifdef CONFIG_APUS -#include <asm-m68k/keyboard.h> -#else #define KEYBOARD_IRQ 1 #define DISABLE_KBD_DURING_INTERRUPTS 0 @@ -75,8 +72,6 @@ static inline void kbd_init_hw(void) extern unsigned long SYSRQ_KEY; -#endif /* CONFIG_APUS */ - #endif /* __KERNEL__ */ #endif /* __ASMPPC_KEYBOARD_H */ diff --git a/include/asm-ppc/linux_logo.h b/include/asm-ppc/linux_logo.h index 09bf34089..199d0dc2c 100644 --- a/include/asm-ppc/linux_logo.h +++ b/include/asm-ppc/linux_logo.h @@ -12,14 +12,6 @@ */ #include <linux/config.h> -#ifdef CONFIG_APUS -#include <asm-m68k/linux_logo.h> - -#undef linux_logo_banner -#define linux_logo_banner "Linux/PPC version " UTS_RELEASE - -#else - #include <linux/init.h> #define linux_logo_banner "Linux/PPC version " UTS_RELEASE @@ -48,4 +40,3 @@ extern unsigned char linux_logo16_blue[]; extern unsigned char linux_logo16[]; #endif -#endif /* CONFIG_APUS */ diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h index cd1dbe294..6f85554ca 100644 --- a/include/asm-ppc/machdep.h +++ b/include/asm-ppc/machdep.h @@ -9,6 +9,7 @@ #endif struct pt_regs; +struct pci_bus; struct machdep_calls { void (*setup_arch)(unsigned long * memory_start_p, @@ -20,8 +21,9 @@ struct machdep_calls { /* Optional, may be NULL. */ unsigned int (*irq_cannonicalize)(unsigned int irq); void (*init_IRQ)(void); - void (*do_IRQ)(struct pt_regs *regs, int cpu, int isfake); - + int (*get_irq)(struct pt_regs *); + void (*post_irq)( int ); + /* A general init function, called by ppc_init in init/main.c. May be NULL. */ void (*init)(void); @@ -72,8 +74,9 @@ struct machdep_calls { int (*pcibios_write_config_dword)(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned int val); void (*pcibios_fixup)(void); -struct pci_bus; void (*pcibios_fixup_bus)(struct pci_bus *); + /* this is for modules, since _machine can be a define -- Cort */ + int ppc_machine; }; extern struct machdep_calls ppc_md; @@ -89,7 +92,7 @@ struct boot_info unsigned long magic_start; char cmd_line[256]; char boot_loader[128]; - int _machine; + int _machine_type; unsigned long initrd_start, initrd_size; unsigned long systemmap_start, systemmap_size; unsigned long prom_entry; @@ -97,4 +100,14 @@ struct boot_info unsigned long magic_end; }; struct boot_info *binfo; + +/* + * Power macintoshes have either a CUDA or a PMU controlling + * system reset, power, NVRAM, RTC. + */ +enum sys_ctrler_kind { + SYS_CTRLER_CUDA = 1, + SYS_CTRLER_PMU = 2, +} sys_ctrler; + #endif /* _PPC_MACHDEP_H */ diff --git a/include/asm-ppc/mbx.h b/include/asm-ppc/mbx.h index 1d8d91039..e67e0344f 100644 --- a/include/asm-ppc/mbx.h +++ b/include/asm-ppc/mbx.h @@ -39,9 +39,10 @@ typedef struct bd_info { * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI * Bridge CSRs 1:1 into the kernel address space. */ -#define PCI_ISA_IO_ADDR ((uint)0x80000000) +#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) #define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) -#define PCI_ISA_MEM_ADDR ((uint)0xc0000000) +#define PCI_IDE_ADDR ((unsigned)0x81000000) +#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) #define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) #define PCMCIA_MEM_ADDR ((uint)0xe0000000) #define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024)) @@ -59,4 +60,29 @@ typedef struct bd_info { #define IMAP_SIZE ((uint)(64 * 1024)) #define PCI_CSR_ADDR ((uint)0xfa210000) #define PCI_CSR_SIZE ((uint)(64 * 1024)) + +/* Map additional physical space into well known virtual addresses. Due + * to virtual address mapping, these physical addresses are not accessible + * in a 1:1 virtual to physical mapping. + */ +#define ISA_IO_VIRT_ADDR ((uint)0xfa220000) +#define ISA_IO_VIRT_SIZE ((uint)64 * 1024) + +/* Interrupt assignments. + * These are defined (and fixed) by the MBX hardware implementation. + */ +#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ +#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ +#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ +#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ +#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ +#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ + +/* The MBX uses the 8259. +*/ +#define NR_8259_INTS 16 + +/* Generic 8xx type +*/ +#define _MACH_8xx (_MACH_mbx) #endif diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h new file mode 100644 index 000000000..656d3d60e --- /dev/null +++ b/include/asm-ppc/mpc8xx.h @@ -0,0 +1,71 @@ + +/* This is the single file included by all MPC8xx build options. + * Since there are many different boards and no standard configuration, + * we have a unique include file for each. Rather than change every + * file that has to include MPC8xx configuration, they all include + * this one and the configuration switching is done here. + */ +#ifndef __CONFIG_8xx_DEFS +#define __CONFIG_8xx_DEFS + +#ifdef CONFIG_8xx + +#ifdef CONFIG_MBX +#include <asm/mbx.h> +#endif + +#ifdef CONFIG_FADS +#include <asm/fads.h> +#endif + +#ifdef CONFIG_RPXLITE +#include <asm/rpxlite.h> +#endif + +#ifdef CONFIG_BSEIP +#include <asm/bseip.h> +#endif + +#ifdef CONFIG_RPXCLASSIC +#include <asm/rpxclassic.h> +#endif + +/* I need this to get pt_regs....... +*/ +#include <asm/ptrace.h> + +/* Currently, all 8xx boards that support a processor to PCI/ISA bridge + * use the same memory map. + */ +#if 0 +#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR) +#define _IO_BASE PCI_ISA_IO_ADDR +#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR +#define PCI_DRAM_OFFSET 0x80000000 +#else +#define _IO_BASE 0 +#define _ISA_MEM_BASE 0 +#define PCI_DRAM_OFFSET 0 +#endif +#else +#define _IO_BASE 0 +#define _ISA_MEM_BASE 0 +#define PCI_DRAM_OFFSET 0 +#endif + +extern unsigned long isa_io_base; +extern unsigned long isa_mem_base; +extern unsigned long pci_dram_offset; + +/* The "residual" data board information structure the boot loader + * hands to us. + */ +extern unsigned char __res[]; + +extern int request_8xxirq(unsigned int irq, + void (*handler)(int, void *, struct pt_regs *), + unsigned long flags, + const char *device, + void *dev_id); +#endif /* CONFIG_8xx */ +#endif diff --git a/include/asm-ppc/ohare.h b/include/asm-ppc/ohare.h index c022e5034..ffc4ef10b 100644 --- a/include/asm-ppc/ohare.h +++ b/include/asm-ppc/ohare.h @@ -18,7 +18,9 @@ #define OH_BAY_IDE_ENABLE 8 #define OH_BAY_FLOPPY_ENABLE 0x10 #define OH_IDE_ENABLE 0x20 +#define OH_IDE_POWER 0x40 /* a guess */ #define OH_BAY_ENABLE 0x80 +#define OH_IDE_RESET 0x100 /* 0-based, a guess */ #define OH_SCC_ENABLE 0x200 #define OH_MESH_ENABLE 0x400 #define OH_FLOPPY_ENABLE 0x800 diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index ebb5fd934..3a822590b 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -9,11 +9,28 @@ #include <asm/mmu.h> #include <asm/page.h> +#ifndef CONFIG_8xx extern void local_flush_tlb_all(void); extern void local_flush_tlb_mm(struct mm_struct *mm); extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end); +#else /* CONFIG_8xx */ +#define __tlbia() asm volatile ("tlbia" : : ) + +extern inline void local_flush_tlb_all(void) + { __tlbia(); } +extern inline void local_flush_tlb_mm(struct mm_struct *mm) + { __tlbia(); } +extern inline void local_flush_tlb_page(struct vm_area_struct *vma, + unsigned long vmaddr) + { __tlbia(); } +extern inline void local_flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) + { __tlbia(); } +extern inline void flush_hash_page(unsigned context, unsigned long va) + { } +#endif #define flush_tlb_all local_flush_tlb_all #define flush_tlb_mm local_flush_tlb_mm @@ -636,22 +653,6 @@ extern void kernel_set_cachemode (unsigned long address, unsigned long size, #define io_remap_page_range remap_page_range -#ifdef CONFIG_8xx -#define __tlbia() asm volatile ("tlbia" : : ) - -extern inline void local_flush_tlb_all(void) - { __tlbia(); } -extern inline void local_flush_tlb_mm(struct mm_struct *mm) - { __tlbia(); } -extern inline void local_flush_tlb_page(struct vm_area_struct *vma, - unsigned long vmaddr) - { __tlbia(); } -extern inline void local_flush_tlb_range(struct mm_struct *mm, - unsigned long start, unsigned long end) - { __tlbia(); } -extern inline void flush_hash_page(unsigned context, unsigned long va) - { } -#endif #endif __ASSEMBLY__ #endif /* _PPC_PGTABLE_H */ diff --git a/include/asm-ppc/pmu.h b/include/asm-ppc/pmu.h deleted file mode 100644 index f6309d6b2..000000000 --- a/include/asm-ppc/pmu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Definitions for talking to the PMU. The PMU is a microcontroller - * which controls battery charging and system power on PowerBook 3400 - * and 2400 models as well as the RTC and various other things. - * - * Copyright (C) 1998 Paul Mackerras. - */ - -/* - * PMU commands - */ -#define PMU_POWER_CTRL 0x11 /* control power of some devices */ -#define PMU_ADB_CMD 0x20 /* send ADB packet */ -#define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */ -#define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */ -#define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */ -#define PMU_SET_RTC 0x30 /* set real-time clock */ -#define PMU_READ_RTC 0x38 /* read real-time clock */ -#define PMU_SET_VOLBUTTON 0x40 /* set volume up/down position */ -#define PMU_BACKLIGHT_BRIGHT 0x41 /* set backlight brightness */ -#define PMU_GET_VOLBUTTON 0x48 /* get volume up/down position */ -#define PMU_PCEJECT 0x4c /* eject PC-card from slot */ -#define PMU_BATTERY_STATE 0x6b /* report battery state etc. */ -#define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */ -#define PMU_INT_ACK 0x78 /* read interrupt bits */ -#define PMU_SHUTDOWN 0x7e /* turn power off */ -#define PMU_SLEEP 0x7f /* put CPU to sleep */ -#define PMU_RESET 0xd0 /* reset CPU */ -#define PMU_GET_BRIGHTBUTTON 0xd9 /* report brightness up/down pos */ -#define PMU_GET_COVER 0xdc /* report cover open/closed */ - -/* Bits to use with the PMU_POWER_CTRL command */ -#define PMU_POW_ON 0x80 /* OR this to power ON the device */ -#define PMU_POW_OFF 0x00 /* leave bit 7 to 0 to power it OFF */ -#define PMU_POW_BACKLIGHT 0x01 /* backlight power */ -#define PMU_POW_IRLED 0x04 /* IR led power (on wallstreet) ??? */ - -/* Bits in PMU interrupt and interrupt mask bytes */ -#define PMU_INT_ADB_AUTO 0x04 /* ADB autopoll, when PMU_INT_ADB */ -#define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */ -#define PMU_INT_SNDBRT 0x08 /* sound/brightness up/down buttons */ -#define PMU_INT_ADB 0x10 /* ADB autopoll or reply data */ -#define PMU_INT_TICK 0x80 /* 1-second tick interrupt */ - -/* Kind of PMU (model) */ -enum { - PMU_UNKNOWN, - PMU_OHARE_BASED, - PMU_HEATHROW_BASED -}; - -/* - * Ioctl commands for the /dev/pmu device - */ -#include <linux/ioctl.h> - -/* no param */ -#define PMU_IOC_SLEEP _IO('B', 0) -/* out param: u32* backlight value: 0 to 31 */ -#define PMU_IOC_GET_BACKLIGHT _IOR('B', 1, sizeof(__u32*)) -/* in param: u32 backlight value: 0 to 31 */ -#define PMU_IOC_SET_BACKLIGHT _IOW('B', 2, sizeof(__u32)) -/* out param: u32* backlight value: 0 to 31 */ -#define PMU_IOC_GET_MODEL _IOR('B', 3, sizeof(__u32*)) - -#ifdef __KERNEL__ - -void find_via_pmu(void); -void via_pmu_init(void); - -int pmu_request(struct adb_request *req, - void (*done)(struct adb_request *), int nbytes, ...); -void pmu_poll(void); - -void pmu_enable_backlight(int on); -void pmu_set_brightness(int level); - -void pmu_enable_irled(int on); - -void pmu_restart(void); -void pmu_shutdown(void); - -int pmu_present(void); -int pmu_get_model(void); - -/* - * Stuff for putting the powerbook to sleep and waking it again. - */ -#include <linux/notifier.h> - -extern struct notifier_block *sleep_notifier_list; - -/* code values for calling sleep/wakeup handlers */ -#define PBOOK_SLEEP 1 -#define PBOOK_WAKE 2 - -#endif /* __KERNEL */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 53096182c..974f78a47 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -34,7 +34,7 @@ #define MSR_RI (1<<1) /* Recoverable Exception */ #define MSR_LE (1<<0) /* Little-Endian enable */ -#ifdef CONFIG_APUS +#ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI #else #define MSR_ MSR_ME|MSR_RI @@ -104,6 +104,7 @@ #define _MACH_bseip 128 /* Bright Star Engineering ip-Engine */ #define _MACH_yk 256 /* Motorola Yellowknife */ #define _MACH_gemini 512 /* Synergy Microsystems gemini board */ +#define _MACH_classic 1024 /* RPCG RPX-Classic 8xx board */ /* see residual.h for these */ #define _PREP_Motorola 0x01 /* motorola prep */ @@ -212,13 +213,12 @@ n: #define SR15 15 #ifndef __ASSEMBLY__ +#ifndef CONFIG_MACH_SPECIFIC extern int _machine; - -/* Temporary hacks until we can clean things up better - Corey */ extern int have_of; -extern int is_prep; extern int is_chrp; extern int is_powerplus; +#endif /* CONFIG_MACH_SPECIFIC */ /* what kind of prep workstation we are */ extern int _prep_type; @@ -331,5 +331,28 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #endif /* ndef ASSEMBLY*/ - +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_PREP) +#define _machine _MACH_prep +#define have_of 0 +#elif defined(CONFIG_CHRP) +#define _machine _MACH_chrp +#define have_of 1 +#elif defined(CONFIG_PMAC) +#define _machine _MACH_Pmac +#define have_of 1 +#elif defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + #endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h index 018da94fd..2acd7b45a 100644 --- a/include/asm-ppc/prom.h +++ b/include/asm-ppc/prom.h @@ -65,6 +65,7 @@ typedef void (*prom_entry)(struct prom_args *); extern void abort(void); extern void prom_init(int, int, prom_entry); extern void prom_print(const char *msg); +extern void relocate_nodes(void); extern void finish_device_tree(void); extern struct device_node *find_devices(const char *name); extern struct device_node *find_type_devices(const char *type); @@ -72,7 +73,8 @@ extern struct device_node *find_path_device(const char *path); extern struct device_node *find_compatible_devices(const char *type, const char *compat); extern struct device_node *find_phandle(phandle); -extern int device_is_compatible(struct device_node *device, const char* compat); +extern int device_is_compatible(struct device_node *device, const char *); +extern int machine_is_compatible(const char *compat); extern unsigned char *get_property(struct device_node *node, const char *name, int *lenp); extern void print_properties(struct device_node *node); diff --git a/include/asm-ppc/rpxclassic.h b/include/asm-ppc/rpxclassic.h new file mode 100644 index 000000000..fd733b38e --- /dev/null +++ b/include/asm-ppc/rpxclassic.h @@ -0,0 +1,67 @@ + +/* + * A collection of structures, addresses, and values associated with + * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff. + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ +#ifndef __MACH_RPX_DEFS +#define __MACH_RPX_DEFS + +/* A Board Information structure that is given to a program when + * prom starts it up. + */ +typedef struct bd_info { + unsigned int bi_memstart; /* Memory start address */ + unsigned int bi_memsize; /* Memory (end) size in bytes */ + unsigned int bi_intfreq; /* Internal Freq, in Hz */ + unsigned int bi_busfreq; /* Bus Freq, in Hz */ + unsigned char bi_enetaddr[6]; + unsigned int bi_baudrate; +} bd_t; + +extern bd_t m8xx_board_info; + +/* Memory map is configured by the PROM startup. + * We just map a few things we need. The CSR is actually 4 byte-wide + * registers that can be accessed as 8-, 16-, or 32-bit values. + */ +#define PCMCIA_MEM_ADDR ((uint)0x04000000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) +#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) +#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) +#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) +#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) +#define RPX_CSR_ADDR ((uint)0xfa400000) +#define RPX_CSR_SIZE ((uint)(4 * 1024)) +#define IMAP_ADDR ((uint)0xfa200000) +#define IMAP_SIZE ((uint)(64 * 1024)) +#define PCI_CSR_ADDR ((uint)0x80000000) +#define PCI_CSR_SIZE ((uint)(64 * 1024)) + +/* Things of interest in the CSR. +*/ +#define BCSR0_ETHEN ((uint)0x80000000) +#define BCSR0_ETHLPBK ((uint)0x40000000) +#define BCSR0_COLTESTDIS ((uint)0x20000000) +#define BCSR0_FULLDPLXDIS ((uint)0x10000000) +#define BCSR0_ENFLSHSEL ((uint)0x04000000) +#define BCSR0_FLASH_SEL ((uint)0x02000000) +#define BCSR0_ENMONXCVR ((uint)0x01000000) + +#define BCSR2_EN232XCVR ((uint)0x00008000) +#define BCSR2_QSPACESEL ((uint)0x00004000) + +/* Interrupt level assignments. +*/ +#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_rpxclassic) + +#endif diff --git a/include/asm-ppc/rpxlite.h b/include/asm-ppc/rpxlite.h new file mode 100644 index 000000000..c0cc7e0a6 --- /dev/null +++ b/include/asm-ppc/rpxlite.h @@ -0,0 +1,67 @@ + +/* + * A collection of structures, addresses, and values associated with + * the RPCG RPX-Lite board. Copied from the MBX stuff. + * + * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) + */ +#ifndef __MACH_RPX_DEFS +#define __MACH_RPX_DEFS + +/* A Board Information structure that is given to a program when + * prom starts it up. + */ +typedef struct bd_info { + unsigned int bi_memstart; /* Memory start address */ + unsigned int bi_memsize; /* Memory (end) size in bytes */ + unsigned int bi_intfreq; /* Internal Freq, in Hz */ + unsigned int bi_busfreq; /* Bus Freq, in Hz */ + unsigned char bi_enetaddr[6]; + unsigned int bi_baudrate; +} bd_t; + +extern bd_t m8xx_board_info; + +/* Memory map is configured by the PROM startup. + * We just map a few things we need. The CSR is actually 4 byte-wide + * registers that can be accessed as 8-, 16-, or 32-bit values. + */ +#define RPX_CSR_ADDR ((uint)0xfa400000) +#define RPX_CSR_SIZE ((uint)(4 * 1024)) +#define IMAP_ADDR ((uint)0xfa200000) +#define IMAP_SIZE ((uint)(64 * 1024)) +#define HIOX_CSR_ADDR ((uint)0xfac00000) +#define HIOX_CSR_SIZE ((uint)(4 * 1024)) +#define PCMCIA_MEM_ADDR ((uint)0x04000000) +#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) +#define PCMCIA_IO_ADDR ((uint)0x04400000) +#define PCMCIA_IO_SIZE ((uint)(4 * 1024)) + +/* Things of interest in the CSR. +*/ +#define BCSR0_ETHEN ((uint)0x80000000) +#define BCSR0_ETHLPBK ((uint)0x40000000) +#define BCSR0_COLTESTDIS ((uint)0x20000000) +#define BCSR0_FULLDPLXDIS ((uint)0x10000000) +#define BCSR0_LEDOFF ((uint)0x08000000) +#define BCSR0_USBDISABLE ((uint)0x04000000) +#define BCSR0_USBHISPEED ((uint)0x02000000) +#define BCSR0_USBPWREN ((uint)0x01000000) +#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) +#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) +#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) + +/* HIO Expansion card. +*/ +#define HIOX_CSR_ENAUDIO ((uint)0x00000200) +#define HIOX_CSR_RSTAUDIO ((uint)0x00000100) /* 0 == reset */ + +/* We don't use the 8259. +*/ +#define NR_8259_INTS 0 + +/* Machine type +*/ +#define _MACH_8xx (_MACH_rpxlite) + +#endif diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index edef8a7da..61d3412b9 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -4,9 +4,6 @@ #include <linux/config.h> -#ifdef CONFIG_APUS -#include <asm-m68k/serial.h> -#else #ifdef CONFIG_GEMINI #include <asm/gemini_serial.h> #else @@ -20,20 +17,18 @@ */ #define BASE_BAUD ( 1843200 / 16 ) -#ifdef CONFIG_PMAC -/* - * Auto-probing will cause machine checks on powermacs. - */ -#define SERIAL_PORT_DFNS - #ifdef CONFIG_SERIAL_MANY_PORTS #define RS_TABLE_SIZE 64 #else #define RS_TABLE_SIZE 4 #endif -#else +#ifdef CONFIG_PMAC +/* + * Auto-probing will cause machine checks on powermacs. + */ #define SERIAL_PORT_DFNS +#else /* * PReP, CHRP, etc. */ @@ -143,4 +138,3 @@ #endif /* CONFIG_PMAC */ #endif /* CONFIG_GEMINI */ -#endif /* CONFIG_APUS */ diff --git a/include/asm-ppc/shmparam.h b/include/asm-ppc/shmparam.h index 754af6979..3ece6775b 100644 --- a/include/asm-ppc/shmparam.h +++ b/include/asm-ppc/shmparam.h @@ -33,7 +33,7 @@ * SHMMAX <= (PAGE_SIZE << _SHM_IDX_BITS). */ -#define SHMMAX 0x3fa000 /* max shared seg size (bytes) */ +#define SHMMAX 0x2000000 /* max shared seg size (bytes) */ #define SHMMIN 1 /* really PAGE_SIZE */ /* min shared seg size (bytes) */ #define SHMMNI (1<<_SHM_ID_BITS) /* max num of segs system wide */ #define SHMALL /* max shm system wide (pages) */ \ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h index eab97eea9..d2df19224 100644 --- a/include/asm-ppc/smp.h +++ b/include/asm-ppc/smp.h @@ -21,7 +21,6 @@ struct cpuinfo_PPC { }; extern struct cpuinfo_PPC cpu_data[NR_CPUS]; -extern int first_cpu_booted; extern unsigned long smp_proc_in_lock[NR_CPUS]; extern void smp_message_pass(int target, int msg, unsigned long data, int wait); diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h index 327b4927a..ad1fdda17 100644 --- a/include/asm-ppc/spinlock.h +++ b/include/asm-ppc/spinlock.h @@ -1,10 +1,8 @@ #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H -/* Simple spin lock operations. There are two variants, one clears IRQ's - * on the local processor, one does not. - * - * We make no fairness assumptions. They have a cost. +/* + * Simple spin lock operations. */ typedef struct { @@ -24,19 +22,6 @@ extern int spin_trylock(spinlock_t *lock); #define spin_lock(lp) _spin_lock(lp) #define spin_unlock(lp) _spin_unlock(lp) -#define spin_lock_irq(lock) \ - do { __cli(); spin_lock(lock); } while (0) -#define spin_lock_bh(___lk) do { local_bh_disable(); spin_lock(___lk); } while(0) - -#define spin_unlock_irq(lock) \ - do { spin_unlock(lock); __sti(); } while (0) -#define spin_unlock_bh(___lk) do { spin_unlock(___lk); local_bh_enable(); } while(0) - -#define spin_lock_irqsave(lock, flags) \ - do { __save_flags(flags); __cli(); spin_lock(lock); } while (0) -#define spin_unlock_irqrestore(lock, flags) \ - do { spin_unlock(lock); __restore_flags(flags); } while (0) - extern unsigned long __spin_trylock(volatile unsigned long *lock); /* diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index 9984267dd..2bf822e33 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -1,5 +1,5 @@ /* - * $Id: system.h,v 1.48 1999/09/05 11:56:40 paulus Exp $ + * $Id: system.h,v 1.49 1999/09/11 18:37:54 cort Exp $ * * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> */ @@ -104,6 +104,11 @@ extern void __global_restore_flags(unsigned long); #endif /* !__SMP__ */ +#define local_irq_disable() __cli() +#define local_irq_enable() __sti() +#define local_irq_save(flags) __save_and_cli(flags) +#define local_irq_restore(flags) __restore_flags(flags) + #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) extern unsigned long xchg_u64(void *ptr, unsigned long val); diff --git a/include/asm-sparc/keyboard.h b/include/asm-sparc/keyboard.h index 7b1cbb0be..754537ed8 100644 --- a/include/asm-sparc/keyboard.h +++ b/include/asm-sparc/keyboard.h @@ -13,6 +13,9 @@ #ifdef __KERNEL__ +#include <linux/ioport.h> +#include <asm/io.h> + #define KEYBOARD_IRQ 13 #define DISABLE_KBD_DURING_INTERRUPTS 0 @@ -45,6 +48,31 @@ extern unsigned char pcikbd_sysrq_xlate[128]; /* #define SYSRQ_KEY 0x54 */ /* sparc64 */ #define SYSRQ_KEY 0x63 /* sparc */ +/* resource allocation */ +#define kbd_request_region() request_region(0x60, 16, "keyboard") +#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \ + "keyboard", NULL) + +/* How to access the keyboard macros on this platform. */ +#define kbd_read_input() inb(KBD_DATA_REG) +#define kbd_read_status() inb(KBD_STATUS_REG) +#define kbd_write_output(val) outb(val, KBD_DATA_REG) +#define kbd_write_command(val) outb(val, KBD_CNTL_REG) + +/* Some stoneage hardware needs delays after some operations. */ +#define kbd_pause() do { } while(0) + +/* + * Machine specific bits for the PS/2 driver + */ + +#define AUX_IRQ 12 + +#define aux_request_irq(hand, dev_id) \ + request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS/2 Mouse", dev_id) + +#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) + #endif /* __KERNEL__ */ #endif /* !(_SPARC_KEYBOARD_H) */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 98b115c13..d6521ab67 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -38,21 +38,14 @@ #define ACPI_FACP_SIG 0x50434146 /* 'FACP' */ #define ACPI_DSDT_SIG 0x54445344 /* 'DSDT' */ -/* PM1_STS flags */ -#define ACPI_TMR_STS 0x0001 -#define ACPI_BM_STS 0x0010 -#define ACPI_GBL_STS 0x0020 -#define ACPI_PWRBTN_STS 0x0100 -#define ACPI_SLPBTN_STS 0x0200 -#define ACPI_RTC_STS 0x0400 -#define ACPI_WAK_STS 0x8000 - -/* PM1_EN flags */ -#define ACPI_TMR_EN 0x0001 -#define ACPI_GBL_EN 0x0020 -#define ACPI_PWRBTN_EN 0x0100 -#define ACPI_SLPBTN_EN 0x0200 -#define ACPI_RTC_EN 0x0400 +/* PM1_STS/EN flags */ +#define ACPI_TMR 0x0001 +#define ACPI_BM 0x0010 +#define ACPI_GBL 0x0020 +#define ACPI_PWRBTN 0x0100 +#define ACPI_SLPBTN 0x0200 +#define ACPI_RTC 0x0400 +#define ACPI_WAK 0x8000 /* PM1_CNT flags */ #define ACPI_SCI_EN 0x0001 @@ -64,8 +57,12 @@ #define ACPI_SLP_EN 0x2000 /* PM_TMR masks */ -#define ACPI_TMR_VAL_MASK 0x00ffffff -#define ACPI_E_TMR_VAL_MASK 0xff000000 +#define ACPI_TMR_MASK 0x00ffffff +#define ACPI_TMR_HZ 3580000 /* 3.58 MHz */ + +/* strangess to avoid integer overflow */ +#define ACPI_uS_TO_TMR_TICKS(val) \ + (((val) * (ACPI_TMR_HZ / 10000)) / 100) /* PM2_CNT flags */ #define ACPI_ARB_DIS 0x01 @@ -146,11 +143,29 @@ struct acpi_facp { }; #define ACPI_FIND_TABLES _IOR('A', 1, struct acpi_find_tables) -#define ACPI_WAIT_EVENT _IO('A', 2) +#define ACPI_ENABLE_EVENT _IOW('A', 2, struct acpi_enable_event) +#define ACPI_WAIT_EVENT _IOR('A', 3, struct acpi_wait_event) struct acpi_find_tables { - unsigned long facp; - unsigned long dsdt; + unsigned long facp; /* FACP physical address */ + unsigned long dsdt; /* DSDT physical address */ +}; + +struct acpi_enable_event { + __u32 pm1_enable; /* fixed events */ + __u32 gpe_enable; /* general-purpose events (GPEs) */ + __u32 gpe_level; /* level-triggered GPEs */ +}; + +struct acpi_wait_event { + __u32 pm1_status; /* fixed events */ + __u32 gpe_status; /* general-purpose events */ }; +#ifdef __KERNEL__ + +extern void (*acpi_idle)(void); + +#endif + #endif /* _LINUX_ACPI_H */ diff --git a/include/linux/dcache.h b/include/linux/dcache.h index 825dfd28d..0ae06753f 100644 --- a/include/linux/dcache.h +++ b/include/linux/dcache.h @@ -131,7 +131,6 @@ extern void d_delete(struct dentry *); /* allocate/de-allocate */ extern struct dentry * d_alloc(struct dentry *, const struct qstr *); -extern void prune_dcache(int); extern void shrink_dcache_sb(struct super_block *); extern void shrink_dcache_parent(struct dentry *); extern int d_invalidate(struct dentry *); @@ -139,10 +138,12 @@ extern int d_invalidate(struct dentry *); #define shrink_dcache() prune_dcache(0) /* dcache memory management */ -extern int select_dcache(int, int); -extern void shrink_dcache_memory(int, unsigned int); -extern void check_dcache_memory(void); -extern void free_inode_memory(int); /* defined in fs/inode.c */ +extern int shrink_dcache_memory(int, unsigned int); +extern void prune_dcache(int); + +/* icache memory management (defined in linux/fs/inode.c) */ +extern int shrink_icache_memory(int, int); +extern void prune_icache(int); /* only used at mount-time */ extern struct dentry * d_alloc_root(struct inode *); diff --git a/include/linux/fb.h b/include/linux/fb.h index f7a7e2b64..fb8e0bc96 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -26,6 +26,7 @@ /* #define FBIOSWITCH_MONIBIT 0x460E */ #define FBIOGET_CON2FBMAP 0x460F #define FBIOPUT_CON2FBMAP 0x4610 +#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ #define FB_TYPE_PLANES 1 /* Non interleaved planes */ @@ -80,6 +81,8 @@ #define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ #define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ #define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ +#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ +#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */ struct fb_fix_screeninfo { char id[16]; /* identification string eg "TT Builtin" */ diff --git a/include/linux/fs.h b/include/linux/fs.h index 8667c79db..d1ee10406 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -45,7 +45,6 @@ struct poll_table_struct; #define BLOCK_SIZE (1<<BLOCK_SIZE_BITS) /* And dynamically-tunable limits and defaults: */ -extern int max_inodes; extern int max_files, nr_files, nr_free_files; extern int max_super_blocks, nr_super_blocks; @@ -270,6 +269,7 @@ void init_buffer(struct buffer_head *, bh_end_io_t *, void *); #include <linux/adfs_fs_i.h> #include <linux/qnx4_fs_i.h> #include <linux/udf_fs_i.h> +#include <linux/ncp_fs_i.h> /* * Attribute flags. These should be or-ed together to figure out what @@ -383,6 +383,7 @@ struct inode { struct adfs_inode_info adfs_i; struct qnx4_inode_info qnx4_i; struct udf_inode_info udf_i; + struct ncp_inode_info ncpfs_i; struct socket socket_i; void *generic_ip; } u; @@ -513,6 +514,7 @@ extern int fasync_helper(int, struct file *, int, struct fasync_struct **); #include <linux/adfs_fs_sb.h> #include <linux/qnx4_fs_sb.h> #include <linux/udf_fs_sb.h> +#include <linux/ncp_fs_sb.h> extern struct list_head super_blocks; @@ -558,6 +560,7 @@ struct super_block { struct adfs_sb_info adfs_sb; struct qnx4_sb_info qnx4_sb; struct udf_sb_info udf_sb; + struct ncp_sb_info ncpfs_sb; void *generic_sbp; } u; /* @@ -724,7 +727,7 @@ extern char * getname(const char *); #define __getname() ((char *) __get_free_page(GFP_KERNEL)) #define putname(name) free_page((unsigned long)(name)) -extern void kill_fasync(struct fasync_struct *, int); +extern void kill_fasync(struct fasync_struct *, int, int); extern int register_blkdev(unsigned int, const char *, struct file_operations *); extern int unregister_blkdev(unsigned int, const char *); extern int blkdev_open(struct inode *, struct file *); diff --git a/include/linux/ide.h b/include/linux/ide.h index 71bcdc98e..3ebe6c211 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h @@ -46,9 +46,6 @@ #ifndef OK_TO_RESET_CONTROLLER /* 1 needed for good error recovery */ #define OK_TO_RESET_CONTROLLER 1 /* 0 for use with AH2372A/B interface */ #endif -#ifndef FAKE_FDISK_FOR_EZDRIVE /* 1 to help linux fdisk with EZDRIVE */ -#define FAKE_FDISK_FOR_EZDRIVE 1 /* 0 to reduce kernel size */ -#endif #ifndef FANCY_STATUS_DUMPS /* 1 for human-readable drive errors */ #define FANCY_STATUS_DUMPS 1 /* 0 to reduce kernel size */ #endif @@ -262,9 +259,7 @@ typedef struct ide_drive_s { unsigned nice2 : 1; /* flag: give a share in our own bandwidth */ unsigned doorlocking : 1; /* flag: for removable only: door lock/unlock works */ unsigned autotune : 2; /* 1=autotune, 2=noautotune, 0=default */ -#if FAKE_FDISK_FOR_EZDRIVE - unsigned remap_0_to_1 : 1; /* flag: partitioned with ezdrive */ -#endif /* FAKE_FDISK_FOR_EZDRIVE */ + unsigned remap_0_to_1 : 2; /* 0=remap if ezdrive, 1=remap, 2=noremap */ unsigned ata_flash : 1; /* 1=present, 0=default */ byte media; /* disk, cdrom, tape, floppy, ... */ select_t select; /* basic drive/head select reg value */ @@ -282,8 +277,9 @@ typedef struct ide_drive_s { byte sect; /* "real" sectors per track */ byte bios_head; /* BIOS/fdisk/LILO number of heads */ byte bios_sect; /* BIOS/fdisk/LILO sectors per track */ - unsigned short bios_cyl; /* BIOS/fdisk/LILO number of cyls */ - unsigned short cyl; /* "real" number of cyls */ + unsigned int bios_cyl; /* BIOS/fdisk/LILO number of cyls */ + unsigned int cyl; /* "real" number of cyls */ + unsigned long capacity; /* total number of sectors */ unsigned int drive_data; /* for use by tuneproc/selectproc as needed */ void *hwif; /* actually (ide_hwif_t *) */ wait_queue_head_t wqueue; /* used to wait for drive in open() */ @@ -624,20 +620,18 @@ int ide_wait_stat (ide_drive_t *drive, byte good, byte bad, unsigned long timeou /* * This routine is called from the partition-table code in genhd.c * to "convert" a drive to a logical geometry with fewer than 1024 cyls. - * - * The second parameter, "xparm", determines exactly how the translation - * will be handled: - * 0 = convert to CHS with fewer than 1024 cyls - * using the same method as Ontrack DiskManager. - * 1 = same as "0", plus offset everything by 63 sectors. - * -1 = similar to "0", plus redirect sector 0 to sector 1. - * >1 = convert to a CHS geometry with "xparm" heads. - * - * Returns 0 if the translation was not possible, if the device was not - * an IDE disk drive, or if a geometry was "forced" on the commandline. - * Returns 1 if the geometry translation was successful. */ -int ide_xlate_1024 (kdev_t, int, const char *); +int ide_xlate_1024 (kdev_t, int, int, const char *); + +/* + * Convert kdev_t structure into ide_drive_t * one. + */ +ide_drive_t *get_info_ptr (kdev_t i_rdev); + +/* + * Return the current idea about the total capacity of this drive. + */ +unsigned long current_capacity (ide_drive_t *drive); /* * Start a reset operation for an IDE interface. diff --git a/include/linux/msg.h b/include/linux/msg.h index 7bfcfd084..2d42361b1 100644 --- a/include/linux/msg.h +++ b/include/linux/msg.h @@ -11,31 +11,10 @@ #define MSG_NOERROR 010000 /* no error if message is too big */ #define MSG_EXCEPT 020000 /* recv any msg except of specified type.*/ -#ifdef __KERNEL__ - -/* one msqid structure for each queue on the system */ -struct msqid_ds_kern { - struct ipc_perm msg_perm; - struct msg *msg_first; /* first message on queue */ - struct msg *msg_last; /* last message in queue */ - __kernel_time_t msg_stime; /* last msgsnd time */ - __kernel_time_t msg_rtime; /* last msgrcv time */ - __kernel_time_t msg_ctime; /* last change time */ - wait_queue_head_t wwait; - wait_queue_head_t rwait; - unsigned short msg_cbytes; /* current number of bytes on queue */ - unsigned short msg_qnum; /* number of messages in queue */ - unsigned short msg_qbytes; /* max number of bytes on queue */ - __kernel_ipc_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_ipc_pid_t msg_lrpid; /* last receive pid */ -}; - -#endif - struct msqid_ds { struct ipc_perm msg_perm; - struct msg *msg_first; /* first message on queue */ - struct msg *msg_last; /* last message in queue */ + struct msg *msg_first; /* first message on queue,unused */ + struct msg *msg_last; /* last message in queue,unused */ __kernel_time_t msg_stime; /* last msgsnd time */ __kernel_time_t msg_rtime; /* last msgrcv time */ __kernel_time_t msg_ctime; /* last change time */ @@ -66,9 +45,9 @@ struct msginfo { unsigned short msgseg; }; -#define MSGMNI 128 /* <= 1K */ /* max # of msg queue identifiers */ -#define MSGMAX 4056 /* <= 4056 */ /* max size of message (bytes) */ -#define MSGMNB 16384 /* ? */ /* default max size of a message queue */ +#define MSGMNI 128 /* <= 32768 */ /* max # of msg queue identifiers */ +#define MSGMAX 4056 /* <= 4056 (?)*/ /* max size of message (bytes) */ +#define MSGMNB 16384 /* <= MAX_INT */ /* default max size of a message queue */ /* unused */ #define MSGPOOL (MSGMNI*MSGMNB/1024) /* size in kilobytes of message pool */ @@ -80,15 +59,6 @@ struct msginfo { #ifdef __KERNEL__ -/* one msg structure for each message */ -struct msg { - struct msg *msg_next; /* next message on queue */ - long msg_type; - char *msg_spot; /* message text address */ - time_t msg_stime; /* msgsnd time */ - short msg_ts; /* message text size */ -}; - asmlinkage long sys_msgget (key_t key, int msgflg); asmlinkage long sys_msgsnd (int msqid, struct msgbuf *msgp, size_t msgsz, int msgflg); asmlinkage long sys_msgrcv (int msqid, struct msgbuf *msgp, size_t msgsz, long msgtyp, int msgflg); diff --git a/include/linux/ncp.h b/include/linux/ncp.h index 229618db0..e6cdfe1b0 100644 --- a/include/linux/ncp.h +++ b/include/linux/ncp.h @@ -11,7 +11,6 @@ #define _LINUX_NCP_H #include <linux/types.h> -#include <linux/ipx.h> #define NCP_PTYPE (0x11) #define NCP_PORT (0x0451) @@ -57,21 +56,6 @@ struct ncp_volume_info { char volume_name[NCP_VOLNAME_LEN + 1]; }; -/* these define the attribute byte as seen by NCP */ -#define aRONLY (ntohl(0x01000000)) -#define aHIDDEN (__constant_ntohl(0x02000000)) -#define aSYSTEM (__constant_ntohl(0x04000000)) -#define aEXECUTE (ntohl(0x08000000)) -#define aDIR (ntohl(0x10000000)) -#define aARCH (ntohl(0x20000000)) -#define aSHARED (ntohl(0x80000000)) -#define aDONTSUBALLOCATE (ntohl(1L<<(11+8))) -#define aTRANSACTIONAL (ntohl(1L<<(12+8))) -#define aPURGE (ntohl(1L<<(16-8))) -#define aRENAMEINHIBIT (ntohl(1L<<(17-8))) -#define aDELETEINHIBIT (ntohl(1L<<(18-8))) -#define aDONTCOMPRESS (nothl(1L<<(27-24))) - #define AR_READ (ntohs(0x0100)) #define AR_WRITE (ntohs(0x0200)) #define AR_EXCLUSIVE (ntohs(0x2000)) @@ -186,15 +170,6 @@ struct nw_modify_dos_info { __u32 maximumSpace __attribute__((packed)); }; -struct nw_file_info { - struct nw_info_struct i; - int opened; - int access; - __u32 server_file_handle __attribute__((packed)); - __u8 open_create_action __attribute__((packed)); - __u8 file_handle[6] __attribute__((packed)); -}; - struct nw_search_sequence { __u8 volNumber __attribute__((packed)); __u32 dirBase __attribute__((packed)); diff --git a/include/linux/ncp_fs.h b/include/linux/ncp_fs.h index 9c5df5342..1be68cfb5 100644 --- a/include/linux/ncp_fs.h +++ b/include/linux/ncp_fs.h @@ -12,18 +12,8 @@ #include <linux/in.h> #include <linux/types.h> -#include <linux/ncp_mount.h> - -/* NLS charsets by ioctl */ -#define NCP_IOCSNAME_LEN 20 -struct ncp_nls_ioctl -{ - unsigned char codepage[NCP_IOCSNAME_LEN+1]; - unsigned char iocharset[NCP_IOCSNAME_LEN+1]; -}; - -#include <linux/ncp_fs_sb.h> -#include <linux/ncp_fs_i.h> +#include <linux/ipx.h> +#include <linux/ncp_no.h> /* * ioctl commands @@ -91,6 +81,14 @@ struct ncp_privatedata_ioctl void* data; /* ~1000 for NDS */ }; +/* NLS charsets by ioctl */ +#define NCP_IOCSNAME_LEN 20 +struct ncp_nls_ioctl +{ + unsigned char codepage[NCP_IOCSNAME_LEN+1]; + unsigned char iocharset[NCP_IOCSNAME_LEN+1]; +}; + #define NCP_IOC_NCPREQUEST _IOR('n', 1, struct ncp_ioctl_request) #define NCP_IOC_GETMOUNTUID _IOW('n', 2, __kernel_uid_t) @@ -123,6 +121,9 @@ struct ncp_privatedata_ioctl #define NCP_IOC_GETCHARSETS _IOWR('n', 11, struct ncp_nls_ioctl) #define NCP_IOC_SETCHARSETS _IOR('n', 11, struct ncp_nls_ioctl) +#define NCP_IOC_GETDENTRYTTL _IOW('n', 12, __u32) +#define NCP_IOC_SETDENTRYTTL _IOR('n', 12, __u32) + /* * The packet size to allocate. One page should be enough. */ @@ -151,53 +152,27 @@ struct ncp_privatedata_ioctl #define DDPRINTK(format, args...) #endif -/* The readdir cache size controls how many directory entries are - * cached. - */ -#define NCP_READDIR_CACHE_SIZE 64 - #define NCP_MAX_RPC_TIMEOUT (6*HZ) -/* - * This is the ncpfs part of the inode structure. This must contain - * all the information we need to work with an inode after creation. - * (Move to ncp_fs_i.h once it stabilizes, and add a union in fs.h) - */ -struct ncpfs_i { - __u32 dirEntNum __attribute__((packed)); - __u32 DosDirNum __attribute__((packed)); - __u32 volNumber __attribute__((packed)); -#ifdef CONFIG_NCPFS_SMALLDOS - __u32 origNS; -#endif -#ifdef CONFIG_NCPFS_STRONG - __u32 nwattr; -#endif - int opened; - int access; - __u32 server_file_handle __attribute__((packed)); - __u8 open_create_action __attribute__((packed)); - __u8 file_handle[6] __attribute__((packed)); -}; -/* - * This is an extension of the nw_file_info structure with - * the additional information we need to create an inode. - */ -struct ncpfs_inode_info { - ino_t ino; /* dummy inode number */ - struct nw_file_info nw_info; +struct ncp_entry_info { + struct nw_info_struct i; + ino_t ino; + int opened; + int access; + __u32 server_file_handle __attribute__((packed)); + __u8 open_create_action __attribute__((packed)); + __u8 file_handle[6] __attribute__((packed)); }; /* Guess, what 0x564c is :-) */ #define NCP_SUPER_MAGIC 0x564c -#define NCP_SBP(sb) ((struct ncp_server *)((sb)->u.generic_sbp)) +#define NCP_SBP(sb) (&((sb)->u.ncpfs_sb)) -#define NCP_SERVER(inode) NCP_SBP((inode)->i_sb) -/* We don't have an ncpfs union yet, so use smbfs ... */ -#define NCP_FINFO(inode) ((struct ncpfs_i *)&((inode)->u.smbfs_i)) +#define NCP_SERVER(inode) NCP_SBP((inode)->i_sb) +#define NCP_FINFO(inode) (&((inode)->u.ncpfs_i)) #ifdef DEBUG_NCP_MALLOC @@ -230,17 +205,14 @@ static inline void ncp_kfree_s(void *obj, int size) /* linux/fs/ncpfs/inode.c */ int ncp_notify_change(struct dentry *, struct iattr *attr); struct super_block *ncp_read_super(struct super_block *, void *, int); -struct inode *ncp_iget(struct super_block *, struct ncpfs_inode_info *); -void ncp_update_inode(struct inode *, struct nw_file_info *); -void ncp_update_inode2(struct inode *, struct nw_file_info *); +struct inode *ncp_iget(struct super_block *, struct ncp_entry_info *); +void ncp_update_inode(struct inode *, struct ncp_entry_info *); +void ncp_update_inode2(struct inode *, struct ncp_entry_info *); extern int init_ncp_fs(void); /* linux/fs/ncpfs/dir.c */ extern struct inode_operations ncp_dir_inode_operations; -int ncp_conn_logged_in(struct ncp_server *); -void ncp_init_dir_cache(void); -void ncp_invalid_dir_cache(struct inode *); -void ncp_free_dir_cache(void); +int ncp_conn_logged_in(struct super_block *); int ncp_date_dos2unix(__u16 time, __u16 date); void ncp_date_unix2dos(int unix_date, __u16 * time, __u16 * date); diff --git a/include/linux/ncp_fs_i.h b/include/linux/ncp_fs_i.h index 3df38b287..96728bcdd 100644 --- a/include/linux/ncp_fs_i.h +++ b/include/linux/ncp_fs_i.h @@ -8,29 +8,24 @@ #ifndef _LINUX_NCP_FS_I #define _LINUX_NCP_FS_I -#include <linux/ncp.h> - #ifdef __KERNEL__ -enum ncp_inode_state { - NCP_INODE_VALID = 19, /* Inode currently in use */ - NCP_INODE_LOOKED_UP, /* directly before iget */ - NCP_INODE_CACHED, /* in a path to an inode which is in use */ - NCP_INODE_INVALID -}; - /* - * ncp fs inode data (in memory only) + * This is the ncpfs part of the inode structure. This must contain + * all the information we need to work with an inode after creation. */ struct ncp_inode_info { - enum ncp_inode_state state; - int nused; /* for directories: - number of references in memory */ - struct ncp_inode_info *dir; - struct ncp_inode_info *next, *prev; - struct inode *inode; - struct nw_file_info finfo; + __u32 dirEntNum __attribute__((packed)); + __u32 DosDirNum __attribute__((packed)); + __u32 volNumber __attribute__((packed)); + __u32 nwattr; + int opened; + int access; + __u32 server_file_handle __attribute__((packed)); + __u8 open_create_action __attribute__((packed)); + __u8 file_handle[6] __attribute__((packed)); }; -#endif -#endif +#endif /* __KERNEL__ */ + +#endif /* _LINUX_NCP_FS_I */ diff --git a/include/linux/ncp_fs_sb.h b/include/linux/ncp_fs_sb.h index 43f902bed..6f71f8e37 100644 --- a/include/linux/ncp_fs_sb.h +++ b/include/linux/ncp_fs_sb.h @@ -8,9 +8,8 @@ #ifndef _NCP_FS_SB #define _NCP_FS_SB -#include <asm/semaphore.h> -#include <linux/ncp_mount.h> #include <linux/types.h> +#include <linux/ncp_mount.h> #ifdef __KERNEL__ @@ -51,9 +50,6 @@ struct ncp_server { int has_subfunction; int ncp_reply_size; - struct ncp_inode_info root; - struct dentry* root_dentry; - int root_setuped; /* info for packet signing */ @@ -75,11 +71,17 @@ struct ncp_server { void* data; } priv; - struct ncp_nls_ioctl nls_charsets; /* NLS user data */ - struct nls_table *nls_vol; /* codepage used on volume */ - struct nls_table *nls_io; /* charset used for input and display */ + /* nls info: codepage for volume and charset for I/O */ + struct nls_table *nls_vol; + struct nls_table *nls_io; + + /* maximum age in jiffies */ + int dentry_ttl; }; +#define ncp_sb_info ncp_server + + static inline int ncp_conn_valid(struct ncp_server *server) { return ((server->conn_status & 0x11) == 0); diff --git a/include/linux/ncp_mount.h b/include/linux/ncp_mount.h index a214372a5..a276ab1e4 100644 --- a/include/linux/ncp_mount.h +++ b/include/linux/ncp_mount.h @@ -9,9 +9,7 @@ #define _LINUX_NCP_MOUNT_H #include <linux/types.h> -#include <linux/ipx.h> #include <linux/ncp.h> -#include <linux/ncp_fs_i.h> #define NCP_MOUNT_VERSION 3 diff --git a/include/linux/ncp_no.h b/include/linux/ncp_no.h new file mode 100644 index 000000000..a4523ed0e --- /dev/null +++ b/include/linux/ncp_no.h @@ -0,0 +1,19 @@ +#ifndef _NCP_NO +#define _NCP_NO + +/* these define the attribute byte as seen by NCP */ +#define aRONLY (ntohl(0x01000000)) +#define aHIDDEN (__constant_ntohl(0x02000000)) +#define aSYSTEM (__constant_ntohl(0x04000000)) +#define aEXECUTE (ntohl(0x08000000)) +#define aDIR (ntohl(0x10000000)) +#define aARCH (ntohl(0x20000000)) +#define aSHARED (ntohl(0x80000000)) +#define aDONTSUBALLOCATE (ntohl(1L<<(11+8))) +#define aTRANSACTIONAL (ntohl(1L<<(12+8))) +#define aPURGE (ntohl(1L<<(16-8))) +#define aRENAMEINHIBIT (ntohl(1L<<(17-8))) +#define aDELETEINHIBIT (ntohl(1L<<(18-8))) +#define aDONTCOMPRESS (nothl(1L<<(27-24))) + +#endif /* _NCP_NO */ diff --git a/include/linux/net.h b/include/linux/net.h index 8b4b3f35a..d91b6bcf6 100644 --- a/include/linux/net.h +++ b/include/linux/net.h @@ -126,7 +126,7 @@ struct net_proto void (*init_func)(struct net_proto *); /* Bootstrap */ }; -extern int sock_wake_async(struct socket *sk, int how); +extern int sock_wake_async(struct socket *sk, int how, int band); extern int sock_register(struct net_proto_family *fam); extern int sock_unregister(int family); extern struct socket *sock_alloc(void); diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 6c1b4a630..89c05f9f0 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -77,7 +77,8 @@ struct nf_sockopt_ops int nf_register_hook(struct nf_hook_ops *reg); void nf_unregister_hook(struct nf_hook_ops *reg); -/* Functions to register get/setsockopt ranges (non-inclusive). */ +/* Functions to register get/setsockopt ranges (non-inclusive). You + need to check permissions yourself! */ int nf_register_sockopt(struct nf_sockopt_ops *reg); void nf_unregister_sockopt(struct nf_sockopt_ops *reg); diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h index d3bc6887f..12996c14d 100644 --- a/include/linux/netfilter_ipv4.h +++ b/include/linux/netfilter_ipv4.h @@ -58,4 +58,10 @@ void nf_debug_ip_finish_output2(struct sk_buff *skb); #endif /*__KERNEL__*/ #endif /*CONFIG_NETFILTER_DEBUG*/ +/* Arguments for setsockopt SOL_IP: */ +/* 2.0 firewalling went from 64 through 71 (and +256, +512, etc). */ +/* 2.2 firewalling (+ masq) went from 64 through 76 */ +/* 2.4 firewalling went 64 through 67. */ +#define SO_ORIGINAL_DST 80 + #endif /*__LINUX_IP_NETFILTER_H*/ diff --git a/include/linux/parport.h b/include/linux/parport.h index 50256a87d..f1c6cb5af 100644 --- a/include/linux/parport.h +++ b/include/linux/parport.h @@ -13,6 +13,7 @@ #define PARPORT_DMA_NONE -1 #define PARPORT_IRQ_AUTO -2 #define PARPORT_DMA_AUTO -2 +#define PARPORT_DMA_NOFIFO -3 #define PARPORT_DISABLE -2 #define PARPORT_IRQ_PROBEONLY -3 diff --git a/include/linux/parport_pc.h b/include/linux/parport_pc.h index a8c67bc9d..6898c4e5f 100644 --- a/include/linux/parport_pc.h +++ b/include/linux/parport_pc.h @@ -41,33 +41,50 @@ struct parport_pc_private { extern __inline__ void parport_pc_write_data(struct parport *p, unsigned char d) { +#ifdef DEBUG_PARPORT + printk (KERN_DEBUG "parport_pc_write_data(%p,0x%02x)\n", p, d); +#endif outb(d, DATA(p)); } extern __inline__ unsigned char parport_pc_read_data(struct parport *p) { - return inb(DATA(p)); + unsigned char val = inb (DATA (p)); +#ifdef DEBUG_PARPORT + printk (KERN_DEBUG "parport_pc_read_data(%p) = 0x%02x\n", + p, val); +#endif + return val; } -extern __inline__ unsigned char __frob_control (struct parport *p, - unsigned char mask, - unsigned char val) +/* __parport_pc_frob_control differs from parport_pc_frob_control in that + * it doesn't do any extra masking. */ +static __inline__ unsigned char __parport_pc_frob_control (struct parport *p, + unsigned char mask, + unsigned char val) { - const unsigned char wm = (PARPORT_CONTROL_STROBE | - PARPORT_CONTROL_AUTOFD | - PARPORT_CONTROL_INIT | - PARPORT_CONTROL_SELECT); struct parport_pc_private *priv = p->physport->private_data; unsigned char ctr = priv->ctr; +#ifdef DEBUG_PARPORT + printk (KERN_DEBUG + "__parport_pc_frob_control(%02x,%02x): %02x -> %02x\n", + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); +#endif ctr = (ctr & ~mask) ^ val; ctr &= priv->ctr_writable; /* only write writable bits. */ outb (ctr, CONTROL (p)); - return priv->ctr = ctr & wm; /* update soft copy */ + priv->ctr = ctr; /* Update soft copy */ + return ctr; } extern __inline__ void parport_pc_data_reverse (struct parport *p) { - __frob_control (p, 0x20, 0x20); + __parport_pc_frob_control (p, 0x20, 0x20); +} + +extern __inline__ void parport_pc_data_forward (struct parport *p) +{ + __parport_pc_frob_control (p, 0x20, 0x00); } extern __inline__ void parport_pc_write_control (struct parport *p, @@ -80,18 +97,22 @@ extern __inline__ void parport_pc_write_control (struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (d & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n", - p->name, p->cad->name); - parport_pc_data_reverse (p); + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n", + p->name, p->cad->name); + parport_pc_data_reverse (p); } - __frob_control (p, wm, d & wm); + __parport_pc_frob_control (p, wm, d & wm); } extern __inline__ unsigned char parport_pc_read_control(struct parport *p) { + const unsigned char rm = (PARPORT_CONTROL_STROBE | + PARPORT_CONTROL_AUTOFD | + PARPORT_CONTROL_INIT | + PARPORT_CONTROL_SELECT); const struct parport_pc_private *priv = p->physport->private_data; - return priv->ctr; /* Use soft copy */ + return priv->ctr & rm; /* Use soft copy */ } extern __inline__ unsigned char parport_pc_frob_control (struct parport *p, @@ -105,16 +126,20 @@ extern __inline__ unsigned char parport_pc_frob_control (struct parport *p, /* Take this out when drivers have adapted to newer interface. */ if (mask & 0x20) { - printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n", - p->name, p->cad->name); + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n", + p->name, p->cad->name, + (val & 0x20) ? "reverse" : "forward"); + if (val & 0x20) parport_pc_data_reverse (p); + else + parport_pc_data_forward (p); } /* Restrict mask and val to control lines. */ mask &= wm; val &= wm; - return __frob_control (p, mask, val); + return __parport_pc_frob_control (p, mask, val); } extern __inline__ unsigned char parport_pc_read_status(struct parport *p) @@ -122,19 +147,15 @@ extern __inline__ unsigned char parport_pc_read_status(struct parport *p) return inb(STATUS(p)); } -extern __inline__ void parport_pc_data_forward (struct parport *p) -{ - __frob_control (p, 0x20, 0x00); -} extern __inline__ void parport_pc_disable_irq(struct parport *p) { - __frob_control (p, 0x10, 0x00); + __parport_pc_frob_control (p, 0x10, 0x00); } extern __inline__ void parport_pc_enable_irq(struct parport *p) { - __frob_control (p, 0x10, 0x10); + __parport_pc_frob_control (p, 0x10, 0x10); } extern void parport_pc_release_resources(struct parport *p); diff --git a/include/linux/pci.h b/include/linux/pci.h index 5148fcd7f..a52799997 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -262,1097 +262,9 @@ #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ -/* Device classes and subclasses */ - -#define PCI_CLASS_NOT_DEFINED 0x0000 -#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 - -#define PCI_BASE_CLASS_STORAGE 0x01 -#define PCI_CLASS_STORAGE_SCSI 0x0100 -#define PCI_CLASS_STORAGE_IDE 0x0101 -#define PCI_CLASS_STORAGE_FLOPPY 0x0102 -#define PCI_CLASS_STORAGE_IPI 0x0103 -#define PCI_CLASS_STORAGE_RAID 0x0104 -#define PCI_CLASS_STORAGE_OTHER 0x0180 - -#define PCI_BASE_CLASS_NETWORK 0x02 -#define PCI_CLASS_NETWORK_ETHERNET 0x0200 -#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 -#define PCI_CLASS_NETWORK_FDDI 0x0202 -#define PCI_CLASS_NETWORK_ATM 0x0203 -#define PCI_CLASS_NETWORK_OTHER 0x0280 - -#define PCI_BASE_CLASS_DISPLAY 0x03 -#define PCI_CLASS_DISPLAY_VGA 0x0300 -#define PCI_CLASS_DISPLAY_XGA 0x0301 -#define PCI_CLASS_DISPLAY_OTHER 0x0380 - -#define PCI_BASE_CLASS_MULTIMEDIA 0x04 -#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 -#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 -#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 - -#define PCI_BASE_CLASS_MEMORY 0x05 -#define PCI_CLASS_MEMORY_RAM 0x0500 -#define PCI_CLASS_MEMORY_FLASH 0x0501 -#define PCI_CLASS_MEMORY_OTHER 0x0580 - -#define PCI_BASE_CLASS_BRIDGE 0x06 -#define PCI_CLASS_BRIDGE_HOST 0x0600 -#define PCI_CLASS_BRIDGE_ISA 0x0601 -#define PCI_CLASS_BRIDGE_EISA 0x0602 -#define PCI_CLASS_BRIDGE_MC 0x0603 -#define PCI_CLASS_BRIDGE_PCI 0x0604 -#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 -#define PCI_CLASS_BRIDGE_NUBUS 0x0606 -#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 -#define PCI_CLASS_BRIDGE_OTHER 0x0680 - -#define PCI_BASE_CLASS_COMMUNICATION 0x07 -#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 -#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 -#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 - -#define PCI_BASE_CLASS_SYSTEM 0x08 -#define PCI_CLASS_SYSTEM_PIC 0x0800 -#define PCI_CLASS_SYSTEM_DMA 0x0801 -#define PCI_CLASS_SYSTEM_TIMER 0x0802 -#define PCI_CLASS_SYSTEM_RTC 0x0803 -#define PCI_CLASS_SYSTEM_OTHER 0x0880 - -#define PCI_BASE_CLASS_INPUT 0x09 -#define PCI_CLASS_INPUT_KEYBOARD 0x0900 -#define PCI_CLASS_INPUT_PEN 0x0901 -#define PCI_CLASS_INPUT_MOUSE 0x0902 -#define PCI_CLASS_INPUT_OTHER 0x0980 - -#define PCI_BASE_CLASS_DOCKING 0x0a -#define PCI_CLASS_DOCKING_GENERIC 0x0a00 -#define PCI_CLASS_DOCKING_OTHER 0x0a01 - -#define PCI_BASE_CLASS_PROCESSOR 0x0b -#define PCI_CLASS_PROCESSOR_386 0x0b00 -#define PCI_CLASS_PROCESSOR_486 0x0b01 -#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 -#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 -#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 -#define PCI_CLASS_PROCESSOR_CO 0x0b40 - -#define PCI_BASE_CLASS_SERIAL 0x0c -#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 -#define PCI_CLASS_SERIAL_ACCESS 0x0c01 -#define PCI_CLASS_SERIAL_SSA 0x0c02 -#define PCI_CLASS_SERIAL_USB 0x0c03 -#define PCI_CLASS_SERIAL_FIBER 0x0c04 - -#define PCI_BASE_CLASS_INTELLIGENT 0x0e -#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 - -#define PCI_CLASS_HOT_SWAP_CONTROLLER 0xff00 - -#define PCI_CLASS_OTHERS 0xff +/* Include the ID list */ -/* - * Vendor and card ID's: sort these numerically according to vendor - * (and according to card ID within vendor). Send all updates to - * <pci-ids@ucw.cz>. - */ -#define PCI_VENDOR_ID_COMPAQ 0x0e11 -#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 -#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 -#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 -#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 -#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 -#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 -#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 -#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 -#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 -#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 -#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 -#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 - -#define PCI_VENDOR_ID_NCR 0x1000 -#define PCI_DEVICE_ID_NCR_53C810 0x0001 -#define PCI_DEVICE_ID_NCR_53C820 0x0002 -#define PCI_DEVICE_ID_NCR_53C825 0x0003 -#define PCI_DEVICE_ID_NCR_53C815 0x0004 -#define PCI_DEVICE_ID_NCR_53C860 0x0006 -#define PCI_DEVICE_ID_NCR_53C896 0x000b -#define PCI_DEVICE_ID_NCR_53C895 0x000c -#define PCI_DEVICE_ID_NCR_53C885 0x000d -#define PCI_DEVICE_ID_NCR_53C875 0x000f -#define PCI_DEVICE_ID_NCR_53C1510 0x0010 -#define PCI_DEVICE_ID_NCR_53C875J 0x008f - -#define PCI_VENDOR_ID_ATI 0x1002 -#define PCI_DEVICE_ID_ATI_68800 0x4158 -#define PCI_DEVICE_ID_ATI_215CT222 0x4354 -#define PCI_DEVICE_ID_ATI_210888CX 0x4358 -#define PCI_DEVICE_ID_ATI_215GB 0x4742 -#define PCI_DEVICE_ID_ATI_215GD 0x4744 -#define PCI_DEVICE_ID_ATI_215GI 0x4749 -#define PCI_DEVICE_ID_ATI_215GP 0x4750 -#define PCI_DEVICE_ID_ATI_215GQ 0x4751 -#define PCI_DEVICE_ID_ATI_215GT 0x4754 -#define PCI_DEVICE_ID_ATI_215GTB 0x4755 -#define PCI_DEVICE_ID_ATI_210888GX 0x4758 -#define PCI_DEVICE_ID_ATI_215LG 0x4c47 -#define PCI_DEVICE_ID_ATI_264LT 0x4c54 -#define PCI_DEVICE_ID_ATI_264VT 0x5654 - -#define PCI_VENDOR_ID_VLSI 0x1004 -#define PCI_DEVICE_ID_VLSI_82C592 0x0005 -#define PCI_DEVICE_ID_VLSI_82C593 0x0006 -#define PCI_DEVICE_ID_VLSI_82C594 0x0007 -#define PCI_DEVICE_ID_VLSI_82C597 0x0009 -#define PCI_DEVICE_ID_VLSI_82C541 0x000c -#define PCI_DEVICE_ID_VLSI_82C543 0x000d -#define PCI_DEVICE_ID_VLSI_82C532 0x0101 -#define PCI_DEVICE_ID_VLSI_82C534 0x0102 -#define PCI_DEVICE_ID_VLSI_82C535 0x0104 -#define PCI_DEVICE_ID_VLSI_82C147 0x0105 -#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 - -#define PCI_VENDOR_ID_ADL 0x1005 -#define PCI_DEVICE_ID_ADL_2301 0x2301 - -#define PCI_VENDOR_ID_NS 0x100b -#define PCI_DEVICE_ID_NS_87415 0x0002 -#define PCI_DEVICE_ID_NS_87410 0xd001 - -#define PCI_VENDOR_ID_TSENG 0x100c -#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 -#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 -#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 -#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 -#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 - -#define PCI_VENDOR_ID_WEITEK 0x100e -#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 -#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 - -#define PCI_VENDOR_ID_DEC 0x1011 -#define PCI_DEVICE_ID_DEC_BRD 0x0001 -#define PCI_DEVICE_ID_DEC_TULIP 0x0002 -#define PCI_DEVICE_ID_DEC_TGA 0x0004 -#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 -#define PCI_DEVICE_ID_DEC_TGA2 0x000D -#define PCI_DEVICE_ID_DEC_FDDI 0x000F -#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 -#define PCI_DEVICE_ID_DEC_21142 0x0019 -#define PCI_DEVICE_ID_DEC_21052 0x0021 -#define PCI_DEVICE_ID_DEC_21150 0x0022 -#define PCI_DEVICE_ID_DEC_21152 0x0024 -#define PCI_DEVICE_ID_DEC_21153 0x0025 -#define PCI_DEVICE_ID_DEC_21154 0x0026 -#define PCI_DEVICE_ID_DEC_21285 0x1065 -#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 - -#define PCI_VENDOR_ID_CIRRUS 0x1013 -#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 -#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 -#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 -#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 -#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac -#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 -#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc -#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 -#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 -#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 -#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 -#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 -#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 -#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 -#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 - -#define PCI_VENDOR_ID_IBM 0x1014 -#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a -#define PCI_DEVICE_ID_IBM_TR 0x0018 -#define PCI_DEVICE_ID_IBM_82G2675 0x001d -#define PCI_DEVICE_ID_IBM_MCA 0x0020 -#define PCI_DEVICE_ID_IBM_82351 0x0022 -#define PCI_DEVICE_ID_IBM_PYTHON 0x002d -#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e -#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e -#define PCI_DEVICE_ID_IBM_MPIC 0x0046 -#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d -#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff - -#define PCI_VENDOR_ID_WD 0x101c -#define PCI_DEVICE_ID_WD_7197 0x3296 - -#define PCI_VENDOR_ID_AMD 0x1022 -#define PCI_DEVICE_ID_AMD_LANCE 0x2000 -#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 -#define PCI_DEVICE_ID_AMD_SCSI 0x2020 - -#define PCI_VENDOR_ID_TRIDENT 0x1023 -#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 -#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 -#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 -#define PCI_DEVICE_ID_TRIDENT_939A 0x939A -#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 -#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 -#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 -#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 -#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 -#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 -#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 -#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 -#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 -#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 -#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 - -#define PCI_VENDOR_ID_AI 0x1025 -#define PCI_DEVICE_ID_AI_M1435 0x1435 - -#define PCI_VENDOR_ID_MATROX 0x102B -#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 -#define PCI_DEVICE_ID_MATROX_MIL 0x0519 -#define PCI_DEVICE_ID_MATROX_MYS 0x051A -#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b -#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f -#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 -#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 -#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 -#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 -#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 -#define PCI_DEVICE_ID_MATROX_G400 0x0525 -#define PCI_DEVICE_ID_MATROX_VIA 0x4536 - -#define PCI_VENDOR_ID_CT 0x102c -#define PCI_DEVICE_ID_CT_65545 0x00d8 -#define PCI_DEVICE_ID_CT_65548 0x00dc -#define PCI_DEVICE_ID_CT_65550 0x00e0 -#define PCI_DEVICE_ID_CT_65554 0x00e4 -#define PCI_DEVICE_ID_CT_65555 0x00e5 - -#define PCI_VENDOR_ID_MIRO 0x1031 -#define PCI_DEVICE_ID_MIRO_36050 0x5601 - -#define PCI_VENDOR_ID_NEC 0x1033 -#define PCI_DEVICE_ID_NEC_PCX2 0x0046 - -#define PCI_VENDOR_ID_FD 0x1036 -#define PCI_DEVICE_ID_FD_36C70 0x0000 - -#define PCI_VENDOR_ID_SI 0x1039 -#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 -#define PCI_DEVICE_ID_SI_6202 0x0002 -#define PCI_DEVICE_ID_SI_503 0x0008 -#define PCI_DEVICE_ID_SI_ACPI 0x0009 -#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 -#define PCI_DEVICE_ID_SI_6205 0x0205 -#define PCI_DEVICE_ID_SI_501 0x0406 -#define PCI_DEVICE_ID_SI_496 0x0496 -#define PCI_DEVICE_ID_SI_530 0x0530 -#define PCI_DEVICE_ID_SI_601 0x0601 -#define PCI_DEVICE_ID_SI_620 0x0620 -#define PCI_DEVICE_ID_SI_5107 0x5107 -#define PCI_DEVICE_ID_SI_5511 0x5511 -#define PCI_DEVICE_ID_SI_5513 0x5513 -#define PCI_DEVICE_ID_SI_5571 0x5571 -#define PCI_DEVICE_ID_SI_5591 0x5591 -#define PCI_DEVICE_ID_SI_5597 0x5597 -#define PCI_DEVICE_ID_SI_5600 0x5600 -#define PCI_DEVICE_ID_SI_6306 0x6306 -#define PCI_DEVICE_ID_SI_6326 0x6326 -#define PCI_DEVICE_ID_SI_7001 0x7001 - -#define PCI_VENDOR_ID_HP 0x103c -#define PCI_DEVICE_ID_HP_J2585A 0x1030 -#define PCI_DEVICE_ID_HP_J2585B 0x1031 - -#define PCI_VENDOR_ID_PCTECH 0x1042 -#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 -#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 -#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 -#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 -#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 - -#define PCI_VENDOR_ID_DPT 0x1044 -#define PCI_DEVICE_ID_DPT 0xa400 - -#define PCI_VENDOR_ID_OPTI 0x1045 -#define PCI_DEVICE_ID_OPTI_92C178 0xc178 -#define PCI_DEVICE_ID_OPTI_82C557 0xc557 -#define PCI_DEVICE_ID_OPTI_82C558 0xc558 -#define PCI_DEVICE_ID_OPTI_82C621 0xc621 -#define PCI_DEVICE_ID_OPTI_82C700 0xc700 -#define PCI_DEVICE_ID_OPTI_82C701 0xc701 -#define PCI_DEVICE_ID_OPTI_82C814 0xc814 -#define PCI_DEVICE_ID_OPTI_82C822 0xc822 -#define PCI_DEVICE_ID_OPTI_82C861 0xc861 -#define PCI_DEVICE_ID_OPTI_82C825 0xd568 - -#define PCI_VENDOR_ID_SGS 0x104a -#define PCI_DEVICE_ID_SGS_2000 0x0008 -#define PCI_DEVICE_ID_SGS_1764 0x0009 - -#define PCI_VENDOR_ID_BUSLOGIC 0x104B -#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 -#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 -#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 - -#define PCI_VENDOR_ID_TI 0x104c -#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 -#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 -#define PCI_DEVICE_ID_TI_PCI1130 0xac12 -#define PCI_DEVICE_ID_TI_PCI1031 0xac13 -#define PCI_DEVICE_ID_TI_PCI1131 0xac15 -#define PCI_DEVICE_ID_TI_PCI1250 0xac16 -#define PCI_DEVICE_ID_TI_PCI1220 0xac17 - -#define PCI_VENDOR_ID_OAK 0x104e -#define PCI_DEVICE_ID_OAK_OTI107 0x0107 - -/* Winbond have two vendor IDs! See 0x10ad as well */ -#define PCI_VENDOR_ID_WINBOND2 0x1050 -#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 -#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a - -#define PCI_VENDOR_ID_MOTOROLA 0x1057 -#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 -#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 -#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 -#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 -#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 -#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 - -#define PCI_VENDOR_ID_PROMISE 0x105a -#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 -#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 -#define PCI_DEVICE_ID_PROMISE_5300 0x5300 - -#define PCI_VENDOR_ID_N9 0x105d -#define PCI_DEVICE_ID_N9_I128 0x2309 -#define PCI_DEVICE_ID_N9_I128_2 0x2339 -#define PCI_DEVICE_ID_N9_I128_T2R 0x493d - -#define PCI_VENDOR_ID_UMC 0x1060 -#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 -#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 -#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a -#define PCI_DEVICE_ID_UMC_UM8886A 0x886a -#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 -#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 -#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 -#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 -#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 - -#define PCI_VENDOR_ID_X 0x1061 -#define PCI_DEVICE_ID_X_AGX016 0x0001 - -#define PCI_VENDOR_ID_MYLEX 0x1069 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 - -#define PCI_VENDOR_ID_MYLEX 0x1069 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 - -#define PCI_VENDOR_ID_MYLEX 0x1069 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 - -#define PCI_VENDOR_ID_PICOP 0x1066 -#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 -#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 - -#define PCI_VENDOR_ID_APPLE 0x106b -#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 -#define PCI_DEVICE_ID_APPLE_GC 0x0002 -#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e - -#define PCI_VENDOR_ID_NEXGEN 0x1074 -#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 - -#define PCI_VENDOR_ID_QLOGIC 0x1077 -#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 -#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 -#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 -#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 - -#define PCI_VENDOR_ID_CYRIX 0x1078 -#define PCI_DEVICE_ID_CYRIX_5510 0x0000 -#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 -#define PCI_DEVICE_ID_CYRIX_5520 0x0002 -#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 -#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 -#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 -#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 -#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 - -#define PCI_VENDOR_ID_LEADTEK 0x107d -#define PCI_DEVICE_ID_LEADTEK_805 0x0000 - -#define PCI_VENDOR_ID_CONTAQ 0x1080 -#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 -#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 - -#define PCI_VENDOR_ID_FOREX 0x1083 - -#define PCI_VENDOR_ID_OLICOM 0x108d -#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 -#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 -#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 -#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 -#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 -#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 - -#define PCI_VENDOR_ID_SUN 0x108e -#define PCI_DEVICE_ID_SUN_EBUS 0x1000 -#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 -#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 -#define PCI_DEVICE_ID_SUN_PBM 0x8000 -#define PCI_DEVICE_ID_SUN_SABRE 0xa000 - -#define PCI_VENDOR_ID_CMD 0x1095 -#define PCI_DEVICE_ID_CMD_640 0x0640 -#define PCI_DEVICE_ID_CMD_643 0x0643 -#define PCI_DEVICE_ID_CMD_646 0x0646 -#define PCI_DEVICE_ID_CMD_647 0x0647 -#define PCI_DEVICE_ID_CMD_670 0x0670 - -#define PCI_VENDOR_ID_VISION 0x1098 -#define PCI_DEVICE_ID_VISION_QD8500 0x0001 -#define PCI_DEVICE_ID_VISION_QD8580 0x0002 - -#define PCI_VENDOR_ID_BROOKTREE 0x109e -#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 -#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 -#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e -#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 -#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 - -#define PCI_VENDOR_ID_SIERRA 0x10a8 -#define PCI_DEVICE_ID_SIERRA_STB 0x0000 - -#define PCI_VENDOR_ID_SGI 0x10a9 -#define PCI_DEVICE_ID_SGI_IOC3 0x0003 - -#define PCI_VENDOR_ID_ACC 0x10aa -#define PCI_DEVICE_ID_ACC_2056 0x0000 - -#define PCI_VENDOR_ID_WINBOND 0x10ad -#define PCI_DEVICE_ID_WINBOND_83769 0x0001 -#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 -#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 - -#define PCI_VENDOR_ID_DATABOOK 0x10b3 -#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 - -#define PCI_VENDOR_ID_PLX 0x10b5 -#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 -#define PCI_DEVICE_ID_PLX_9050 0x9050 -#define PCI_DEVICE_ID_PLX_9060 0x9060 -#define PCI_DEVICE_ID_PLX_9060ES 0x906E -#define PCI_DEVICE_ID_PLX_9060SD 0x906D -#define PCI_DEVICE_ID_PLX_9080 0x9080 -#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 - -#define PCI_VENDOR_ID_MADGE 0x10b6 -#define PCI_DEVICE_ID_MADGE_MK2 0x0002 -#define PCI_DEVICE_ID_MADGE_C155S 0x1001 - -#define PCI_VENDOR_ID_3COM 0x10b7 -#define PCI_DEVICE_ID_3COM_3C985 0x0001 -#define PCI_DEVICE_ID_3COM_3C339 0x3390 -#define PCI_DEVICE_ID_3COM_3C590 0x5900 -#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 -#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 -#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 -#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 -#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 -#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 -#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 -#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 - -#define PCI_VENDOR_ID_SMC 0x10b8 -#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 - -#define PCI_VENDOR_ID_AL 0x10b9 -#define PCI_DEVICE_ID_AL_M1445 0x1445 -#define PCI_DEVICE_ID_AL_M1449 0x1449 -#define PCI_DEVICE_ID_AL_M1451 0x1451 -#define PCI_DEVICE_ID_AL_M1461 0x1461 -#define PCI_DEVICE_ID_AL_M1489 0x1489 -#define PCI_DEVICE_ID_AL_M1511 0x1511 -#define PCI_DEVICE_ID_AL_M1513 0x1513 -#define PCI_DEVICE_ID_AL_M1521 0x1521 -#define PCI_DEVICE_ID_AL_M1523 0x1523 -#define PCI_DEVICE_ID_AL_M1531 0x1531 -#define PCI_DEVICE_ID_AL_M1533 0x1533 -#define PCI_DEVICE_ID_AL_M1541 0x1541 -#define PCI_DEVICE_ID_AL_M1543 0x1543 -#define PCI_DEVICE_ID_AL_M3307 0x3307 -#define PCI_DEVICE_ID_AL_M4803 0x5215 -#define PCI_DEVICE_ID_AL_M5219 0x5219 -#define PCI_DEVICE_ID_AL_M5229 0x5229 -#define PCI_DEVICE_ID_AL_M5237 0x5237 -#define PCI_DEVICE_ID_AL_M5243 0x5243 -#define PCI_DEVICE_ID_AL_M7101 0x7101 - -#define PCI_VENDOR_ID_MITSUBISHI 0x10ba - -#define PCI_VENDOR_ID_SURECOM 0x10bd -#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 - -#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 - -#define PCI_VENDOR_ID_ASP 0x10cd -#define PCI_DEVICE_ID_ASP_ABP940 0x1200 -#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 -#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 - -#define PCI_VENDOR_ID_MACRONIX 0x10d9 -#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 -#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 - -#define PCI_VENDOR_ID_CERN 0x10dc -#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 -#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 -#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 -#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 - -#define PCI_VENDOR_ID_NVIDIA 0x10de -#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 -#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 -#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 -#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C -#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D -#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 - -#define PCI_VENDOR_ID_IMS 0x10e0 -#define PCI_DEVICE_ID_IMS_8849 0x8849 - -#define PCI_VENDOR_ID_TEKRAM2 0x10e1 -#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c - -#define PCI_VENDOR_ID_TUNDRA 0x10e3 -#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 - -#define PCI_VENDOR_ID_AMCC 0x10e8 -#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 -#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 -#define PCI_DEVICE_ID_AMCC_S5933 0x807d -#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c - -#define PCI_VENDOR_ID_INTERG 0x10ea -#define PCI_DEVICE_ID_INTERG_1680 0x1680 -#define PCI_DEVICE_ID_INTERG_1682 0x1682 -#define PCI_DEVICE_ID_INTERG_2000 0x2000 - -#define PCI_VENDOR_ID_REALTEK 0x10ec -#define PCI_DEVICE_ID_REALTEK_8029 0x8029 -#define PCI_DEVICE_ID_REALTEK_8129 0x8129 -#define PCI_DEVICE_ID_REALTEK_8139 0x8139 - -#define PCI_VENDOR_ID_TRUEVISION 0x10fa -#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c - -#define PCI_VENDOR_ID_INIT 0x1101 -#define PCI_DEVICE_ID_INIT_320P 0x9100 -#define PCI_DEVICE_ID_INIT_360P 0x9500 - -#define PCI_VENDOR_ID_TTI 0x1103 -#define PCI_DEVICE_ID_TTI_HPT343 0x0003 -#define PCI_DEVICE_ID_TTI_HPT366 0x0004 - -#define PCI_VENDOR_ID_VIA 0x1106 -#define PCI_DEVICE_ID_VIA_8501_0 0x0501 -#define PCI_DEVICE_ID_VIA_82C505 0x0505 -#define PCI_DEVICE_ID_VIA_82C561 0x0561 -#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 -#define PCI_DEVICE_ID_VIA_82C576 0x0576 -#define PCI_DEVICE_ID_VIA_82C585 0x0585 -#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 -#define PCI_DEVICE_ID_VIA_82C595 0x0595 -#define PCI_DEVICE_ID_VIA_82C596 0x0596 -#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 -#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 -#define PCI_DEVICE_ID_VIA_82C680 0x0680 -#define PCI_DEVICE_ID_VIA_82C686 0x0686 -#define PCI_DEVICE_ID_VIA_82C691 0x0691 -#define PCI_DEVICE_ID_VIA_82C693 0x0693 -#define PCI_DEVICE_ID_VIA_82C926 0x0926 -#define PCI_DEVICE_ID_VIA_82C416 0x1571 -#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 -#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 -#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 -#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 -#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 -#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 -#define PCI_DEVICE_ID_VIA_86C100A 0x6100 -#define PCI_DEVICE_ID_VIA_8501_1 0x8501 -#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 -#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 - -#define PCI_VENDOR_ID_SMC2 0x1113 -#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 - -#define PCI_VENDOR_ID_VORTEX 0x1119 -#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 -#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 -#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 -#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 -#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 -#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 -#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 -#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 -#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 -#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 -#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a -#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b -#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c -#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d -#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 -#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 -#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 -#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 -#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 -#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 -#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 -#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 -#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 -#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 -#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 -#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 -#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 -#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 -#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 -#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 -#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 -#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 - -#define PCI_VENDOR_ID_EF 0x111a -#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 -#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 - -#define PCI_VENDOR_ID_FORE 0x1127 -#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 -#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 - -#define PCI_VENDOR_ID_IMAGINGTECH 0x112f -#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 - -#define PCI_VENDOR_ID_PHILIPS 0x1131 -#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 -#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 - -#define PCI_VENDOR_ID_CYCLONE 0x113c -#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 - -#define PCI_VENDOR_ID_ALLIANCE 0x1142 -#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 -#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 -#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 -#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d - -#define PCI_VENDOR_ID_SK 0x1148 -#define PCI_DEVICE_ID_SK_FP 0x4000 -#define PCI_DEVICE_ID_SK_TR 0x4200 -#define PCI_DEVICE_ID_SK_GE 0x4300 - -#define PCI_VENDOR_ID_VMIC 0x114a -#define PCI_DEVICE_ID_VMIC_VME 0x7587 - -#define PCI_VENDOR_ID_DIGI 0x114f -#define PCI_DEVICE_ID_DIGI_EPC 0x0002 -#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 -#define PCI_DEVICE_ID_DIGI_XEM 0x0004 -#define PCI_DEVICE_ID_DIGI_XR 0x0005 -#define PCI_DEVICE_ID_DIGI_CX 0x0006 -#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 -#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a -#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 - -#define PCI_VENDOR_ID_MUTECH 0x1159 -#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 - -#define PCI_VENDOR_ID_RENDITION 0x1163 -#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 -#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 - -#define PCI_VENDOR_ID_TOSHIBA 0x1179 -#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 -#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a -#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f - -#define PCI_VENDOR_ID_RICOH 0x1180 -#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 -#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 -#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 -#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 - -#define PCI_VENDOR_ID_ARTOP 0x1191 -#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 -#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 - -#define PCI_VENDOR_ID_ZEITNET 0x1193 -#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 -#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 - -#define PCI_VENDOR_ID_OMEGA 0x119b -#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 - -#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 -#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 - -#define PCI_VENDOR_ID_GALILEO 0x11ab -#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146 - -#define PCI_VENDOR_ID_LITEON 0x11ad -#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 - -#define PCI_VENDOR_ID_V3 0x11b0 -#define PCI_DEVICE_ID_V3_V960 0x0001 -#define PCI_DEVICE_ID_V3_V350 0x0001 -#define PCI_DEVICE_ID_V3_V960V2 0x0002 -#define PCI_DEVICE_ID_V3_V350V2 0x0002 - -#define PCI_VENDOR_ID_NP 0x11bc -#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 - -#define PCI_VENDOR_ID_ATT 0x11c1 -#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 - -#define PCI_VENDOR_ID_SPECIALIX 0x11cb -#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 -#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 -#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 - -#define PCI_VENDOR_ID_AURAVISION 0x11d1 -#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 - -#define PCI_VENDOR_ID_IKON 0x11d5 -#define PCI_DEVICE_ID_IKON_10115 0x0115 -#define PCI_DEVICE_ID_IKON_10117 0x0117 - -#define PCI_VENDOR_ID_ZORAN 0x11de -#define PCI_DEVICE_ID_ZORAN_36057 0x6057 -#define PCI_DEVICE_ID_ZORAN_36120 0x6120 - -#define PCI_VENDOR_ID_KINETIC 0x11f4 -#define PCI_DEVICE_ID_KINETIC_2915 0x2915 - -#define PCI_VENDOR_ID_COMPEX 0x11f6 -#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 -#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 - -#define PCI_VENDOR_ID_RP 0x11fe -#define PCI_DEVICE_ID_RP32INTF 0x0001 -#define PCI_DEVICE_ID_RP8INTF 0x0002 -#define PCI_DEVICE_ID_RP16INTF 0x0003 -#define PCI_DEVICE_ID_RP4QUAD 0x0004 -#define PCI_DEVICE_ID_RP8OCTA 0x0005 -#define PCI_DEVICE_ID_RP8J 0x0006 -#define PCI_DEVICE_ID_RPP4 0x000A -#define PCI_DEVICE_ID_RPP8 0x000B -#define PCI_DEVICE_ID_RP8M 0x000C - -#define PCI_VENDOR_ID_CYCLADES 0x120e -#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 -#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 -#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 -#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 -#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 -#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 -#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 -#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 - -#define PCI_VENDOR_ID_ESSENTIAL 0x120f -#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 - -#define PCI_VENDOR_ID_O2 0x1217 -#define PCI_DEVICE_ID_O2_6729 0x6729 -#define PCI_DEVICE_ID_O2_6730 0x673a -#define PCI_DEVICE_ID_O2_6832 0x6832 -#define PCI_DEVICE_ID_O2_6836 0x6836 - -#define PCI_VENDOR_ID_3DFX 0x121a -#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 -#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 -#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 -#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 - -#define PCI_VENDOR_ID_SIGMADES 0x1236 -#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 - -#define PCI_VENDOR_ID_CCUBE 0x123f - -#define PCI_VENDOR_ID_AVM 0x1244 -#define PCI_DEVICE_ID_AVM_A1 0x0a00 - -#define PCI_VENDOR_ID_DIPIX 0x1246 - -#define PCI_VENDOR_ID_STALLION 0x124d -#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 -#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 -#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 - -#define PCI_VENDOR_ID_OPTIBASE 0x1255 -#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 -#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 -#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 -#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 -#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 - -#define PCI_VENDOR_ID_ESS 0x125d -#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 - -#define PCI_VENDOR_ID_SATSAGEM 0x1267 -#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 -#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b - -#define PCI_VENDOR_ID_HUGHES 0x1273 -#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 - -#define PCI_VENDOR_ID_ENSONIQ 0x1274 -#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 -#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 - -#define PCI_VENDOR_ID_ALTEON 0x12ae -#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 - -#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 -#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 - -#define PCI_VENDOR_ID_PICTUREL 0x12c5 -#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 - -#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 -#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 - -#define PCI_VENDOR_ID_CBOARDS 0x1307 -#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 - -#define PCI_VENDOR_ID_SIIG 0x131f -#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 -#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 -#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 -#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 -#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 -#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 -#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 -#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 -#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 -#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 -#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 -#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 -#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 -#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 -#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 -#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 -#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 -#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 -#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 - -#define PCI_VENDOR_ID_SEALEVEL 0x135e -#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 -#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 -#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 -#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 -#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 -#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 - -#define PCI_VENDOR_ID_NETGEAR 0x1385 -#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a - -#define PCI_VENDOR_ID_LAVA 0x1407 -#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 -#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ -#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ - -#define PCI_VENDOR_ID_PANACOM 0x14d4 -#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 -#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 - -#define PCI_VENDOR_ID_SYMPHONY 0x1c1c -#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 - -#define PCI_VENDOR_ID_TEKRAM 0x1de1 -#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 - -#define PCI_VENDOR_ID_3DLABS 0x3d3d -#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 -#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 -#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 -#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 -#define PCI_DEVICE_ID_3DLABS_MX 0x0006 - -#define PCI_VENDOR_ID_AVANCE 0x4005 -#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 -#define PCI_DEVICE_ID_AVANCE_2302 0x2302 - -#define PCI_VENDOR_ID_NETVIN 0x4a14 -#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 - -#define PCI_VENDOR_ID_S3 0x5333 -#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 -#define PCI_DEVICE_ID_S3_ViRGE 0x5631 -#define PCI_DEVICE_ID_S3_TRIO 0x8811 -#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 -#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 -#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d -#define PCI_DEVICE_ID_S3_868 0x8880 -#define PCI_DEVICE_ID_S3_928 0x88b0 -#define PCI_DEVICE_ID_S3_864_1 0x88c0 -#define PCI_DEVICE_ID_S3_864_2 0x88c1 -#define PCI_DEVICE_ID_S3_964_1 0x88d0 -#define PCI_DEVICE_ID_S3_964_2 0x88d1 -#define PCI_DEVICE_ID_S3_968 0x88f0 -#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 -#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 -#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 -#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 -#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 -#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 -#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 -#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 - -#define PCI_VENDOR_ID_DCI 0x6666 -#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 - -#define PCI_VENDOR_ID_GENROCO 0x5555 -#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 - -#define PCI_VENDOR_ID_INTEL 0x8086 -#define PCI_DEVICE_ID_INTEL_21145 0x0039 -#define PCI_DEVICE_ID_INTEL_82375 0x0482 -#define PCI_DEVICE_ID_INTEL_82424 0x0483 -#define PCI_DEVICE_ID_INTEL_82378 0x0484 -#define PCI_DEVICE_ID_INTEL_82430 0x0486 -#define PCI_DEVICE_ID_INTEL_82434 0x04a3 -#define PCI_DEVICE_ID_INTEL_I960 0x0960 -#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 -#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 -#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 -#define PCI_DEVICE_ID_INTEL_7116 0x1223 -#define PCI_DEVICE_ID_INTEL_82596 0x1226 -#define PCI_DEVICE_ID_INTEL_82865 0x1227 -#define PCI_DEVICE_ID_INTEL_82557 0x1229 -#define PCI_DEVICE_ID_INTEL_82437 0x122d -#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e -#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 -#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 -#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 -#define PCI_DEVICE_ID_INTEL_82441 0x1237 -#define PCI_DEVICE_ID_INTEL_82380FB 0x124b -#define PCI_DEVICE_ID_INTEL_82439 0x1250 -#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 -#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 -#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 -#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 -#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 -#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 -#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 -#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 -#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 -#define PCI_VENDOR_ID_COMPUTONE 0x8e0e -#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 - -#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 -#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 -#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 -#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 -#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 -#define PCI_DEVICE_ID_INTEL_P6 0x84c4 -#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 -#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca - -#define PCI_VENDOR_ID_KTI 0x8e2e -#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 - -#define PCI_VENDOR_ID_ADAPTEC 0x9004 -#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 -#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 -#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 -#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 -#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 -#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 -#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 -#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 -#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 -#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 -#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 -#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 -#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 -#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 -#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 -#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 -#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 -#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 -#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 -#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 -#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 -#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 -#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 -#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 -#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 -#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 - -#define PCI_VENDOR_ID_ADAPTEC2 0x9005 -#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 -#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 -#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 -#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f -#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 -#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 -#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f -#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 -#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 -#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 -#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f -#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 -#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 -#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 -#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf - -#define PCI_VENDOR_ID_ATRONICS 0x907f -#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 - -#define PCI_VENDOR_ID_HOLTEK 0x9412 -#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 - -#define PCI_VENDOR_ID_TIGERJET 0xe159 -#define PCI_DEVICE_ID_TIGERJET_300 0x0001 - -#define PCI_VENDOR_ID_ARK 0xedd8 -#define PCI_DEVICE_ID_ARK_STING 0xa091 -#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 -#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 - -#define PCI_VENDOR_ID_INTERPHASE 0x107e -#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 -#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 - -#define PCI_VENDOR_ID_INTERPHASE 0x107e -#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 -#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 - -#define PCI_VENDOR_ID_INTERPHASE 0x107e -#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 -#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 +#include <linux/pci_ids.h> /* * The PCI interface treats multi-function devices as independent @@ -1372,6 +284,8 @@ #include <linux/config.h> #include <linux/ioport.h> +#include <asm/pci.h> + #define DEVICE_COUNT_COMPATIBLE 4 #define DEVICE_COUNT_IRQ 2 #define DEVICE_COUNT_DMA 2 @@ -1397,7 +311,8 @@ struct pci_dev { unsigned short subsystem_vendor; unsigned short subsystem_device; unsigned int class; /* 3 bytes: (base,sub,prog-if) */ - unsigned int hdr_type; /* PCI header type */ + u8 hdr_type; /* PCI header type (`multi' flag masked out) */ + u8 rom_base_reg; /* Which config register controls the ROM */ unsigned short regs; @@ -1415,6 +330,7 @@ struct pci_dev { struct resource irq_resource[DEVICE_COUNT_IRQ]; char name[48]; /* Device name */ + char slot_name[8]; /* Slot name */ int (*prepare)(struct pci_dev *dev); int (*activate)(struct pci_dev *dev); @@ -1491,11 +407,11 @@ struct pci_ops { void pcibios_init(void); void pcibios_fixup_bus(struct pci_bus *); char *pcibios_setup (char *str); + void pcibios_update_resource(struct pci_dev *, struct resource *, struct resource *, int); void pcibios_update_irq(struct pci_dev *, int irq); - /* Backward compatibility, don't use in new code! */ int pcibios_present(void); @@ -1525,6 +441,7 @@ int get_pci_list(char *buf); int pci_proc_attach_device(struct pci_dev *dev); int pci_proc_detach_device(struct pci_dev *dev); void pci_name_device(struct pci_dev *dev); +void pci_read_bridge_bases(struct pci_bus *child); struct resource *pci_find_parent_resource(struct pci_dev *dev, struct resource *res); struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, struct pci_dev *from); @@ -1535,13 +452,6 @@ struct pci_dev *pci_find_class (unsigned int class, struct pci_dev *from); struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); int pci_find_capability (struct pci_dev *dev, int cap); -int pci_assign_resource(struct pci_dev *dev, int i); -int pci_claim_resource(struct pci_dev *, int); -void pci_assign_unassigned_resources(u32 min_io, u32 min_mem); -void pci_set_bus_ranges(void); -void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), - int (*)(struct pci_dev *, u8, u8)); - #define PCI_ANY_ID (~0) int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val); @@ -1552,9 +462,42 @@ int pci_write_config_word(struct pci_dev *dev, int where, u16 val); int pci_write_config_dword(struct pci_dev *dev, int where, u32 val); void pci_set_master(struct pci_dev *dev); +/* Helper functions (drivers/pci/setup.c) */ + +int pci_claim_resource(struct pci_dev *, int); +void pci_assign_unassigned_resources(u32 min_io, u32 min_mem); +void pci_set_bus_ranges(void); +void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), + int (*)(struct pci_dev *, u8, u8)); + +/* + * simple PCI probing for drivers + */ + +struct pci_simple_probe_entry; +typedef int (*pci_simple_probe_callback) (struct pci_dev *dev, int match_num, + const struct pci_simple_probe_entry *ent, + void *drvr_data); + +struct pci_simple_probe_entry { + unsigned short vendor; /* vendor id, PCI_ANY_ID, or 0 for last entry */ + unsigned short device; /* device id, PCI_ANY_ID, or 0 for last entry */ + unsigned short subsys_vendor; /* subsystem vendor id, 0 for don't care */ + unsigned short subsys_device; /* subsystem device id, 0 for don't care */ + void *dev_data; /* driver-private, entry-specific data */ +}; + +int pci_simple_probe (struct pci_simple_probe_entry *list, size_t match_limit, + pci_simple_probe_callback cb, void *drvr_data); + + + +/* + * If the system does not have PCI, clearly these return errors. Define + * these as simple inline functions to avoid hair in drivers. + */ + #ifndef CONFIG_PCI -/* If the system does not have PCI, clearly these return errors. Define - these as simple inline functions to avoid hair in drivers. */ extern inline int pcibios_present(void) { return 0; } #define _PCI_NOP(o,s,t) \ @@ -1577,9 +520,16 @@ extern inline struct pci_dev *pci_find_class(unsigned int class, struct pci_dev extern inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn) { return NULL; } +extern inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device, +unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from) +{ return NULL; } + extern inline void pci_set_master(struct pci_dev *dev) { return; } +extern inline int pci_simple_probe (struct pci_simple_probe_entry *list, size_t match_limit, + pci_simple_probe_callback cb, void *drvr_data) +{ return 0; } #endif /* !CONFIG_PCI */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h new file mode 100644 index 000000000..94b391282 --- /dev/null +++ b/include/linux/pci_ids.h @@ -0,0 +1,1098 @@ +/* + * PCI Class, Vendor and Device IDs + * + * Please keep sorted. + */ + +/* Device classes and subclasses */ + +#define PCI_CLASS_NOT_DEFINED 0x0000 +#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 + +#define PCI_BASE_CLASS_STORAGE 0x01 +#define PCI_CLASS_STORAGE_SCSI 0x0100 +#define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_FLOPPY 0x0102 +#define PCI_CLASS_STORAGE_IPI 0x0103 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_OTHER 0x0180 + +#define PCI_BASE_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200 +#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 +#define PCI_CLASS_NETWORK_FDDI 0x0202 +#define PCI_CLASS_NETWORK_ATM 0x0203 +#define PCI_CLASS_NETWORK_OTHER 0x0280 + +#define PCI_BASE_CLASS_DISPLAY 0x03 +#define PCI_CLASS_DISPLAY_VGA 0x0300 +#define PCI_CLASS_DISPLAY_XGA 0x0301 +#define PCI_CLASS_DISPLAY_OTHER 0x0380 + +#define PCI_BASE_CLASS_MULTIMEDIA 0x04 +#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 +#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 + +#define PCI_BASE_CLASS_MEMORY 0x05 +#define PCI_CLASS_MEMORY_RAM 0x0500 +#define PCI_CLASS_MEMORY_FLASH 0x0501 +#define PCI_CLASS_MEMORY_OTHER 0x0580 + +#define PCI_BASE_CLASS_BRIDGE 0x06 +#define PCI_CLASS_BRIDGE_HOST 0x0600 +#define PCI_CLASS_BRIDGE_ISA 0x0601 +#define PCI_CLASS_BRIDGE_EISA 0x0602 +#define PCI_CLASS_BRIDGE_MC 0x0603 +#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 +#define PCI_CLASS_BRIDGE_NUBUS 0x0606 +#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 +#define PCI_CLASS_BRIDGE_OTHER 0x0680 + +#define PCI_BASE_CLASS_COMMUNICATION 0x07 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 +#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 + +#define PCI_BASE_CLASS_SYSTEM 0x08 +#define PCI_CLASS_SYSTEM_PIC 0x0800 +#define PCI_CLASS_SYSTEM_DMA 0x0801 +#define PCI_CLASS_SYSTEM_TIMER 0x0802 +#define PCI_CLASS_SYSTEM_RTC 0x0803 +#define PCI_CLASS_SYSTEM_OTHER 0x0880 + +#define PCI_BASE_CLASS_INPUT 0x09 +#define PCI_CLASS_INPUT_KEYBOARD 0x0900 +#define PCI_CLASS_INPUT_PEN 0x0901 +#define PCI_CLASS_INPUT_MOUSE 0x0902 +#define PCI_CLASS_INPUT_OTHER 0x0980 + +#define PCI_BASE_CLASS_DOCKING 0x0a +#define PCI_CLASS_DOCKING_GENERIC 0x0a00 +#define PCI_CLASS_DOCKING_OTHER 0x0a01 + +#define PCI_BASE_CLASS_PROCESSOR 0x0b +#define PCI_CLASS_PROCESSOR_386 0x0b00 +#define PCI_CLASS_PROCESSOR_486 0x0b01 +#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 +#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 +#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 +#define PCI_CLASS_PROCESSOR_CO 0x0b40 + +#define PCI_BASE_CLASS_SERIAL 0x0c +#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 +#define PCI_CLASS_SERIAL_ACCESS 0x0c01 +#define PCI_CLASS_SERIAL_SSA 0x0c02 +#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_FIBER 0x0c04 + +#define PCI_BASE_CLASS_INTELLIGENT 0x0e +#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 + +#define PCI_CLASS_HOT_SWAP_CONTROLLER 0xff00 + +#define PCI_CLASS_OTHERS 0xff + +/* Vendors and devices. Sort key: vendor first, device next. */ + +#define PCI_VENDOR_ID_COMPAQ 0x0e11 +#define PCI_DEVICE_ID_COMPAQ_TOKENRING 0x0508 +#define PCI_DEVICE_ID_COMPAQ_1280 0x3033 +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX 0x4000 +#define PCI_DEVICE_ID_COMPAQ_SMART2P 0xae10 +#define PCI_DEVICE_ID_COMPAQ_NETEL100 0xae32 +#define PCI_DEVICE_ID_COMPAQ_NETEL10 0xae34 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35 +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40 +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43 +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011 +#define PCI_DEVICE_ID_COMPAQ_THUNDER 0xf130 +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150 + +#define PCI_VENDOR_ID_NCR 0x1000 +#define PCI_DEVICE_ID_NCR_53C810 0x0001 +#define PCI_DEVICE_ID_NCR_53C820 0x0002 +#define PCI_DEVICE_ID_NCR_53C825 0x0003 +#define PCI_DEVICE_ID_NCR_53C815 0x0004 +#define PCI_DEVICE_ID_NCR_53C860 0x0006 +#define PCI_DEVICE_ID_NCR_53C896 0x000b +#define PCI_DEVICE_ID_NCR_53C895 0x000c +#define PCI_DEVICE_ID_NCR_53C885 0x000d +#define PCI_DEVICE_ID_NCR_53C875 0x000f +#define PCI_DEVICE_ID_NCR_53C1510 0x0010 +#define PCI_DEVICE_ID_NCR_53C875J 0x008f + +#define PCI_VENDOR_ID_ATI 0x1002 +#define PCI_DEVICE_ID_ATI_68800 0x4158 +#define PCI_DEVICE_ID_ATI_215CT222 0x4354 +#define PCI_DEVICE_ID_ATI_210888CX 0x4358 +#define PCI_DEVICE_ID_ATI_215GB 0x4742 +#define PCI_DEVICE_ID_ATI_215GD 0x4744 +#define PCI_DEVICE_ID_ATI_215GI 0x4749 +#define PCI_DEVICE_ID_ATI_215GP 0x4750 +#define PCI_DEVICE_ID_ATI_215GQ 0x4751 +#define PCI_DEVICE_ID_ATI_215GT 0x4754 +#define PCI_DEVICE_ID_ATI_215GTB 0x4755 +#define PCI_DEVICE_ID_ATI_210888GX 0x4758 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_264VT 0x5654 + +#define PCI_VENDOR_ID_VLSI 0x1004 +#define PCI_DEVICE_ID_VLSI_82C592 0x0005 +#define PCI_DEVICE_ID_VLSI_82C593 0x0006 +#define PCI_DEVICE_ID_VLSI_82C594 0x0007 +#define PCI_DEVICE_ID_VLSI_82C597 0x0009 +#define PCI_DEVICE_ID_VLSI_82C541 0x000c +#define PCI_DEVICE_ID_VLSI_82C543 0x000d +#define PCI_DEVICE_ID_VLSI_82C532 0x0101 +#define PCI_DEVICE_ID_VLSI_82C534 0x0102 +#define PCI_DEVICE_ID_VLSI_82C535 0x0104 +#define PCI_DEVICE_ID_VLSI_82C147 0x0105 +#define PCI_DEVICE_ID_VLSI_VAS96011 0x0702 + +#define PCI_VENDOR_ID_ADL 0x1005 +#define PCI_DEVICE_ID_ADL_2301 0x2301 + +#define PCI_VENDOR_ID_NS 0x100b +#define PCI_DEVICE_ID_NS_87415 0x0002 +#define PCI_DEVICE_ID_NS_87410 0xd001 + +#define PCI_VENDOR_ID_TSENG 0x100c +#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202 +#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205 +#define PCI_DEVICE_ID_TSENG_W32P_c 0x3206 +#define PCI_DEVICE_ID_TSENG_W32P_d 0x3207 +#define PCI_DEVICE_ID_TSENG_ET6000 0x3208 + +#define PCI_VENDOR_ID_WEITEK 0x100e +#define PCI_DEVICE_ID_WEITEK_P9000 0x9001 +#define PCI_DEVICE_ID_WEITEK_P9100 0x9100 + +#define PCI_VENDOR_ID_DEC 0x1011 +#define PCI_DEVICE_ID_DEC_BRD 0x0001 +#define PCI_DEVICE_ID_DEC_TULIP 0x0002 +#define PCI_DEVICE_ID_DEC_TGA 0x0004 +#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009 +#define PCI_DEVICE_ID_DEC_TGA2 0x000D +#define PCI_DEVICE_ID_DEC_FDDI 0x000F +#define PCI_DEVICE_ID_DEC_TULIP_PLUS 0x0014 +#define PCI_DEVICE_ID_DEC_21142 0x0019 +#define PCI_DEVICE_ID_DEC_21052 0x0021 +#define PCI_DEVICE_ID_DEC_21150 0x0022 +#define PCI_DEVICE_ID_DEC_21152 0x0024 +#define PCI_DEVICE_ID_DEC_21153 0x0025 +#define PCI_DEVICE_ID_DEC_21154 0x0026 +#define PCI_DEVICE_ID_DEC_21285 0x1065 +#define PCI_DEVICE_ID_COMPAQ_42XX 0x0046 + +#define PCI_VENDOR_ID_CIRRUS 0x1013 +#define PCI_DEVICE_ID_CIRRUS_7548 0x0038 +#define PCI_DEVICE_ID_CIRRUS_5430 0x00a0 +#define PCI_DEVICE_ID_CIRRUS_5434_4 0x00a4 +#define PCI_DEVICE_ID_CIRRUS_5434_8 0x00a8 +#define PCI_DEVICE_ID_CIRRUS_5436 0x00ac +#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 +#define PCI_DEVICE_ID_CIRRUS_5480 0x00bc +#define PCI_DEVICE_ID_CIRRUS_5462 0x00d0 +#define PCI_DEVICE_ID_CIRRUS_5464 0x00d4 +#define PCI_DEVICE_ID_CIRRUS_5465 0x00d6 +#define PCI_DEVICE_ID_CIRRUS_6729 0x1100 +#define PCI_DEVICE_ID_CIRRUS_6832 0x1110 +#define PCI_DEVICE_ID_CIRRUS_7542 0x1200 +#define PCI_DEVICE_ID_CIRRUS_7543 0x1202 +#define PCI_DEVICE_ID_CIRRUS_7541 0x1204 + +#define PCI_VENDOR_ID_IBM 0x1014 +#define PCI_DEVICE_ID_IBM_FIRE_CORAL 0x000a +#define PCI_DEVICE_ID_IBM_TR 0x0018 +#define PCI_DEVICE_ID_IBM_82G2675 0x001d +#define PCI_DEVICE_ID_IBM_MCA 0x0020 +#define PCI_DEVICE_ID_IBM_82351 0x0022 +#define PCI_DEVICE_ID_IBM_PYTHON 0x002d +#define PCI_DEVICE_ID_IBM_SERVERAID 0x002e +#define PCI_DEVICE_ID_IBM_TR_WAKE 0x003e +#define PCI_DEVICE_ID_IBM_MPIC 0x0046 +#define PCI_DEVICE_ID_IBM_3780IDSP 0x007d +#define PCI_DEVICE_ID_IBM_MPIC_2 0xffff + +#define PCI_VENDOR_ID_WD 0x101c +#define PCI_DEVICE_ID_WD_7197 0x3296 + +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 + +#define PCI_VENDOR_ID_TRIDENT 0x1023 +#define PCI_DEVICE_ID_TRIDENT_9320 0x9320 +#define PCI_DEVICE_ID_TRIDENT_9388 0x9388 +#define PCI_DEVICE_ID_TRIDENT_9397 0x9397 +#define PCI_DEVICE_ID_TRIDENT_939A 0x939A +#define PCI_DEVICE_ID_TRIDENT_9520 0x9520 +#define PCI_DEVICE_ID_TRIDENT_9525 0x9525 +#define PCI_DEVICE_ID_TRIDENT_9420 0x9420 +#define PCI_DEVICE_ID_TRIDENT_9440 0x9440 +#define PCI_DEVICE_ID_TRIDENT_9660 0x9660 +#define PCI_DEVICE_ID_TRIDENT_9750 0x9750 +#define PCI_DEVICE_ID_TRIDENT_9850 0x9850 +#define PCI_DEVICE_ID_TRIDENT_9880 0x9880 +#define PCI_DEVICE_ID_TRIDENT_8400 0x8400 +#define PCI_DEVICE_ID_TRIDENT_8420 0x8420 +#define PCI_DEVICE_ID_TRIDENT_8500 0x8500 + +#define PCI_VENDOR_ID_AI 0x1025 +#define PCI_DEVICE_ID_AI_M1435 0x1435 + +#define PCI_VENDOR_ID_MATROX 0x102B +#define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 +#define PCI_DEVICE_ID_MATROX_MIL 0x0519 +#define PCI_DEVICE_ID_MATROX_MYS 0x051A +#define PCI_DEVICE_ID_MATROX_MIL_2 0x051b +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f +#define PCI_DEVICE_ID_MATROX_MGA_IMP 0x0d10 +#define PCI_DEVICE_ID_MATROX_G100_MM 0x1000 +#define PCI_DEVICE_ID_MATROX_G100_AGP 0x1001 +#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 +#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 +#define PCI_DEVICE_ID_MATROX_G400 0x0525 +#define PCI_DEVICE_ID_MATROX_VIA 0x4536 + +#define PCI_VENDOR_ID_CT 0x102c +#define PCI_DEVICE_ID_CT_65545 0x00d8 +#define PCI_DEVICE_ID_CT_65548 0x00dc +#define PCI_DEVICE_ID_CT_65550 0x00e0 +#define PCI_DEVICE_ID_CT_65554 0x00e4 +#define PCI_DEVICE_ID_CT_65555 0x00e5 + +#define PCI_VENDOR_ID_MIRO 0x1031 +#define PCI_DEVICE_ID_MIRO_36050 0x5601 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_PCX2 0x0046 + +#define PCI_VENDOR_ID_FD 0x1036 +#define PCI_DEVICE_ID_FD_36C70 0x0000 + +#define PCI_VENDOR_ID_SI 0x1039 +#define PCI_DEVICE_ID_SI_5591_AGP 0x0001 +#define PCI_DEVICE_ID_SI_6202 0x0002 +#define PCI_DEVICE_ID_SI_503 0x0008 +#define PCI_DEVICE_ID_SI_ACPI 0x0009 +#define PCI_DEVICE_ID_SI_5597_VGA 0x0200 +#define PCI_DEVICE_ID_SI_6205 0x0205 +#define PCI_DEVICE_ID_SI_501 0x0406 +#define PCI_DEVICE_ID_SI_496 0x0496 +#define PCI_DEVICE_ID_SI_530 0x0530 +#define PCI_DEVICE_ID_SI_601 0x0601 +#define PCI_DEVICE_ID_SI_620 0x0620 +#define PCI_DEVICE_ID_SI_5107 0x5107 +#define PCI_DEVICE_ID_SI_5511 0x5511 +#define PCI_DEVICE_ID_SI_5513 0x5513 +#define PCI_DEVICE_ID_SI_5571 0x5571 +#define PCI_DEVICE_ID_SI_5591 0x5591 +#define PCI_DEVICE_ID_SI_5597 0x5597 +#define PCI_DEVICE_ID_SI_5600 0x5600 +#define PCI_DEVICE_ID_SI_6306 0x6306 +#define PCI_DEVICE_ID_SI_6326 0x6326 +#define PCI_DEVICE_ID_SI_7001 0x7001 + +#define PCI_VENDOR_ID_HP 0x103c +#define PCI_DEVICE_ID_HP_J2585A 0x1030 +#define PCI_DEVICE_ID_HP_J2585B 0x1031 + +#define PCI_VENDOR_ID_PCTECH 0x1042 +#define PCI_DEVICE_ID_PCTECH_RZ1000 0x1000 +#define PCI_DEVICE_ID_PCTECH_RZ1001 0x1001 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010 +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020 + +#define PCI_VENDOR_ID_DPT 0x1044 +#define PCI_DEVICE_ID_DPT 0xa400 + +#define PCI_VENDOR_ID_OPTI 0x1045 +#define PCI_DEVICE_ID_OPTI_92C178 0xc178 +#define PCI_DEVICE_ID_OPTI_82C557 0xc557 +#define PCI_DEVICE_ID_OPTI_82C558 0xc558 +#define PCI_DEVICE_ID_OPTI_82C621 0xc621 +#define PCI_DEVICE_ID_OPTI_82C700 0xc700 +#define PCI_DEVICE_ID_OPTI_82C701 0xc701 +#define PCI_DEVICE_ID_OPTI_82C814 0xc814 +#define PCI_DEVICE_ID_OPTI_82C822 0xc822 +#define PCI_DEVICE_ID_OPTI_82C861 0xc861 +#define PCI_DEVICE_ID_OPTI_82C825 0xd568 + +#define PCI_VENDOR_ID_SGS 0x104a +#define PCI_DEVICE_ID_SGS_2000 0x0008 +#define PCI_DEVICE_ID_SGS_1764 0x0009 + +#define PCI_VENDOR_ID_BUSLOGIC 0x104B +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140 +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER 0x1040 +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT 0x8130 + +#define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TVP4010 0x3d04 +#define PCI_DEVICE_ID_TI_TVP4020 0x3d07 +#define PCI_DEVICE_ID_TI_PCI1130 0xac12 +#define PCI_DEVICE_ID_TI_PCI1031 0xac13 +#define PCI_DEVICE_ID_TI_PCI1131 0xac15 +#define PCI_DEVICE_ID_TI_PCI1250 0xac16 +#define PCI_DEVICE_ID_TI_PCI1220 0xac17 + +#define PCI_VENDOR_ID_OAK 0x104e +#define PCI_DEVICE_ID_OAK_OTI107 0x0107 + +/* Winbond have two vendor IDs! See 0x10ad as well */ +#define PCI_VENDOR_ID_WINBOND2 0x1050 +#define PCI_DEVICE_ID_WINBOND2_89C940 0x0940 +#define PCI_DEVICE_ID_WINBOND2_89C940F 0x5a5a + +#define PCI_VENDOR_ID_MOTOROLA 0x1057 +#define PCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 +#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001 +#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 +#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 +#define PCI_DEVICE_ID_MOTOROLA_FALCON 0x4802 +#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806 + +#define PCI_VENDOR_ID_PROMISE 0x105a +#define PCI_DEVICE_ID_PROMISE_20246 0x4d33 +#define PCI_DEVICE_ID_PROMISE_20262 0x4d38 +#define PCI_DEVICE_ID_PROMISE_5300 0x5300 + +#define PCI_VENDOR_ID_N9 0x105d +#define PCI_DEVICE_ID_N9_I128 0x2309 +#define PCI_DEVICE_ID_N9_I128_2 0x2339 +#define PCI_DEVICE_ID_N9_I128_T2R 0x493d + +#define PCI_VENDOR_ID_UMC 0x1060 +#define PCI_DEVICE_ID_UMC_UM8673F 0x0101 +#define PCI_DEVICE_ID_UMC_UM8891A 0x0891 +#define PCI_DEVICE_ID_UMC_UM8886BF 0x673a +#define PCI_DEVICE_ID_UMC_UM8886A 0x886a +#define PCI_DEVICE_ID_UMC_UM8881F 0x8881 +#define PCI_DEVICE_ID_UMC_UM8886F 0x8886 +#define PCI_DEVICE_ID_UMC_UM9017F 0x9017 +#define PCI_DEVICE_ID_UMC_UM8886N 0xe886 +#define PCI_DEVICE_ID_UMC_UM8891N 0xe891 + +#define PCI_VENDOR_ID_X 0x1061 +#define PCI_DEVICE_ID_X_AGX016 0x0001 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 + +#define PCI_VENDOR_ID_MYLEX 0x1069 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 + +#define PCI_VENDOR_ID_PICOP 0x1066 +#define PCI_DEVICE_ID_PICOP_PT86C52X 0x0001 +#define PCI_DEVICE_ID_PICOP_PT80C524 0x8002 + +#define PCI_VENDOR_ID_APPLE 0x106b +#define PCI_DEVICE_ID_APPLE_BANDIT 0x0001 +#define PCI_DEVICE_ID_APPLE_GC 0x0002 +#define PCI_DEVICE_ID_APPLE_HYDRA 0x000e + +#define PCI_VENDOR_ID_NEXGEN 0x1074 +#define PCI_DEVICE_ID_NEXGEN_82C501 0x4e78 + +#define PCI_VENDOR_ID_QLOGIC 0x1077 +#define PCI_DEVICE_ID_QLOGIC_ISP1020 0x1020 +#define PCI_DEVICE_ID_QLOGIC_ISP1022 0x1022 +#define PCI_DEVICE_ID_QLOGIC_ISP2100 0x2100 +#define PCI_DEVICE_ID_QLOGIC_ISP2200 0x2200 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_DEVICE_ID_CYRIX_5510 0x0000 +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001 +#define PCI_DEVICE_ID_CYRIX_5520 0x0002 +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100 +#define PCI_DEVICE_ID_CYRIX_5530_SMI 0x0101 +#define PCI_DEVICE_ID_CYRIX_5530_IDE 0x0102 +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103 +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104 + +#define PCI_VENDOR_ID_LEADTEK 0x107d +#define PCI_DEVICE_ID_LEADTEK_805 0x0000 + +#define PCI_VENDOR_ID_CONTAQ 0x1080 +#define PCI_DEVICE_ID_CONTAQ_82C599 0x0600 +#define PCI_DEVICE_ID_CONTAQ_82C693 0xc693 + +#define PCI_VENDOR_ID_FOREX 0x1083 + +#define PCI_VENDOR_ID_OLICOM 0x108d +#define PCI_DEVICE_ID_OLICOM_OC3136 0x0001 +#define PCI_DEVICE_ID_OLICOM_OC2315 0x0011 +#define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 +#define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 +#define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 +#define PCI_DEVICE_ID_OLICOM_OC6151 0x0021 + +#define PCI_VENDOR_ID_SUN 0x108e +#define PCI_DEVICE_ID_SUN_EBUS 0x1000 +#define PCI_DEVICE_ID_SUN_HAPPYMEAL 0x1001 +#define PCI_DEVICE_ID_SUN_SIMBA 0x5000 +#define PCI_DEVICE_ID_SUN_PBM 0x8000 +#define PCI_DEVICE_ID_SUN_SABRE 0xa000 + +#define PCI_VENDOR_ID_CMD 0x1095 +#define PCI_DEVICE_ID_CMD_640 0x0640 +#define PCI_DEVICE_ID_CMD_643 0x0643 +#define PCI_DEVICE_ID_CMD_646 0x0646 +#define PCI_DEVICE_ID_CMD_647 0x0647 +#define PCI_DEVICE_ID_CMD_670 0x0670 + +#define PCI_VENDOR_ID_VISION 0x1098 +#define PCI_DEVICE_ID_VISION_QD8500 0x0001 +#define PCI_DEVICE_ID_VISION_QD8580 0x0002 + +#define PCI_VENDOR_ID_BROOKTREE 0x109e +#define PCI_DEVICE_ID_BROOKTREE_848 0x0350 +#define PCI_DEVICE_ID_BROOKTREE_849A 0x0351 +#define PCI_DEVICE_ID_BROOKTREE_878_1 0x036e +#define PCI_DEVICE_ID_BROOKTREE_878 0x0878 +#define PCI_DEVICE_ID_BROOKTREE_8474 0x8474 + +#define PCI_VENDOR_ID_SIERRA 0x10a8 +#define PCI_DEVICE_ID_SIERRA_STB 0x0000 + +#define PCI_VENDOR_ID_SGI 0x10a9 +#define PCI_DEVICE_ID_SGI_IOC3 0x0003 + +#define PCI_VENDOR_ID_ACC 0x10aa +#define PCI_DEVICE_ID_ACC_2056 0x0000 + +#define PCI_VENDOR_ID_WINBOND 0x10ad +#define PCI_DEVICE_ID_WINBOND_83769 0x0001 +#define PCI_DEVICE_ID_WINBOND_82C105 0x0105 +#define PCI_DEVICE_ID_WINBOND_83C553 0x0565 + +#define PCI_VENDOR_ID_DATABOOK 0x10b3 +#define PCI_DEVICE_ID_DATABOOK_87144 0xb106 + +#define PCI_VENDOR_ID_PLX 0x10b5 +#define PCI_DEVICE_ID_PLX_SPCOM200 0x1103 +#define PCI_DEVICE_ID_PLX_9050 0x9050 +#define PCI_DEVICE_ID_PLX_9060 0x9060 +#define PCI_DEVICE_ID_PLX_9060ES 0x906E +#define PCI_DEVICE_ID_PLX_9060SD 0x906D +#define PCI_DEVICE_ID_PLX_9080 0x9080 +#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001 + +#define PCI_VENDOR_ID_MADGE 0x10b6 +#define PCI_DEVICE_ID_MADGE_MK2 0x0002 +#define PCI_DEVICE_ID_MADGE_C155S 0x1001 + +#define PCI_VENDOR_ID_3COM 0x10b7 +#define PCI_DEVICE_ID_3COM_3C985 0x0001 +#define PCI_DEVICE_ID_3COM_3C339 0x3390 +#define PCI_DEVICE_ID_3COM_3C590 0x5900 +#define PCI_DEVICE_ID_3COM_3C595TX 0x5950 +#define PCI_DEVICE_ID_3COM_3C595T4 0x5951 +#define PCI_DEVICE_ID_3COM_3C595MII 0x5952 +#define PCI_DEVICE_ID_3COM_3C900TPO 0x9000 +#define PCI_DEVICE_ID_3COM_3C900COMBO 0x9001 +#define PCI_DEVICE_ID_3COM_3C905TX 0x9050 +#define PCI_DEVICE_ID_3COM_3C905T4 0x9051 +#define PCI_DEVICE_ID_3COM_3C905B_TX 0x9055 + +#define PCI_VENDOR_ID_SMC 0x10b8 +#define PCI_DEVICE_ID_SMC_EPIC100 0x0005 + +#define PCI_VENDOR_ID_AL 0x10b9 +#define PCI_DEVICE_ID_AL_M1445 0x1445 +#define PCI_DEVICE_ID_AL_M1449 0x1449 +#define PCI_DEVICE_ID_AL_M1451 0x1451 +#define PCI_DEVICE_ID_AL_M1461 0x1461 +#define PCI_DEVICE_ID_AL_M1489 0x1489 +#define PCI_DEVICE_ID_AL_M1511 0x1511 +#define PCI_DEVICE_ID_AL_M1513 0x1513 +#define PCI_DEVICE_ID_AL_M1521 0x1521 +#define PCI_DEVICE_ID_AL_M1523 0x1523 +#define PCI_DEVICE_ID_AL_M1531 0x1531 +#define PCI_DEVICE_ID_AL_M1533 0x1533 +#define PCI_DEVICE_ID_AL_M1541 0x1541 +#define PCI_DEVICE_ID_AL_M1543 0x1543 +#define PCI_DEVICE_ID_AL_M3307 0x3307 +#define PCI_DEVICE_ID_AL_M4803 0x5215 +#define PCI_DEVICE_ID_AL_M5219 0x5219 +#define PCI_DEVICE_ID_AL_M5229 0x5229 +#define PCI_DEVICE_ID_AL_M5237 0x5237 +#define PCI_DEVICE_ID_AL_M5243 0x5243 +#define PCI_DEVICE_ID_AL_M7101 0x7101 + +#define PCI_VENDOR_ID_MITSUBISHI 0x10ba + +#define PCI_VENDOR_ID_SURECOM 0x10bd +#define PCI_DEVICE_ID_SURECOM_NE34 0x0e34 + +#define PCI_VENDOR_ID_NEOMAGIC 0x10c8 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083 + +#define PCI_VENDOR_ID_ASP 0x10cd +#define PCI_DEVICE_ID_ASP_ABP940 0x1200 +#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 +#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 + +#define PCI_VENDOR_ID_MACRONIX 0x10d9 +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512 +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531 + +#define PCI_VENDOR_ID_CERN 0x10dc +#define PCI_DEVICE_ID_CERN_SPSB_PMC 0x0001 +#define PCI_DEVICE_ID_CERN_SPSB_PCI 0x0002 +#define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 +#define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022 + +#define PCI_VENDOR_ID_NVIDIA 0x10de +#define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 +#define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 +#define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 +#define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C +#define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D +#define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 + +#define PCI_VENDOR_ID_IMS 0x10e0 +#define PCI_DEVICE_ID_IMS_8849 0x8849 + +#define PCI_VENDOR_ID_TEKRAM2 0x10e1 +#define PCI_DEVICE_ID_TEKRAM2_690c 0x690c + +#define PCI_VENDOR_ID_TUNDRA 0x10e3 +#define PCI_DEVICE_ID_TUNDRA_CA91C042 0x0000 + +#define PCI_VENDOR_ID_AMCC 0x10e8 +#define PCI_DEVICE_ID_AMCC_MYRINET 0x8043 +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062 +#define PCI_DEVICE_ID_AMCC_S5933 0x807d +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c + +#define PCI_VENDOR_ID_INTERG 0x10ea +#define PCI_DEVICE_ID_INTERG_1680 0x1680 +#define PCI_DEVICE_ID_INTERG_1682 0x1682 +#define PCI_DEVICE_ID_INTERG_2000 0x2000 + +#define PCI_VENDOR_ID_REALTEK 0x10ec +#define PCI_DEVICE_ID_REALTEK_8029 0x8029 +#define PCI_DEVICE_ID_REALTEK_8129 0x8129 +#define PCI_DEVICE_ID_REALTEK_8139 0x8139 + +#define PCI_VENDOR_ID_TRUEVISION 0x10fa +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c + +#define PCI_VENDOR_ID_INIT 0x1101 +#define PCI_DEVICE_ID_INIT_320P 0x9100 +#define PCI_DEVICE_ID_INIT_360P 0x9500 + +#define PCI_VENDOR_ID_TTI 0x1103 +#define PCI_DEVICE_ID_TTI_HPT343 0x0003 +#define PCI_DEVICE_ID_TTI_HPT366 0x0004 + +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_8501_0 0x0501 +#define PCI_DEVICE_ID_VIA_82C505 0x0505 +#define PCI_DEVICE_ID_VIA_82C561 0x0561 +#define PCI_DEVICE_ID_VIA_82C586_1 0x0571 +#define PCI_DEVICE_ID_VIA_82C576 0x0576 +#define PCI_DEVICE_ID_VIA_82C585 0x0585 +#define PCI_DEVICE_ID_VIA_82C586_0 0x0586 +#define PCI_DEVICE_ID_VIA_82C595 0x0595 +#define PCI_DEVICE_ID_VIA_82C596 0x0596 +#define PCI_DEVICE_ID_VIA_82C597_0 0x0597 +#define PCI_DEVICE_ID_VIA_82C598_0 0x0598 +#define PCI_DEVICE_ID_VIA_82C680 0x0680 +#define PCI_DEVICE_ID_VIA_82C686 0x0686 +#define PCI_DEVICE_ID_VIA_82C691 0x0691 +#define PCI_DEVICE_ID_VIA_82C693 0x0693 +#define PCI_DEVICE_ID_VIA_82C926 0x0926 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C595_97 0x1595 +#define PCI_DEVICE_ID_VIA_82C586_2 0x3038 +#define PCI_DEVICE_ID_VIA_82C586_3 0x3040 +#define PCI_DEVICE_ID_VIA_82C686_4 0x3057 +#define PCI_DEVICE_ID_VIA_82C686_5 0x3058 +#define PCI_DEVICE_ID_VIA_82C686_6 0x3068 +#define PCI_DEVICE_ID_VIA_86C100A 0x6100 +#define PCI_DEVICE_ID_VIA_8501_1 0x8501 +#define PCI_DEVICE_ID_VIA_82C597_1 0x8597 +#define PCI_DEVICE_ID_VIA_82C598_1 0x8598 + +#define PCI_VENDOR_ID_SMC2 0x1113 +#define PCI_DEVICE_ID_SMC2_1211TX 0x1211 + +#define PCI_VENDOR_ID_VORTEX 0x1119 +#define PCI_DEVICE_ID_VORTEX_GDT60x0 0x0000 +#define PCI_DEVICE_ID_VORTEX_GDT6000B 0x0001 +#define PCI_DEVICE_ID_VORTEX_GDT6x10 0x0002 +#define PCI_DEVICE_ID_VORTEX_GDT6x20 0x0003 +#define PCI_DEVICE_ID_VORTEX_GDT6530 0x0004 +#define PCI_DEVICE_ID_VORTEX_GDT6550 0x0005 +#define PCI_DEVICE_ID_VORTEX_GDT6x17 0x0006 +#define PCI_DEVICE_ID_VORTEX_GDT6x27 0x0007 +#define PCI_DEVICE_ID_VORTEX_GDT6537 0x0008 +#define PCI_DEVICE_ID_VORTEX_GDT6557 0x0009 +#define PCI_DEVICE_ID_VORTEX_GDT6x15 0x000a +#define PCI_DEVICE_ID_VORTEX_GDT6x25 0x000b +#define PCI_DEVICE_ID_VORTEX_GDT6535 0x000c +#define PCI_DEVICE_ID_VORTEX_GDT6555 0x000d +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115 +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120 +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121 +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122 +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123 +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124 +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125 + +#define PCI_VENDOR_ID_EF 0x111a +#define PCI_DEVICE_ID_EF_ATM_FPGA 0x0000 +#define PCI_DEVICE_ID_EF_ATM_ASIC 0x0002 + +#define PCI_VENDOR_ID_FORE 0x1127 +#define PCI_DEVICE_ID_FORE_PCA200PC 0x0210 +#define PCI_DEVICE_ID_FORE_PCA200E 0x0300 + +#define PCI_VENDOR_ID_IMAGINGTECH 0x112f +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000 + +#define PCI_VENDOR_ID_PHILIPS 0x1131 +#define PCI_DEVICE_ID_PHILIPS_SAA7145 0x7145 +#define PCI_DEVICE_ID_PHILIPS_SAA7146 0x7146 + +#define PCI_VENDOR_ID_CYCLONE 0x113c +#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001 + +#define PCI_VENDOR_ID_ALLIANCE 0x1142 +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210 +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422 +#define PCI_DEVICE_ID_ALLIANCE_AT24 0x6424 +#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d + +#define PCI_VENDOR_ID_SK 0x1148 +#define PCI_DEVICE_ID_SK_FP 0x4000 +#define PCI_DEVICE_ID_SK_TR 0x4200 +#define PCI_DEVICE_ID_SK_GE 0x4300 + +#define PCI_VENDOR_ID_VMIC 0x114a +#define PCI_DEVICE_ID_VMIC_VME 0x7587 + +#define PCI_VENDOR_ID_DIGI 0x114f +#define PCI_DEVICE_ID_DIGI_EPC 0x0002 +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003 +#define PCI_DEVICE_ID_DIGI_XEM 0x0004 +#define PCI_DEVICE_ID_DIGI_XR 0x0005 +#define PCI_DEVICE_ID_DIGI_CX 0x0006 +#define PCI_DEVICE_ID_DIGI_XRJ 0x0009 +#define PCI_DEVICE_ID_DIGI_EPCJ 0x000a +#define PCI_DEVICE_ID_DIGI_XR_920 0x0027 + +#define PCI_VENDOR_ID_MUTECH 0x1159 +#define PCI_DEVICE_ID_MUTECH_MV1000 0x0001 + +#define PCI_VENDOR_ID_RENDITION 0x1163 +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001 +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000 + +#define PCI_VENDOR_ID_TOSHIBA 0x1179 +#define PCI_DEVICE_ID_TOSHIBA_601 0x0601 +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f + +#define PCI_VENDOR_ID_RICOH 0x1180 +#define PCI_DEVICE_ID_RICOH_RL5C465 0x0465 +#define PCI_DEVICE_ID_RICOH_RL5C466 0x0466 +#define PCI_DEVICE_ID_RICOH_RL5C475 0x0475 +#define PCI_DEVICE_ID_RICOH_RL5C478 0x0478 + +#define PCI_VENDOR_ID_ARTOP 0x1191 +#define PCI_DEVICE_ID_ARTOP_ATP8400 0x0004 +#define PCI_DEVICE_ID_ARTOP_ATP850UF 0x0005 + +#define PCI_VENDOR_ID_ZEITNET 0x1193 +#define PCI_DEVICE_ID_ZEITNET_1221 0x0001 +#define PCI_DEVICE_ID_ZEITNET_1225 0x0002 + +#define PCI_VENDOR_ID_OMEGA 0x119b +#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221 + +#define PCI_SUBVENDOR_ID_KEYSPAN 0x11a9 +#define PCI_SUBDEVICE_ID_KEYSPAN_SX2 0x5334 + +#define PCI_VENDOR_ID_GALILEO 0x11ab +#define PCI_DEVICE_ID_GALILEO_GT64011 0x4146 + +#define PCI_VENDOR_ID_LITEON 0x11ad +#define PCI_DEVICE_ID_LITEON_LNE100TX 0x0002 + +#define PCI_VENDOR_ID_V3 0x11b0 +#define PCI_DEVICE_ID_V3_V960 0x0001 +#define PCI_DEVICE_ID_V3_V350 0x0001 +#define PCI_DEVICE_ID_V3_V960V2 0x0002 +#define PCI_DEVICE_ID_V3_V350V2 0x0002 + +#define PCI_VENDOR_ID_NP 0x11bc +#define PCI_DEVICE_ID_NP_PCI_FDDI 0x0001 + +#define PCI_VENDOR_ID_ATT 0x11c1 +#define PCI_DEVICE_ID_ATT_L56XMF 0x0440 + +#define PCI_VENDOR_ID_SPECIALIX 0x11cb +#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000 +#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000 +#define PCI_DEVICE_ID_SPECIALIX_RIO 0x8000 + +#define PCI_VENDOR_ID_AURAVISION 0x11d1 +#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7 + +#define PCI_VENDOR_ID_IKON 0x11d5 +#define PCI_DEVICE_ID_IKON_10115 0x0115 +#define PCI_DEVICE_ID_IKON_10117 0x0117 + +#define PCI_VENDOR_ID_ZORAN 0x11de +#define PCI_DEVICE_ID_ZORAN_36057 0x6057 +#define PCI_DEVICE_ID_ZORAN_36120 0x6120 + +#define PCI_VENDOR_ID_KINETIC 0x11f4 +#define PCI_DEVICE_ID_KINETIC_2915 0x2915 + +#define PCI_VENDOR_ID_COMPEX 0x11f6 +#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112 +#define PCI_DEVICE_ID_COMPEX_RL2000 0x1401 + +#define PCI_VENDOR_ID_RP 0x11fe +#define PCI_DEVICE_ID_RP32INTF 0x0001 +#define PCI_DEVICE_ID_RP8INTF 0x0002 +#define PCI_DEVICE_ID_RP16INTF 0x0003 +#define PCI_DEVICE_ID_RP4QUAD 0x0004 +#define PCI_DEVICE_ID_RP8OCTA 0x0005 +#define PCI_DEVICE_ID_RP8J 0x0006 +#define PCI_DEVICE_ID_RPP4 0x000A +#define PCI_DEVICE_ID_RPP8 0x000B +#define PCI_DEVICE_ID_RP8M 0x000C + +#define PCI_VENDOR_ID_CYCLADES 0x120e +#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100 +#define PCI_DEVICE_ID_CYCLOM_Y_Hi 0x0101 +#define PCI_DEVICE_ID_CYCLOM_4Y_Lo 0x0102 +#define PCI_DEVICE_ID_CYCLOM_4Y_Hi 0x0103 +#define PCI_DEVICE_ID_CYCLOM_8Y_Lo 0x0104 +#define PCI_DEVICE_ID_CYCLOM_8Y_Hi 0x0105 +#define PCI_DEVICE_ID_CYCLOM_Z_Lo 0x0200 +#define PCI_DEVICE_ID_CYCLOM_Z_Hi 0x0201 + +#define PCI_VENDOR_ID_ESSENTIAL 0x120f +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER 0x0001 + +#define PCI_VENDOR_ID_O2 0x1217 +#define PCI_DEVICE_ID_O2_6729 0x6729 +#define PCI_DEVICE_ID_O2_6730 0x673a +#define PCI_DEVICE_ID_O2_6832 0x6832 +#define PCI_DEVICE_ID_O2_6836 0x6836 + +#define PCI_VENDOR_ID_3DFX 0x121a +#define PCI_DEVICE_ID_3DFX_VOODOO 0x0001 +#define PCI_DEVICE_ID_3DFX_VOODOO2 0x0002 +#define PCI_DEVICE_ID_3DFX_BANSHEE 0x0003 +#define PCI_DEVICE_ID_3DFX_VOODOO3 0x0005 + +#define PCI_VENDOR_ID_SIGMADES 0x1236 +#define PCI_DEVICE_ID_SIGMADES_6425 0x6401 + +#define PCI_VENDOR_ID_CCUBE 0x123f + +#define PCI_VENDOR_ID_AVM 0x1244 +#define PCI_DEVICE_ID_AVM_A1 0x0a00 + +#define PCI_VENDOR_ID_DIPIX 0x1246 + +#define PCI_VENDOR_ID_STALLION 0x124d +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000 +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002 +#define PCI_DEVICE_ID_STALLION_EIOPCI 0x0003 + +#define PCI_VENDOR_ID_OPTIBASE 0x1255 +#define PCI_DEVICE_ID_OPTIBASE_FORGE 0x1110 +#define PCI_DEVICE_ID_OPTIBASE_FUSION 0x1210 +#define PCI_DEVICE_ID_OPTIBASE_VPLEX 0x2110 +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120 +#define PCI_DEVICE_ID_OPTIBASE_VQUEST 0x2130 + +#define PCI_VENDOR_ID_ESS 0x125d +#define PCI_DEVICE_ID_ESS_AUDIOPCI 0x1969 + +#define PCI_VENDOR_ID_SATSAGEM 0x1267 +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352 +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b + +#define PCI_VENDOR_ID_HUGHES 0x1273 +#define PCI_DEVICE_ID_HUGHES_DIRECPC 0x0002 + +#define PCI_VENDOR_ID_ENSONIQ 0x1274 +#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000 +#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 + +#define PCI_VENDOR_ID_ALTEON 0x12ae +#define PCI_DEVICE_ID_ALTEON_ACENIC 0x0001 + +#define PCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232 0x0001 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232 0x0002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232 0x0003 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485 0x0004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4 0x0005 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485 0x0006 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2 0x0007 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485 0x0008 + +#define PCI_VENDOR_ID_PICTUREL 0x12c5 +#define PCI_DEVICE_ID_PICTUREL_PCIVST 0x0081 + +#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018 + +#define PCI_VENDOR_ID_CBOARDS 0x1307 +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001 + +#define PCI_VENDOR_ID_SIIG 0x131f +#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011 +#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012 +#define PCI_DEVICE_ID_SIIG_1P_10x 0x1020 +#define PCI_DEVICE_ID_SIIG_2P_10x 0x1021 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035 +#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036 +#define PCI_DEVICE_ID_SIIG_1P_20x 0x2020 +#define PCI_DEVICE_ID_SIIG_2P_20x 0x2021 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041 +#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011 +#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061 +#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062 + +#define PCI_VENDOR_ID_SEALEVEL 0x135e +#define PCI_DEVICE_ID_SEALEVEL_U530 0x7101 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM2 0x7201 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402 +#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202 +#define PCI_DEVICE_ID_SEALEVEL_COMM4 0x7401 +#define PCI_DEVICE_ID_SEALEVEL_COMM8 0x7801 + +#define PCI_VENDOR_ID_NETGEAR 0x1385 +#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a + +#define PCI_VENDOR_ID_LAVA 0x1407 +#define PCI_DEVICE_ID_LAVA_PARALLEL 0x8000 +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A 0x8002 /* The Lava Dual Parallel is */ +#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B 0x8003 /* two PCI devices on a card */ + +#define PCI_VENDOR_ID_PANACOM 0x14d4 +#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400 +#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402 + +#define PCI_VENDOR_ID_SYMPHONY 0x1c1c +#define PCI_DEVICE_ID_SYMPHONY_101 0x0001 + +#define PCI_VENDOR_ID_TEKRAM 0x1de1 +#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 + +#define PCI_VENDOR_ID_3DLABS 0x3d3d +#define PCI_DEVICE_ID_3DLABS_300SX 0x0001 +#define PCI_DEVICE_ID_3DLABS_500TX 0x0002 +#define PCI_DEVICE_ID_3DLABS_DELTA 0x0003 +#define PCI_DEVICE_ID_3DLABS_PERMEDIA 0x0004 +#define PCI_DEVICE_ID_3DLABS_MX 0x0006 + +#define PCI_VENDOR_ID_AVANCE 0x4005 +#define PCI_DEVICE_ID_AVANCE_ALG2064 0x2064 +#define PCI_DEVICE_ID_AVANCE_2302 0x2302 + +#define PCI_VENDOR_ID_NETVIN 0x4a14 +#define PCI_DEVICE_ID_NETVIN_NV5000SC 0x5000 + +#define PCI_VENDOR_ID_S3 0x5333 +#define PCI_DEVICE_ID_S3_PLATO_PXS 0x0551 +#define PCI_DEVICE_ID_S3_ViRGE 0x5631 +#define PCI_DEVICE_ID_S3_TRIO 0x8811 +#define PCI_DEVICE_ID_S3_AURORA64VP 0x8812 +#define PCI_DEVICE_ID_S3_TRIO64UVP 0x8814 +#define PCI_DEVICE_ID_S3_ViRGE_VX 0x883d +#define PCI_DEVICE_ID_S3_868 0x8880 +#define PCI_DEVICE_ID_S3_928 0x88b0 +#define PCI_DEVICE_ID_S3_864_1 0x88c0 +#define PCI_DEVICE_ID_S3_864_2 0x88c1 +#define PCI_DEVICE_ID_S3_964_1 0x88d0 +#define PCI_DEVICE_ID_S3_964_2 0x88d1 +#define PCI_DEVICE_ID_S3_968 0x88f0 +#define PCI_DEVICE_ID_S3_TRIO64V2 0x8901 +#define PCI_DEVICE_ID_S3_PLATO_PXG 0x8902 +#define PCI_DEVICE_ID_S3_ViRGE_DXGX 0x8a01 +#define PCI_DEVICE_ID_S3_ViRGE_GX2 0x8a10 +#define PCI_DEVICE_ID_S3_ViRGE_MX 0x8c01 +#define PCI_DEVICE_ID_S3_ViRGE_MXP 0x8c02 +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV 0x8c03 +#define PCI_DEVICE_ID_S3_SONICVIBES 0xca00 + +#define PCI_VENDOR_ID_DCI 0x6666 +#define PCI_DEVICE_ID_DCI_PCCOM4 0x0001 + +#define PCI_VENDOR_ID_GENROCO 0x5555 +#define PCI_DEVICE_ID_GENROCO_HFP832 0x0003 + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_21145 0x0039 +#define PCI_DEVICE_ID_INTEL_82375 0x0482 +#define PCI_DEVICE_ID_INTEL_82424 0x0483 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 +#define PCI_DEVICE_ID_INTEL_82430 0x0486 +#define PCI_DEVICE_ID_INTEL_82434 0x04a3 +#define PCI_DEVICE_ID_INTEL_I960 0x0960 +#define PCI_DEVICE_ID_INTEL_82559ER 0x1209 +#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221 +#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222 +#define PCI_DEVICE_ID_INTEL_7116 0x1223 +#define PCI_DEVICE_ID_INTEL_82596 0x1226 +#define PCI_DEVICE_ID_INTEL_82865 0x1227 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82437 0x122d +#define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e +#define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230 +#define PCI_DEVICE_ID_INTEL_82371MX 0x1234 +#define PCI_DEVICE_ID_INTEL_82437MX 0x1235 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_82380FB 0x124b +#define PCI_DEVICE_ID_INTEL_82439 0x1250 +#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 +#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 +#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 +#define PCI_DEVICE_ID_INTEL_82437VX 0x7030 +#define PCI_DEVICE_ID_INTEL_82439TX 0x7100 +#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 +#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 +#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 +#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 +#define PCI_VENDOR_ID_COMPUTONE 0x8e0e +#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 + +#define PCI_DEVICE_ID_INTEL_82443LX_0 0x7180 +#define PCI_DEVICE_ID_INTEL_82443LX_1 0x7181 +#define PCI_DEVICE_ID_INTEL_82443BX_0 0x7190 +#define PCI_DEVICE_ID_INTEL_82443BX_1 0x7191 +#define PCI_DEVICE_ID_INTEL_82443BX_2 0x7192 +#define PCI_DEVICE_ID_INTEL_P6 0x84c4 +#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 +#define PCI_DEVICE_ID_INTEL_82451NX 0x84ca + +#define PCI_VENDOR_ID_KTI 0x8e2e +#define PCI_DEVICE_ID_KTI_ET32P2 0x3000 + +#define PCI_VENDOR_ID_ADAPTEC 0x9004 +#define PCI_DEVICE_ID_ADAPTEC_7810 0x1078 +#define PCI_DEVICE_ID_ADAPTEC_7821 0x2178 +#define PCI_DEVICE_ID_ADAPTEC_38602 0x3860 +#define PCI_DEVICE_ID_ADAPTEC_7850 0x5078 +#define PCI_DEVICE_ID_ADAPTEC_7855 0x5578 +#define PCI_DEVICE_ID_ADAPTEC_5800 0x5800 +#define PCI_DEVICE_ID_ADAPTEC_3860 0x6038 +#define PCI_DEVICE_ID_ADAPTEC_1480A 0x6075 +#define PCI_DEVICE_ID_ADAPTEC_7860 0x6078 +#define PCI_DEVICE_ID_ADAPTEC_7861 0x6178 +#define PCI_DEVICE_ID_ADAPTEC_7870 0x7078 +#define PCI_DEVICE_ID_ADAPTEC_7871 0x7178 +#define PCI_DEVICE_ID_ADAPTEC_7872 0x7278 +#define PCI_DEVICE_ID_ADAPTEC_7873 0x7378 +#define PCI_DEVICE_ID_ADAPTEC_7874 0x7478 +#define PCI_DEVICE_ID_ADAPTEC_7895 0x7895 +#define PCI_DEVICE_ID_ADAPTEC_7880 0x8078 +#define PCI_DEVICE_ID_ADAPTEC_7881 0x8178 +#define PCI_DEVICE_ID_ADAPTEC_7882 0x8278 +#define PCI_DEVICE_ID_ADAPTEC_7883 0x8378 +#define PCI_DEVICE_ID_ADAPTEC_7884 0x8478 +#define PCI_DEVICE_ID_ADAPTEC_7885 0x8578 +#define PCI_DEVICE_ID_ADAPTEC_7886 0x8678 +#define PCI_DEVICE_ID_ADAPTEC_7887 0x8778 +#define PCI_DEVICE_ID_ADAPTEC_7888 0x8878 +#define PCI_DEVICE_ID_ADAPTEC_1030 0x8b78 + +#define PCI_VENDOR_ID_ADAPTEC2 0x9005 +#define PCI_DEVICE_ID_ADAPTEC2_2940U2 0x0010 +#define PCI_DEVICE_ID_ADAPTEC2_2930U2 0x0011 +#define PCI_DEVICE_ID_ADAPTEC2_7890B 0x0013 +#define PCI_DEVICE_ID_ADAPTEC2_7890 0x001f +#define PCI_DEVICE_ID_ADAPTEC2_3940U2 0x0050 +#define PCI_DEVICE_ID_ADAPTEC2_3950U2D 0x0051 +#define PCI_DEVICE_ID_ADAPTEC2_7896 0x005f +#define PCI_DEVICE_ID_ADAPTEC2_7892A 0x0080 +#define PCI_DEVICE_ID_ADAPTEC2_7892B 0x0081 +#define PCI_DEVICE_ID_ADAPTEC2_7892D 0x0083 +#define PCI_DEVICE_ID_ADAPTEC2_7892P 0x008f +#define PCI_DEVICE_ID_ADAPTEC2_7899A 0x00c0 +#define PCI_DEVICE_ID_ADAPTEC2_7899B 0x00c1 +#define PCI_DEVICE_ID_ADAPTEC2_7899D 0x00c3 +#define PCI_DEVICE_ID_ADAPTEC2_7899P 0x00cf + +#define PCI_VENDOR_ID_ATRONICS 0x907f +#define PCI_DEVICE_ID_ATRONICS_2015 0x2015 + +#define PCI_VENDOR_ID_HOLTEK 0x9412 +#define PCI_DEVICE_ID_HOLTEK_6565 0x6565 + +#define PCI_VENDOR_ID_EXSYS 0xd84d +#define PCI_DEVICE_ID_EXSYS_4014 0x4014 + +#define PCI_VENDOR_ID_TIGERJET 0xe159 +#define PCI_DEVICE_ID_TIGERJET_300 0x0001 + +#define PCI_VENDOR_ID_ARK 0xedd8 +#define PCI_DEVICE_ID_ARK_STING 0xa091 +#define PCI_DEVICE_ID_ARK_STINGARK 0xa099 +#define PCI_DEVICE_ID_ARK_2000MT 0xa0a1 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 + +#define PCI_VENDOR_ID_INTERPHASE 0x107e +#define PCI_DEVICE_ID_INTERPHASE_5526 0x0004 +#define PCI_DEVICE_ID_INTERPHASE_55x6 0x0005 + diff --git a/include/linux/prctl.h b/include/linux/prctl.h index 3382a6a57..d8ae9689c 100644 --- a/include/linux/prctl.h +++ b/include/linux/prctl.h @@ -6,5 +6,8 @@ #define PR_SET_PDEATHSIG 1 /* Second arg is a signal */ #define PR_GET_PDEATHSIG 2 /* Second arg is a ptr to return the signal */ +/* Get/set current->dumpable */ +#define PR_GET_DUMPABLE 3 +#define PR_SET_DUMPABLE 4 #endif /* _LINUX_PRCTL_H */ diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index f4a7e6d32..d863aaefe 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -199,6 +199,7 @@ enum scsi_directory_inos { PROC_SCSI_MVME147, PROC_SCSI_MVME16x, PROC_SCSI_BVME6000, + PROC_SCSI_SIM710, PROC_SCSI_A3000, PROC_SCSI_A2091, PROC_SCSI_GVP11, diff --git a/include/linux/sched.h b/include/linux/sched.h index 87e0fb212..1ad6ea2b3 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -142,6 +142,8 @@ extern void init_idle(void); extern void show_state(void); extern void cpu_init (void); extern void trap_init(void); +extern void update_one_process( struct task_struct *p, + unsigned long ticks, unsigned long user, unsigned long system, int cpu); #define MAX_SCHEDULE_TIMEOUT LONG_MAX extern signed long FASTCALL(schedule_timeout(signed long timeout)); @@ -823,8 +825,8 @@ extern inline int task_on_runqueue(struct task_struct *p) extern inline void unhash_process(struct task_struct *p) { if (task_on_runqueue(p)) BUG(); - nr_threads--; write_lock_irq(&tasklist_lock); + nr_threads--; unhash_pid(p); REMOVE_LINKS(p); write_unlock_irq(&tasklist_lock); diff --git a/include/linux/smp.h b/include/linux/smp.h index eae129070..27423ec66 100644 --- a/include/linux/smp.h +++ b/include/linux/smp.h @@ -80,7 +80,7 @@ extern volatile int smp_msg_id; #define smp_threads_ready 1 #define kernel_lock() #define cpu_logical_map(cpu) 0 -#define smp_call_function(func,info,retry,wait) +#define smp_call_function(func,info,retry,wait) 0 #endif #endif diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h index 032293ea3..d72dba85b 100644 --- a/include/linux/sunrpc/xprt.h +++ b/include/linux/sunrpc/xprt.h @@ -124,8 +124,10 @@ struct rpc_rqst { struct rpc_xprt { struct rpc_xprt * link; /* list of all clients */ struct rpc_xprt * rx_pending; /* receive pending list */ + struct rpc_xprt * tx_pending; /* transmit pending list */ - int rx_pending_flag;/* are we on the pending list ? */ + int rx_pending_flag;/* are we on the rcv pending list ? */ + int tx_pending_flag;/* are we on the xmit pending list ? */ struct file * file; /* VFS layer */ struct socket * sock; /* BSD socket layer */ diff --git a/include/linux/synclink.h b/include/linux/synclink.h index 70ce90e10..450341b74 100644 --- a/include/linux/synclink.h +++ b/include/linux/synclink.h @@ -1,7 +1,7 @@ /* * SyncLink Multiprotocol Serial Adapter Driver * - * ==FILEDATE 19990523== + * ==FILEDATE 19990810== * * Copyright (C) 1998 by Microgate Corporation * @@ -50,8 +50,9 @@ #define BIT31 0x80000000 -#define HDLC_MAX_FRAME_SIZE 4096 +#define HDLC_MAX_FRAME_SIZE 65535 #define MAX_ASYNC_TRANSMIT 4096 +#define MAX_ASYNC_BUFFER_SIZE 4096 #define ASYNC_PARITY_NONE 0 #define ASYNC_PARITY_EVEN 1 @@ -68,12 +69,12 @@ #define HDLC_FLAG_AUTO_RTS 0x0080 #define HDLC_FLAG_RXC_DPLL 0x0100 #define HDLC_FLAG_RXC_BRG 0x0200 -#define HDLC_FLAG_RXC_TXCPIN 0x8000 -#define HDLC_FLAG_RXC_RXCPIN 0x0000 +#define HDLC_FLAG_RXC_TXCPIN 0x8000 +#define HDLC_FLAG_RXC_RXCPIN 0x0000 #define HDLC_FLAG_TXC_DPLL 0x0400 #define HDLC_FLAG_TXC_BRG 0x0800 -#define HDLC_FLAG_TXC_TXCPIN 0x0000 -#define HDLC_FLAG_TXC_RXCPIN 0x0008 +#define HDLC_FLAG_TXC_TXCPIN 0x0000 +#define HDLC_FLAG_TXC_RXCPIN 0x0008 #define HDLC_FLAG_DPLL_DIV8 0x1000 #define HDLC_FLAG_DPLL_DIV16 0x2000 #define HDLC_FLAG_DPLL_DIV32 0x0000 @@ -81,6 +82,7 @@ #define HDLC_CRC_NONE 0 #define HDLC_CRC_16_CCITT 1 +#define HDLC_CRC_32_CCITT 2 #define HDLC_TXIDLE_FLAGS 0 #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 @@ -132,7 +134,7 @@ typedef struct _MGSL_PARAMS unsigned char encoding; /* NRZ, NRZI, etc. */ unsigned long clock_speed; /* external clock speed in bits per second */ unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ - unsigned short crc_type; /* None, CRC16 or CRC16-CCITT */ + unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ unsigned char preamble_length; unsigned char preamble; diff --git a/include/linux/tty.h b/include/linux/tty.h index bbb3ea833..6cb629d08 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -331,6 +331,7 @@ struct tty_struct { #define TTY_HW_COOK_OUT 14 #define TTY_HW_COOK_IN 15 #define TTY_PTY_LOCK 16 +#define TTY_NO_WRITE_SPLIT 17 #define TTY_WRITE_FLUSH(tty) tty_write_flush((tty)) diff --git a/include/scsi/sg.h b/include/scsi/sg.h index 8b50bb3da..6756f8d2f 100644 --- a/include/scsi/sg.h +++ b/include/scsi/sg.h @@ -12,10 +12,16 @@ Original driver (sg.h): * Copyright (C) 1998, 1999 Douglas Gilbert - Version: 2.1.34 (990603) - This version for later 2.1.x and 2.2.x series kernels - D. P. Gilbert (dgilbert@interlog.com, dougg@triode.net.au) - + Version: 2.3.35 (990708) + This version for 2.3 series kernels. It only differs from sg version + 2.1.35 used in the 2.2 series kernels by changes to wait_queue. This + in an internal kernel interface and should not effect users. + D. P. Gilbert (dgilbert@interlog.com, dougg@triode.net.au) + + Changes since 2.1.34 (990603) + - add queuing info into struct sg_scsi_id + - block negative timeout values + - add back write() wait on previous read() when no cmd queuing Changes since 2.1.33 (990521) - implement SG_SET_RESERVED_SIZE and associated memory re-org. - add SG_NEXT_CMD_LEN to override SCSI command lengths @@ -144,9 +150,10 @@ typedef struct sg_scsi_id { int scsi_id; /* scsi id of target device */ int lun; int scsi_type; /* TYPE_... defined in scsi/scsi.h */ + short h_cmd_per_lun;/* host (adapter) maximum commands per lun */ + short d_queue_depth;/* device (or adapter) maximum queue length */ int unused1; /* probably find a good use, set 0 for now */ int unused2; /* ditto */ - int unused3; } Sg_scsi_id; /* IOCTLs: ( _GET_s yield result via 'int *' 3rd argument unless @@ -205,6 +212,10 @@ typedef struct sg_scsi_id { #define SG_NEXT_CMD_LEN 0x2283 /* override SCSI command length with given number on the next write() on this file descriptor */ +/* Returns -EBUSY if occupied else takes as input: 0 -> do nothing, + 1 -> device reset or 2 -> bus reset (may not be activated yet) */ +#define SG_SCSI_RESET 0x2284 + #define SG_SCATTER_SZ (8 * 4096) /* PAGE_SIZE not available to user */ /* Largest size (in bytes) a single scatter-gather list element can have. diff --git a/include/video/fbcon.h b/include/video/fbcon.h index 1d972dda3..1cca4c90f 100644 --- a/include/video/fbcon.h +++ b/include/video/fbcon.h @@ -16,6 +16,8 @@ #include <linux/console_struct.h> #include <linux/vt_buffer.h> +#include <asm/io.h> + /* * `switch' for the Low Level Operations @@ -179,7 +181,7 @@ extern void fbcon_redraw_bmove(struct display *, int, int, int, int, int, int); movep is rather expensive compared to ordinary move's some functions rewritten in C for clarity, no speed loss */ -static __inline__ void *mymemclear_small(void *s, size_t count) +static __inline__ void *fb_memclear_small(void *s, size_t count) { if (!count) return(0); @@ -202,7 +204,7 @@ static __inline__ void *mymemclear_small(void *s, size_t count) } -static __inline__ void *mymemclear(void *s, size_t count) +static __inline__ void *fb_memclear(void *s, size_t count) { if (!count) return(0); @@ -244,7 +246,7 @@ static __inline__ void *mymemclear(void *s, size_t count) } -static __inline__ void *mymemset(void *s, size_t count) +static __inline__ void *fb_memset255(void *s, size_t count) { if (!count) return(0); @@ -267,7 +269,7 @@ static __inline__ void *mymemset(void *s, size_t count) } -static __inline__ void *mymemmove(void *d, const void *s, size_t count) +static __inline__ void *fb_memmove(void *d, const void *s, size_t count) { if (d < s) { if (count < 16) { @@ -389,17 +391,17 @@ static __inline__ void *sun4_memset(void *s, char val, size_t count) return s; } -static __inline__ void *mymemset(void *s, size_t count) +static __inline__ void *fb_memset255(void *s, size_t count) { return sun4_memset(s, 255, count); } -static __inline__ void *mymemclear(void *s, size_t count) +static __inline__ void *fb_memclear(void *s, size_t count) { return sun4_memset(s, 0, count); } -static __inline__ void *mymemclear_small(void *s, size_t count) +static __inline__ void *fb_memclear_small(void *s, size_t count) { return sun4_memset(s, 0, count); } @@ -416,7 +418,7 @@ static __inline__ void fast_memmove(void *d, const void *s, size_t count) ((char *) d)[count-i-1] = ((char *) s)[count-i-1]; } -static __inline__ void *mymemmove(char *dst, const char *src, size_t size) +static __inline__ void *fb_memmove(char *dst, const char *src, size_t size) { fast_memmove(dst, src, size); return dst; @@ -424,17 +426,17 @@ static __inline__ void *mymemmove(char *dst, const char *src, size_t size) #else -static __inline__ void *mymemclear_small(void *s, size_t count) +static __inline__ void *fb_memclear_small(void *s, size_t count) { return(memset(s, 0, count)); } -static __inline__ void *mymemclear(void *s, size_t count) +static __inline__ void *fb_memclear(void *s, size_t count) { return(memset(s, 0, count)); } -static __inline__ void *mymemset(void *s, size_t count) +static __inline__ void *fb_memset255(void *s, size_t count) { return(memset(s, 255, count)); } @@ -484,7 +486,7 @@ __asm__ __volatile__ ( } } -static __inline__ void *mymemmove(char *dst, const char *src, size_t size) +static __inline__ void *fb_memmove(char *dst, const char *src, size_t size) { fast_memmove(dst, src, size); return dst; @@ -497,7 +499,7 @@ static __inline__ void *mymemmove(char *dst, const char *src, size_t size) * (Why are these functions better than those from include/asm/string.h?) */ -static __inline__ void *mymemmove(void *d, const void *s, size_t count) +static __inline__ void *fb_memmove(void *d, const void *s, size_t count) { return(memmove(d, s, count)); } @@ -512,7 +514,21 @@ static __inline__ void fast_memmove(char *dst, const char *src, size_t size) #endif -#if defined(__i386__) || defined(__alpha__) +#if defined(__sparc__) + +/* We map all of our framebuffers such that big-endian accesses + * are what we want, so the following is sufficient. + */ + +#define fb_readb sbus_readb +#define fb_readw sbus_readw +#define fb_readl sbus_readl +#define fb_writeb sbus_writeb +#define fb_writew sbus_writew +#define fb_writel sbus_writel +#define fb_memset sbus_memset_io + +#elif defined(__i386__) || defined(__alpha__) #define fb_readb __raw_readb #define fb_readw __raw_readw @@ -520,6 +536,7 @@ static __inline__ void fast_memmove(char *dst, const char *src, size_t size) #define fb_writeb __raw_writeb #define fb_writew __raw_writew #define fb_writel __raw_writel +#define fb_memset memset_io #else @@ -529,6 +546,7 @@ static __inline__ void fast_memmove(char *dst, const char *src, size_t size) #define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b)) #define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b)) #define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b)) +#define fb_memset memset #endif diff --git a/include/video/macmodes.h b/include/video/macmodes.h index c459987e3..1bdfa815b 100644 --- a/include/video/macmodes.h +++ b/include/video/macmodes.h @@ -52,6 +52,9 @@ extern int mac_vmode_to_var(int vmode, int cmode, extern int mac_var_to_vmode(const struct fb_var_screeninfo *var, int *vmode, int *cmode); extern int mac_map_monitor_sense(int sense); +extern int __init mac_find_mode(struct fb_var_screeninfo *var, + struct fb_info *info, const char *mode_option, + unsigned int default_bpp); /* diff --git a/include/video/newport.h b/include/video/newport.h index 2f094e321..bfd2af7b1 100644 --- a/include/video/newport.h +++ b/include/video/newport.h @@ -12,7 +12,7 @@ #define _SGI_NEWPORT_H -typedef volatile unsigned long npireg_t; +typedef volatile unsigned int npireg_t; union npfloat { volatile float flt; @@ -143,7 +143,7 @@ struct newport_rexregs { npireg_t colorback; /* Background color */ npireg_t colorvram; /* Clear color for fast vram */ npireg_t alpharef; /* Reference value for afunctions */ - unsigned long pad0; + unsigned int pad0; npireg_t smask0x; /* Window GL relative screen mask 0 */ npireg_t smask0y; /* Window GL relative screen mask 0 */ npireg_t _setup; @@ -151,7 +151,7 @@ struct newport_rexregs { npireg_t _lsrestore; npireg_t _lssave; - unsigned long _pad1[0x30]; + unsigned int _pad1[0x30]; /* Iterators, full state for context switch */ npfreg_t _xstart; /* X-start point (current) */ @@ -178,7 +178,7 @@ struct newport_rexregs { npireg_t xyendi; npireg_t xstartendi; - unsigned long _unused2[0x29]; + unsigned int _unused2[0x29]; npfreg_t colorred; npfreg_t coloralpha; @@ -223,7 +223,7 @@ struct newport_rexregs { #define NPORT_DMODE_CSMASK 0x0f800000 #define NPORT_DMODE_SENDIAN 0x10000000 - unsigned long _unused3; + unsigned int _unused3; union np_dcb dcbdata0; npireg_t dcbdata1; @@ -248,8 +248,8 @@ struct newport_cregs { #define NPORT_CMODE_SM4 0x00000010 #define NPORT_CMODE_CMSK 0x00001e00 - unsigned long _unused0; - unsigned long config; + unsigned int _unused0; + unsigned int config; #define NPORT_CFG_G32MD 0x00000001 #define NPORT_CFG_BWIDTH 0x00000002 #define NPORT_CFG_ERCVR 0x00000004 @@ -284,11 +284,11 @@ struct newport_cregs { struct newport_regs { struct newport_rexregs set; - unsigned long _unused0[0x16e]; + unsigned int _unused0[0x16e]; struct newport_rexregs go; - unsigned long _unused1[0x22e]; + unsigned int _unused1[0x22e]; struct newport_cregs cset; - unsigned long _unused2[0x1ef]; + unsigned int _unused2[0x1ef]; struct newport_cregs cgo; }; extern struct newport_regs *npregs; |