| Commit message (Collapse) | Author | Age | Files | Lines |
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-Werror clean.
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and can not do with pte bit twiddling without grabbing page_table_lock.
Reinstate most of the old code, after disposing of an extra jump.
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the context register as it should be used, but let's look
into that later.
If there is a problem with the code it will crash after
right after freeing unused kernel memery. I have this code
tested on both UP and SMP though.
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switching in SMP mode, use PF_USEDFPU to determine whether a program
used the fpu in the last time quantum and so needs the fpu context
to be saved during context switch.
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last fpu owner before we assign the fpu to a new math task. However
is mips/mips64 working with this bug? Fix needs to be ported to
2.2/2.3 mips code. Additionally, the mips64 lazy_fpu_switch code
seems to have a ".set reorder" at the wrong place.
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PROM is getting the bit set before entry into kernel).
Fix per cpu frequency reporting.
Fix bug so that we do not clear information about mips4 availability.
Have the slaves flush their cache/tlb and set status based on what
the master processor did.
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Unlike the IRIX functions they only have one instruction overhead per
access, don't involve subroutine calls or any spinlocks, so are
implicitly threadsafe.
Add PCI infrastructure for SN0 + the necessary fixups for IOC3
brokeness.
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fork().
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