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* Each node needs to have a structure that the master nasid fills up toKanoj Sarcar2000-06-091-1/+0
| | | | | tell it where to get the kernel data from (ie, which nasid holds the kernel data). Remove debug cruft from head.S.
* Step one of trying to remove the assumption that nasid 0 is presentKanoj Sarcar2000-06-081-3/+33
| | | | from the mapped kernel code.
* Mapped kernel changes: create elf sections as close as possible toKanoj Sarcar2000-06-081-31/+27
| | | | | IRIX, to get the same kind of loader behavior. Read comments in mapped_kernel.h for more details.
* *** empty log message ***Ralf Baechle2000-06-061-12/+13
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* MAke sure the mapped kernel does not loose its prom command line.Kanoj Sarcar2000-06-061-1/+0
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* Entrylo1 must at least be marked global for the tlb entry mapping theKanoj Sarcar2000-06-061-1/+2
| | | | mapped kernel text/data for tlb translation to work properly.
* The tlbwired register is now set up in the head.S code.Kanoj Sarcar2000-06-061-363/+115
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* Initial rudimentary support for mapped kernel. The kernel text and dataKanoj Sarcar2000-06-061-87/+368
| | | | | | are placed in the cksseg area, and such behavior is tuned thru a make option (off by default). Basis for future kernel text replication and partitioning work/study.
* Fix the address twiddling. For some reason, the code that I was expectingKanoj Sarcar2000-06-051-11/+10
| | | | | was not getting generated (coding problem or cpp/as problem, no point tracking this down).
* Set smp_num_cpus in the IP27 specific code. Getting ready to handleKanoj Sarcar2000-06-021-2/+0
| | | | PROM-disabled cpus.
* Now that __kernel_clock_t is 64 bits, we need to make sure we have aKanoj Sarcar2000-06-012-1/+30
| | | | | | 32 bit version of the sys_times() call (like sparc64, ia64), else the kernel overwrites user space it is not supposed to. Compilations could not be done because of this.
* Forgot..Ulf Carlsson2000-05-301-2/+3
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* First cut of TLB handlers in assembler. I'm not usingUlf Carlsson2000-05-252-10/+227
| | | | | | | | | the context register as it should be used, but let's look into that later. If there is a problem with the code it will crash after right after freeing unused kernel memery. I have this code tested on both UP and SMP though.
* We have to check for pending signals when we return from do_page_fault toUlf Carlsson2000-05-201-1/+1
| | | | handle sigbus and sigsegv within a reasonable amount of time.
* Call syscall_trace after finishing the sigreturn syscall but beforeRalf Baechle2000-05-192-0/+8
| | | | returning from userspace.
* Less intrusive workaround for the gas ``-P'' bug.Ralf Baechle2000-05-181-1/+4
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* sigset_t fixes and a few new functions..Ulf Carlsson2000-05-132-26/+206
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* sigset_t is only 2 words nowadaysUlf Carlsson2000-05-131-3/+1
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* Merge with Linux 2.3.99-pre7 and various other bits.Ralf Baechle2000-05-121-32/+44
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* Add sys32_writev and sys32_readv.Ulf Carlsson2000-05-122-3/+154
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* SMP FPU management: similar to what sparc does, no lazy fpu contextKanoj Sarcar2000-05-115-15/+36
| | | | | | switching in SMP mode, use PF_USEDFPU to determine whether a program used the fpu in the last time quantum and so needs the fpu context to be saved during context switch.
* When last_task_used_math gets the cpu, ST0_CU1 is set during contextKanoj Sarcar2000-05-113-23/+90
| | | | | | | | | | | switch. All other FP programs have ST0_CU1 cleared in their thread_struct, so that they incur faults on first touching the FPU, and are made the FPU owner, aka last_task_used_math. used_math determines whether a thread has used the FPU before; if not, the FPU needs to be initialized before it can own the FPU. Note: a FP program that has already been using the fpu (not neccesarily the owner), must reinit the fpu if it uses the fpu in a signal handler; a sigreturn restores the original context, discarding the context of the handler.
* UP FPU state handling fixes: make sure to save the fpu state of theKanoj Sarcar2000-05-102-1/+5
| | | | | | | last fpu owner before we assign the fpu to a new math task. However is mips/mips64 working with this bug? Fix needs to be ported to 2.2/2.3 mips code. Additionally, the mips64 lazy_fpu_switch code seems to have a ".set reorder" at the wrong place.
* *** empty log message ***Ulf Carlsson2000-05-101-2/+0
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* Add sys32_nanosleep to get syslogd working.Ulf Carlsson2000-05-102-3/+56
| | | | Add sys32_sched_rr_get_interval while I'm at it.
* Bomb little endian compiles for select32, so that the little endian guysKanoj Sarcar2000-05-081-0/+4
| | | | can look at the issue and develope code appropriately.
* Forkdrop IA64 version of sys32_select. Forklift the sparc64 version.Kanoj Sarcar2000-05-071-18/+79
| | | | | When will I learn sparc64 is bigendian like mips64, and ia64 is little endian?
* Forklift sys32_select from IA64 code.Kanoj Sarcar2000-05-042-1/+103
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* More low level debugging stuff that can be turned on with DEBUG_MIPS64.Kanoj Sarcar2000-05-032-0/+16
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* Change the output format of /proc/cpuinfo slightly to report the numberKanoj Sarcar2000-05-021-0/+2
| | | | of cpus.
* SMP debugging enhancements.Kanoj Sarcar2000-05-011-2/+3
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* Have the slave cpus go into the reschedule loop to pick up tasks andKanoj Sarcar2000-04-271-1/+1
| | | | execute them.
* sigprocmask needs to be 32-bitized.Kanoj Sarcar2000-04-272-1/+20
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* Fix the sysentry debugging code: can never do a SAVE_SOME with intrsKanoj Sarcar2000-04-261-2/+5
| | | | | enabled, that might wipe out the effects of the previous SAVE_SOME done at the beginning of handle_sys.
* Make the sysentry debugging code a little more versatile.Kanoj Sarcar2000-04-251-2/+1
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* We use the ST0_CU0 bit to determine whether we are coming intoKanoj Sarcar2000-04-252-1/+13
| | | | | | | | | | kernel mode for the first time from user mode (on intr/exception/ syscall etc). If so, we need to set the sp to point to the kernel stack. On UP kernels, the kernel stack pointer is stored in the global variable "kernelsp". For SMP kernel, the physical address of the current task structure is stuffed into the watchlo/watchhi registers, so on first entry into the kernel, we need to munge this value properly to setup the sp register.
* scall_64.S: Move to kernel mode and enable intrs properly.Kanoj Sarcar2000-04-232-7/+16
| | | | | | | | r4k_tlb_glue.S: The fast handlers must work with intrs disabled, since we can not risk changes in entryhi/lo/tlbregisters. do_page_fault() _must_ work with intrs enabled, to prevent deadlocks in the intercpu tlbflush code. andes.c/r4xx0.c: Make tlb register accesses conservatively safe from intrs coming in and changing register contents.
* Change all instances of __SMP__ to CONFIG_SMP and includeRalf Baechle2000-04-231-1/+3
| | | | <linux/config.h> where necessary.
* First cut at intercpu tlb flushing.Kanoj Sarcar2000-04-221-4/+63
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* Per cpu tlbpid (asid) management for SMP. The asid cache is now perKanoj Sarcar2000-04-221-1/+4
| | | | cpu, and stays in cpu_data[].
* Delete unused junk "current_pgd".Kanoj Sarcar2000-04-212-2/+0
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* Pause fix for mips64.Ralf Baechle2000-04-193-2/+9
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* Intercpu interrupt changes: add in dedicated intr levels for rescheduleKanoj Sarcar2000-04-171-16/+81
| | | | and call function interrupts (tlbflush for later).
* Fix this UP/MP microoptimization business with cpu_data[] andKanoj Sarcar2000-04-081-1/+3
| | | | | boot_cpu_data once and for all. Generic mips64/IP27 code wants to do cpu_data[cpuid] everywhere ...
* Fix semaphores in modules.Ralf Baechle2000-04-071-0/+8
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* Clear the TS bit from the master's status register (don't know whyKanoj Sarcar2000-04-072-2/+6
| | | | | | | | PROM is getting the bit set before entry into kernel). Fix per cpu frequency reporting. Fix bug so that we do not clear information about mips4 availability. Have the slaves flush their cache/tlb and set status based on what the master processor did.
* Make the initial status register setting code for slaves similar to theKanoj Sarcar2000-04-061-16/+19
| | | | master.
* Create idle threads for the slave processors and put them in theirKanoj Sarcar2000-04-061-1/+1
| | | | resched loops.
* Oops, I had overwritten head.S completely with another C file. Fixing.Kanoj Sarcar2000-04-051-127/+92
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* Try to launch all the slave cpus in the system. Currently, I _think_Kanoj Sarcar2000-04-052-81/+128
| | | | | | only the slave on the same node as the master gets launched, investigating why the slaves on the other nodes are not ... Slave processors use a static stack surrently while booting up.
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