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path: root/arch/mips64/sgi-ip27/ip27-pci.c
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* Fix stupid compile error.Ralf Baechle2001-05-251-2/+2
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* Polish a bit; no functional changes.Ralf Baechle2001-05-241-18/+13
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* Delete some of the IOC3 PCI fixup code which has become redundant afterRalf Baechle2001-05-231-49/+20
| | | | | the recent changes to the pcibios read/write functions and ioc3-eth.c changes.
* Some more PCI kludgeology to support the IOC3.Ralf Baechle2001-05-221-1/+9
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* Iomem address space is also 64-bit on IP27. This brings us back 5 outRalf Baechle2001-05-211-0/+1
| | | | | | of 6 unrecognized IOC3 interfaces on posix0. The leftover two are missing due to IOC3 PCI interface bugs which I'll fight next. After a decent nap ...
* Increase the total number of PCI busses supported.Kanoj Sarcar2001-03-021-1/+1
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* Erase all traces of the ioc3-eth driver irq hacks.Kanoj Sarcar2000-09-071-2/+3
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* Slightly tweak how the ioc3 fixup interacts with serial driver. Also,Kanoj Sarcar2000-08-311-1/+2
| | | | | hardcode the 0xFF00 value into subsystem_vendor, instead of relying on PCI commands to ioc3 to do this.
* No more hardcoded serial port addresses. Get the serial driver probingKanoj Sarcar2000-08-311-0/+16
| | | | addresses for ports. Serial driver changes are being sent to Linus.
* Do the bare minimum pci fixups needed for the IOC3, not more ...Kanoj Sarcar2000-08-241-3/+0
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* Kill warnings in the 64-bit kernel.Ralf Baechle2000-07-091-5/+2
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* Add the node offset to the IOC3 to the PCI resourceUlf Carlsson2000-06-011-0/+4
| | | | | address for all IOC3 devices. We will now be able to reach IOC3 cards on other nodes than the first one.
* Remove all IOC3 hacks. IOC3 now allocates it's resources the same wayRalf Baechle2000-05-301-11/+39
| | | | | that all others do. Further cleanup to make ioc3-eth.c start looking like a driver.
* Implement a more dynamic method of associating IRQs with PCI devices.Kanoj Sarcar2000-05-191-18/+49
| | | | | Instead of encoding bus/slot numbers in the IRQ, have seperate arrays to store that information.
* irq.h: With the current scheme of encoding the bus number into theKanoj Sarcar2000-05-181-0/+1
| | | | | | | pci irq, we need to bump up NR_IRQs to handle more than 4 PCI busses. io.h: Port numbers are really "unsigned long", since they need to contain the nasids too. ip27-pci.c: Encode the nasid into the port number for isp1020 for pio.
* Move the intercpu intr irq numbers to the lowest possible. AssignKanoj Sarcar2000-05-151-13/+29
| | | | | | | all PCI irqs above that. Fix pci_map_irq to not just have 2 bits for slot number, else irq numbers will not be unique. Include the bus number as part of the irq for now, so that scsi controllers on various PCI busses get unique irq numbers.
* Some infrastructure for supporting multiple pci busses on origin200/2000.Leo Dagum2000-05-111-85/+117
| | | | | | | nasid and widget id get incoded in pci_dev->irq. pcibr_setup() now does some rudimentary probing for bridge widgets hanging off its xbow. We're not seeing interrupts from remote devices at the cpu, so mscsi card's are turned off for now.
* More placeholder stuff. Added pci_fixup_isp2x00() routine to set upLeo Dagum2000-03-301-2/+68
| | | | | | the device's config space registers and turn on byte swizzling in the bridge for this device (needs to be done before the driver sees it). Again, hardwired to slot 5. Will generalize later.
* Merge with Linux 2.3.40.Ralf Baechle2000-02-161-2/+11
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* Merge with Linux 2.3.32.Ralf Baechle2000-02-041-3/+1
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* Fix build problems after the 2.3.38 merge.Kanoj Sarcar2000-02-031-2/+19
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* Update the IOC3 pci write hack to encompass all writes to the IOC3.Kanoj Sarcar2000-01-311-16/+5
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* Merge with Linux 2.3.23. The new bootmem stuff has broken variousRalf Baechle2000-01-271-4/+0
| | | | | platforms. At this time I've only verified that IP22 support compiles and IP27 actually works.
* 1. Setup the qlogic chips so that the driver decides to use io-mappedKanoj Sarcar2000-01-261-2/+31
| | | | | | | | | | style access instead of memory-mapped style access. Older qlogic drivers only support io-mapped style access, the 2.3.40 driver supports both; it is just easier to get things working with io-mapped access. 2. To achieve above, get CF0_WRITE_PCI_CFG to actually program the registers ... properly. 3. Hack CF0_WRITE_PCI_CFG so that it still only does real work in the above case ... else things hangs. To be investigated.
* Similar to a bunch of other architectures, extend the range of possibleKanoj Sarcar2000-01-251-0/+1
| | | | | ioport values to prevent gratuitous check_region failures from qlogic driver.
* Add {get,put}_user()-style functions that are protected against DBE.Ralf Baechle2000-01-201-0/+219
Unlike the IRIX functions they only have one instruction overhead per access, don't involve subroutine calls or any spinlocks, so are implicitly threadsafe. Add PCI infrastructure for SN0 + the necessary fixups for IOC3 brokeness.
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