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* irq.h: With the current scheme of encoding the bus number into theKanoj Sarcar2000-05-181-0/+1
* Misc fixes.Kanoj Sarcar2000-05-171-8/+7
* Modify the SMP bootup sequence slightly, so that the master waitsKanoj Sarcar2000-05-171-5/+7
* The device initialization code can not assume it is being invoked onKanoj Sarcar2000-05-171-1/+2
* Fix the bridge register programming to indicate a 1:1 mapping betweenKanoj Sarcar2000-05-161-2/+3
* Move the intercpu intr irq numbers to the lowest possible. AssignKanoj Sarcar2000-05-152-61/+52
* Fix races in the low level intr handling code to prevent intr lossKanoj Sarcar2000-05-131-14/+28
* Rudimentary nmi support to be able to do simple debugging on SMPKanoj Sarcar2000-05-123-1/+169
* Enable "reboot"ing the system.Kanoj Sarcar2000-05-111-1/+20
* Some infrastructure for supporting multiple pci busses on origin200/2000.Leo Dagum2000-05-113-195/+377
* SMP bootup and slave processor wakeup needs to be improved, but forKanoj Sarcar2000-05-031-1/+1
* Multicpu boot fixes: 1. make sure each cpu only picks up the interruptsKanoj Sarcar2000-05-021-6/+31
* Initialize the slave cpu tlb registers during bootup.Kanoj Sarcar2000-04-261-0/+2
* Enalbe interrupts on slave cpus.Kanoj Sarcar2000-04-261-0/+1
* Pick a name for the idle process on each cpu - easier for debugging.Kanoj Sarcar2000-04-241-0/+1
* scall_64.S: Move to kernel mode and enable intrs properly.Kanoj Sarcar2000-04-231-1/+5
* First cut at intercpu tlb flushing.Kanoj Sarcar2000-04-221-1/+1
* Per cpu tlbpid (asid) management for SMP. The asid cache is now perKanoj Sarcar2000-04-221-0/+2
* Merge with Linux 2.3.99-pre4.Ralf Baechle2000-04-191-1/+1
* Obligatory UP compile fixes after SMP code changes ...Kanoj Sarcar2000-04-171-4/+2
* Intercpu interrupt changes: add in dedicated intr levels for rescheduleKanoj Sarcar2000-04-171-8/+25
* More intercpu interrupt work: we now have a low level inter cpu intrKanoj Sarcar2000-04-172-26/+42
* Revert to the older irq - pendlevel mapping.Kanoj Sarcar2000-04-121-2/+2
* Move the irq to swlevel mappings a little bit to make space for theKanoj Sarcar2000-04-121-3/+4
* The state of the two interrupt mask registers for the 128 intr levelsKanoj Sarcar2000-04-121-4/+15
* Allow the low level ISR to be able to handle intrs on cpu A or B.Kanoj Sarcar2000-04-121-4/+6
* Moved set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1)Leo Dagum2000-04-101-1/+1
* Fixed bridge_init() so it sets registers for theLeo Dagum2000-04-101-2/+5
* New code to install and enable interrupt handlers for intercpu intrs.Kanoj Sarcar2000-04-082-8/+70
* For slave nodes, make sure not to touch the lower part of their localKanoj Sarcar2000-04-081-6/+1
* Fix this UP/MP microoptimization business with cpu_data[] andKanoj Sarcar2000-04-081-2/+0
* Take notes before I forget ...Kanoj Sarcar2000-04-081-0/+3
* Make it so that clock interrupts can be received on all cpus on the node.Kanoj Sarcar2000-04-081-2/+3
* Minor cleanup - do not invent new synonyms. Use ST0_IE instead of new nameKanoj Sarcar2000-04-071-4/+2
* Last tweak before enabling intrs on slave cpus ... set their intr maskKanoj Sarcar2000-04-071-0/+2
* Clear the TS bit from the master's status register (don't know whyKanoj Sarcar2000-04-072-4/+16
* Initial attempt at seperating out per-cpu and per-hub code that needs toKanoj Sarcar2000-04-074-26/+94
* Create idle threads for the slave processors and put them in theirKanoj Sarcar2000-04-061-11/+77
* Fix UP compiles.Kanoj Sarcar2000-04-051-0/+7
* Try to launch all the slave cpus in the system. Currently, I _think_Kanoj Sarcar2000-04-051-1/+18
* Record nasid/cnode/cpuslice in the per cpu data structure during boot up.Kanoj Sarcar2000-04-042-13/+32
* Added a few klconfig functions from IRIX. This triggered some house cleaning,Kanoj Sarcar2000-04-044-68/+122
* Rudimentary code to launch slave processors by the master processor.Kanoj Sarcar2000-04-041-1/+123
* More placeholder stuff. Added pci_fixup_isp2x00() routine to set upLeo Dagum2000-03-301-2/+68
* Added pcibr_setup() routine to initialize some bridge registers differentLeo Dagum2000-03-301-1/+24
* Interrupts need to start at bit 7 in INT_PEND0 registers because bits [0..6]Leo Dagum2000-03-301-13/+44
* ip27-timer.c: The timer interrupt for SMP machines must do some extraKanoj Sarcar2000-03-271-1/+30
* ip27-irq.c, system.h: implement SMP intr on/off primitives similar to i386.Kanoj Sarcar2000-03-261-5/+189
* Minor memory accounting bug fixes to get cat /proc/meminfo and bootupKanoj Sarcar2000-03-251-2/+7
* The fast tlb handlers [x]tlb_refill_debug blindly look at pgd/pmd/ptes.Kanoj Sarcar2000-03-161-0/+1
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