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* Initialize the slave cpu tlb registers during bootup.Kanoj Sarcar2000-04-261-0/+2
* Fix the sysentry debugging code: can never do a SAVE_SOME with intrsKanoj Sarcar2000-04-261-2/+5
* Enalbe interrupts on slave cpus.Kanoj Sarcar2000-04-261-0/+1
* Make the sysentry debugging code a little more versatile.Kanoj Sarcar2000-04-252-2/+8
* We use the ST0_CU0 bit to determine whether we are coming intoKanoj Sarcar2000-04-252-1/+13
* Pick a name for the idle process on each cpu - easier for debugging.Kanoj Sarcar2000-04-241-0/+1
* Fix the init_new_context code not to zap the percpu tlbpid array whenKanoj Sarcar2000-04-242-4/+4
* scall_64.S: Move to kernel mode and enable intrs properly.Kanoj Sarcar2000-04-235-23/+36
* Change all instances of __SMP__ to CONFIG_SMP and includeRalf Baechle2000-04-231-1/+3
* First cut at intercpu tlb flushing.Kanoj Sarcar2000-04-224-7/+66
* Per cpu tlbpid (asid) management for SMP. The asid cache is now perKanoj Sarcar2000-04-225-69/+91
* Delete unused junk "current_pgd".Kanoj Sarcar2000-04-212-2/+0
* Merge with Linux 2.3.99-pre4.Ralf Baechle2000-04-195-36/+104
* Pause fix for mips64.Ralf Baechle2000-04-193-2/+9
* Obligatory UP compile fixes after SMP code changes ...Kanoj Sarcar2000-04-171-4/+2
* Intercpu interrupt changes: add in dedicated intr levels for rescheduleKanoj Sarcar2000-04-172-24/+106
* More intercpu interrupt work: we now have a low level inter cpu intrKanoj Sarcar2000-04-172-26/+42
* Revert to the older irq - pendlevel mapping.Kanoj Sarcar2000-04-121-2/+2
* Move the irq to swlevel mappings a little bit to make space for theKanoj Sarcar2000-04-121-3/+4
* The state of the two interrupt mask registers for the 128 intr levelsKanoj Sarcar2000-04-121-4/+15
* Allow the low level ISR to be able to handle intrs on cpu A or B.Kanoj Sarcar2000-04-121-4/+6
* Moved set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1)Leo Dagum2000-04-101-1/+1
* Fixed bridge_init() so it sets registers for theLeo Dagum2000-04-101-2/+5
* New code to install and enable interrupt handlers for intercpu intrs.Kanoj Sarcar2000-04-082-8/+70
* For slave nodes, make sure not to touch the lower part of their localKanoj Sarcar2000-04-081-6/+1
* Fix this UP/MP microoptimization business with cpu_data[] andKanoj Sarcar2000-04-082-3/+3
* Take notes before I forget ...Kanoj Sarcar2000-04-081-0/+3
* Make it so that clock interrupts can be received on all cpus on the node.Kanoj Sarcar2000-04-081-2/+3
* Fix semaphores in modules.Ralf Baechle2000-04-071-0/+8
* Minor cleanup - do not invent new synonyms. Use ST0_IE instead of new nameKanoj Sarcar2000-04-071-4/+2
* Last tweak before enabling intrs on slave cpus ... set their intr maskKanoj Sarcar2000-04-071-0/+2
* Clear the TS bit from the master's status register (don't know whyKanoj Sarcar2000-04-074-6/+22
* Initial attempt at seperating out per-cpu and per-hub code that needs toKanoj Sarcar2000-04-074-26/+94
* Make the initial status register setting code for slaves similar to theKanoj Sarcar2000-04-061-16/+19
* Create idle threads for the slave processors and put them in theirKanoj Sarcar2000-04-062-12/+78
* Fix UP compiles.Kanoj Sarcar2000-04-051-0/+7
* Oops, I had overwritten head.S completely with another C file. Fixing.Kanoj Sarcar2000-04-051-127/+92
* Try to launch all the slave cpus in the system. Currently, I _think_Kanoj Sarcar2000-04-053-82/+146
* o 32-bit ioctls (some at least)Ulf Carlsson2000-04-055-23/+793
* Record nasid/cnode/cpuslice in the per cpu data structure during boot up.Kanoj Sarcar2000-04-042-13/+32
* Added a few klconfig functions from IRIX. This triggered some house cleaning,Kanoj Sarcar2000-04-044-68/+122
* Rudimentary code to launch slave processors by the master processor.Kanoj Sarcar2000-04-041-1/+123
* Rudimentary sendintr() routine to send intrs to other cpus. This needs toKanoj Sarcar2000-04-011-0/+37
* save_and_cli and restore_flags ... not save_and_cli and __restore_flags ...Kanoj Sarcar2000-03-311-1/+1
* More placeholder stuff. Added pci_fixup_isp2x00() routine to set upLeo Dagum2000-03-301-2/+68
* Added pcibr_setup() routine to initialize some bridge registers differentLeo Dagum2000-03-301-1/+24
* Interrupts need to start at bit 7 in INT_PEND0 registers because bits [0..6]Leo Dagum2000-03-301-13/+44
* When saving syscalls also save a6 and a7. We may need them later forRalf Baechle2000-03-281-0/+2
* Set ST0_FR the right way.Ralf Baechle2000-03-281-3/+3
* Merge with Linux 2.3.99-pre3.Ralf Baechle2000-03-274-7/+34
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