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* Add sys32_writev and sys32_readv.Ulf Carlsson2000-05-122-3/+154
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* Rudimentary nmi support to be able to do simple debugging on SMPKanoj Sarcar2000-05-123-1/+169
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* Enable "reboot"ing the system.Kanoj Sarcar2000-05-111-1/+20
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* SMP FPU management: similar to what sparc does, no lazy fpu contextKanoj Sarcar2000-05-115-15/+36
| | | | | | switching in SMP mode, use PF_USEDFPU to determine whether a program used the fpu in the last time quantum and so needs the fpu context to be saved during context switch.
* When last_task_used_math gets the cpu, ST0_CU1 is set during contextKanoj Sarcar2000-05-113-23/+90
| | | | | | | | | | | switch. All other FP programs have ST0_CU1 cleared in their thread_struct, so that they incur faults on first touching the FPU, and are made the FPU owner, aka last_task_used_math. used_math determines whether a thread has used the FPU before; if not, the FPU needs to be initialized before it can own the FPU. Note: a FP program that has already been using the fpu (not neccesarily the owner), must reinit the fpu if it uses the fpu in a signal handler; a sigreturn restores the original context, discarding the context of the handler.
* Some infrastructure for supporting multiple pci busses on origin200/2000.Leo Dagum2000-05-113-195/+377
| | | | | | | nasid and widget id get incoded in pci_dev->irq. pcibr_setup() now does some rudimentary probing for bridge widgets hanging off its xbow. We're not seeing interrupts from remote devices at the cpu, so mscsi card's are turned off for now.
* UP FPU state handling fixes: make sure to save the fpu state of theKanoj Sarcar2000-05-102-1/+5
| | | | | | | last fpu owner before we assign the fpu to a new math task. However is mips/mips64 working with this bug? Fix needs to be ported to 2.2/2.3 mips code. Additionally, the mips64 lazy_fpu_switch code seems to have a ".set reorder" at the wrong place.
* Sony name change patches from Geert.Ralf Baechle2000-05-107-7/+7
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* *** empty log message ***Ulf Carlsson2000-05-101-2/+0
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* Add sys32_nanosleep to get syslogd working.Ulf Carlsson2000-05-102-3/+56
| | | | Add sys32_sched_rr_get_interval while I'm at it.
* Bomb little endian compiles for select32, so that the little endian guysKanoj Sarcar2000-05-081-0/+4
| | | | can look at the issue and develope code appropriately.
* Forkdrop IA64 version of sys32_select. Forklift the sparc64 version.Kanoj Sarcar2000-05-071-18/+79
| | | | | When will I learn sparc64 is bigendian like mips64, and ia64 is little endian?
* Revert kernel page allocationFlorian Lohoff2000-05-041-20/+0
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* Forklift sys32_select from IA64 code.Kanoj Sarcar2000-05-042-1/+103
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* More low level debugging stuff that can be turned on with DEBUG_MIPS64.Kanoj Sarcar2000-05-033-0/+29
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* SMP bootup and slave processor wakeup needs to be improved, but forKanoj Sarcar2000-05-031-1/+1
| | | | now, allow smp kernels to boot up on single cpu systems at least.
* Change the output format of /proc/cpuinfo slightly to report the numberKanoj Sarcar2000-05-021-0/+2
| | | | of cpus.
* Multicpu boot fixes: 1. make sure each cpu only picks up the interruptsKanoj Sarcar2000-05-021-6/+31
| | | | | | | that are not masked on it. 2. hack around a single irq_action list, instead of a per cpu/hub irq_action list; for the intercpu intrs, the master cpu sets up the irq_action block, whereas all cpus just program their mask/hub registers to be able to receive the interrupts.
* SMP debugging enhancements.Kanoj Sarcar2000-05-013-3/+4
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* Print out cpu number in debug statements for SMP debugging.Kanoj Sarcar2000-04-281-4/+4
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* Update defconfig files. Nastyness: 2.3.99 builds only with sysctlsRalf Baechle2000-04-284-6/+7
| | | | enabled and for headless systems Magic Sysrq disabled.
* Merge with 2.3.99-pre6.Ralf Baechle2000-04-28210-6311/+5686
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* Have the slave cpus go into the reschedule loop to pick up tasks andKanoj Sarcar2000-04-271-1/+1
| | | | execute them.
* sigprocmask needs to be 32-bitized.Kanoj Sarcar2000-04-272-1/+20
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* Initialize the slave cpu tlb registers during bootup.Kanoj Sarcar2000-04-261-0/+2
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* Fix the sysentry debugging code: can never do a SAVE_SOME with intrsKanoj Sarcar2000-04-261-2/+5
| | | | | enabled, that might wipe out the effects of the previous SAVE_SOME done at the beginning of handle_sys.
* Enalbe interrupts on slave cpus.Kanoj Sarcar2000-04-261-0/+1
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* Make the sysentry debugging code a little more versatile.Kanoj Sarcar2000-04-252-2/+8
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* We use the ST0_CU0 bit to determine whether we are coming intoKanoj Sarcar2000-04-252-1/+13
| | | | | | | | | | kernel mode for the first time from user mode (on intr/exception/ syscall etc). If so, we need to set the sp to point to the kernel stack. On UP kernels, the kernel stack pointer is stored in the global variable "kernelsp". For SMP kernel, the physical address of the current task structure is stuffed into the watchlo/watchhi registers, so on first entry into the kernel, we need to munge this value properly to setup the sp register.
* Pick a name for the idle process on each cpu - easier for debugging.Kanoj Sarcar2000-04-241-0/+1
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* Fix the init_new_context code not to zap the percpu tlbpid array whenKanoj Sarcar2000-04-242-4/+4
| | | | | | doing a clone-vm operation. Also, the intercpu tlbflush code now properly does its job by flushing the tlbpid only on the current processor, and not on all.
* scall_64.S: Move to kernel mode and enable intrs properly.Kanoj Sarcar2000-04-235-23/+36
| | | | | | | | r4k_tlb_glue.S: The fast handlers must work with intrs disabled, since we can not risk changes in entryhi/lo/tlbregisters. do_page_fault() _must_ work with intrs enabled, to prevent deadlocks in the intercpu tlbflush code. andes.c/r4xx0.c: Make tlb register accesses conservatively safe from intrs coming in and changing register contents.
* Change all instances of __SMP__ to CONFIG_SMP and includeRalf Baechle2000-04-232-3/+5
| | | | <linux/config.h> where necessary.
* First cut at intercpu tlb flushing.Kanoj Sarcar2000-04-224-7/+66
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* Per cpu tlbpid (asid) management for SMP. The asid cache is now perKanoj Sarcar2000-04-225-69/+91
| | | | cpu, and stays in cpu_data[].
* Delete unused junk "current_pgd".Kanoj Sarcar2000-04-212-2/+0
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* Don't overwrite the cache exception handler.Ralf Baechle2000-04-211-3/+1
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* Merge with Linux 2.3.99-pre5.Ralf Baechle2000-04-194-462/+546
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* Merge with Linux 2.3.99-pre4.Ralf Baechle2000-04-19147-2302/+3886
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* Pause fix for mips64.Ralf Baechle2000-04-193-2/+9
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* Pause(2) fix for 2.3.Ralf Baechle2000-04-184-189/+36
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* Obligatory UP compile fixes after SMP code changes ...Kanoj Sarcar2000-04-171-4/+2
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* Intercpu interrupt changes: add in dedicated intr levels for rescheduleKanoj Sarcar2000-04-172-24/+106
| | | | and call function interrupts (tlbflush for later).
* More intercpu interrupt work: we now have a low level inter cpu intrKanoj Sarcar2000-04-172-26/+42
| | | | handler.
* Revert to the older irq - pendlevel mapping.Kanoj Sarcar2000-04-121-2/+2
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* Move the irq to swlevel mappings a little bit to make space for theKanoj Sarcar2000-04-121-3/+4
| | | | inter cpu intrs at the same level as IRIX.
* The state of the two interrupt mask registers for the 128 intr levelsKanoj Sarcar2000-04-121-4/+15
| | | | for each cpu in the hub is now stored in the per processor data area.
* Allow the low level ISR to be able to handle intrs on cpu A or B.Kanoj Sarcar2000-04-121-4/+6
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* Moved set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1)Leo Dagum2000-04-101-1/+1
| | | | outside is_slave conditional. All cpu's need to call this now.
* Fixed bridge_init() so it sets registers for theLeo Dagum2000-04-101-2/+5
| | | | | | | | calling process's bridge (not necessarily node 0), and removed call to set_cp0_status() (now in per_cpu_init()). b_wid_int_upper still points to node 0, I don't want to change this till I have a multinode system and kernel to test on.
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