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* Merge with Linux 2.4.0-test6-pre10.Ralf Baechle2000-08-2553-301/+1529
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* Merge with Linux 2.4.0-test6-pre9.Ralf Baechle2000-08-252-1/+15
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* Do the bare minimum pci fixups needed for the IOC3, not more ...Kanoj Sarcar2000-08-241-3/+0
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* On an SMP system, every cpu should use the master node's IOC3 uart portKanoj Sarcar2000-08-241-3/+2
| | | | for printk output, instead of trying to access its own.
* Use prom_printf() as the primary method of doing printks() for IP27.Kanoj Sarcar2000-08-241-0/+24
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* Make prom_printf() functional on IP27s. And prom_printf() is not anKanoj Sarcar2000-08-232-2/+28
| | | | init function, it needs to be around during regular system usage.
* Also output struct task_struct.pid in offsets.h.Ralf Baechle2000-08-221-0/+1
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* Yet more RM7000 hooks.Ralf Baechle2000-08-221-2/+10
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* One more RM7000 hook.Ralf Baechle2000-08-221-0/+1
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* RM7000 has a cycle counter.Ralf Baechle2000-08-221-0/+1
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* Don't pretend that a RM7000 is like a R5000.Ralf Baechle2000-08-221-4/+4
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* Add RM7000 config option.Ralf Baechle2000-08-227-0/+7
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* More RM7k hooks.Ralf Baechle2000-08-221-0/+3
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* 7k hooks.Ralf Baechle2000-08-221-0/+4
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* First cut at RM7000 support.Ralf Baechle2000-08-221-0/+578
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* Beautify diagnostic messages.Ralf Baechle2000-08-161-3/+3
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* Kill warning.Ralf Baechle2000-08-091-10/+13
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* More cleaning of struct stat for glibc 2.2. The necessary glibcRalf Baechle2000-08-091-4/+4
| | | | | patches will go into CVS asap. Remove st_flags and st_gen members, nothing ever used them.
* Faster memcpy / copy_{from,to}_user.Ralf Baechle2000-08-091-31/+76
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* Kill BARRIER macro; it's not needed on R10000.Ralf Baechle2000-08-091-25/+0
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* Merge with Linux 2.4.0-test6-pre8.Ralf Baechle2000-08-0833-126/+123
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* Merge with Linux 2.4.0-test6-pre7.Ralf Baechle2000-08-081-2/+2
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* Merge with Linu 2.4.0-test6-pre6.Ralf Baechle2000-08-0813-85/+94
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* Merge with Linux 2.4.0-test6-pre4.Ralf Baechle2000-08-0871-440/+381
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* Merge with Linux 2.4.0-test6-pre3.Ralf Baechle2000-08-084-0/+8
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* Merge with Linux 2.4.0-test6-pre2.Ralf Baechle2000-08-083-8/+16
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* let it compile againHarald Koerfgen2000-08-088-26/+23
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* Merge with Linux 2.4.0-test6-pre1.Ralf Baechle2000-08-086-6/+7
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* Port the recent cache changes forward and backward between mips andRalf Baechle2000-08-086-301/+164
| | | | mips64.
* Tweak the initialization macros so that they work even on a systemKanoj Sarcar2000-08-051-3/+1
| | | | that has no physical address 0 (non nasid 0 systems).
* sys_sysctl implementationUlf Carlsson2000-08-052-1/+89
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* Fix over enthusiastic tlbflush optimizations.Kanoj Sarcar2000-08-031-3/+6
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* r3k_flush_cache_sigtramp() still assumed 8 byte cachelinesHarald Koerfgen2000-08-031-11/+1
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* ARC console is not just for IP22.Keith M Wesolowski2000-08-0113-426/+122
| | | | Timer dead code cleanup.
* Compile fix: get the ip27-timer.c code that updates process times lookingKanoj Sarcar2000-08-011-25/+10
| | | | like its i386 counterpart.
* R3000 cache bugfix from Maciej.Ralf Baechle2000-07-311-1/+1
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* Shave of 50% of lat_mmap. Our cache routines were plain stupid.Ralf Baechle2000-07-315-63/+85
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* We set the text variable but never used it.Ralf Baechle2000-07-301-14/+0
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* Some of the r4k_flush_page_to_ram variants were identical.Ralf Baechle2000-07-301-28/+17
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* Cleanup r4k_flush_page_to_ram_*() functions.Ralf Baechle2000-07-301-88/+21
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* Smarter and more scalable tlb flushing routines. No need to interruptKanoj Sarcar2000-07-301-12/+43
| | | | | | other cpus when flushing tlbs for single threaded mm's. Rather, just make sure the mm will have to do a new context allocation if it runs on the other cpus.
* Allow selection of PS/2 mouse again on IP22.Keith M Wesolowski2000-07-291-0/+4
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* Merge with 2.4.0-test5 final.Ralf Baechle2000-07-2821-144/+36
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* Merge with Linux 2.4.0-test5-pre6.Ralf Baechle2000-07-282-46/+76
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* Merge with Linux 2.4.0-test5-pre5.Ralf Baechle2000-07-277-60/+42
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* Optimized cache flushing on r10k/o200s, assuming processor handlesKanoj Sarcar2000-07-271-103/+20
| | | | | VCEs in hardwire, and system guarantees io coherency. Only need to do cache flushes for icache coherency.
* Apply the update_mmu_cache patch also to 32-bit mips.Ralf Baechle2000-07-263-3/+14
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* Optimize andes_clear_page() and andes_copy_page() with prefetchRalf Baechle2000-07-261-16/+23
| | | | | | | operations. While those routines are now 30% - 60% faster it turned out that their influence on realworld applications and benchmars is fairly low; I saw an improvment of ~ 3% for lmbench exec sh and even less for other benches.
* When a debugger faults in a page for a debugee, we do not need to updateKanoj Sarcar2000-07-252-0/+12
| | | | | | the mmu cache/tlbs, since the debugger will use a kernel address to access the page, and not the user address. This should fix the strace warning messages that Ralf and Ulf have seen. Fix should be backported into MIPS.
* Name change: the generic call flush_cache_all() does not do anythingKanoj Sarcar2000-07-247-24/+24
| | | | | anymore. All the flush_cache_all() calls in MIPS code is changed to call flush_cache_l1(), and ends up flushing the L1 i/d caches.
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