| Commit message (Collapse) | Author | Age | Files | Lines |
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silly check in pmd_alloc_kernel.
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are stashed in an array of page tables, starting from kptbl[]. The fast
tlbmiss handler quickly checks to see if the faulting address is in the
vmalloc range, and if so, it uses the translations in the kptbl to update
the tlbs. Still to do: tlb invalid faults in the vmalloc range needs to
be handled properly.
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during bootup.
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might also be used by platforms with memory holes, but uniform access times).
CONFIG_NUMA special code will probably make its way into generic kernel.
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distinct from invalid-pmd-table for use during pmd allocation failure (so as
to differentiate pgd_bad and pgd_none). The bad page table must have invalid
pte entries to catch any user references to the range of virtual addresses
it covers.
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initialization. Make sure to allocate only one page for the page table
(prevent memory leaks), since only one page is freed up.
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would core dump as soon as someone (rpc.mountd) wanted to talk to it.
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kernel to match each other and the the glibc definition. The glibc
part of this change has been sent to Andreas.
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something.
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possible. Chainsawed RM200 kernel to compile again. Jazz machine
status unknown.
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top of the replicated kernel text thinking it is unused memory. This
lets us get to multiuser on a replicated kernel text system.
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nasids that the master nasid found for it. Sanitize the replication
procedures.
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code.
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tell it where to get the kernel data from (ie, which nasid holds the
kernel data). Remove debug cruft from head.S.
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massaged bootstrap address so that the PRM launches the slaves into
legal code.
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IRIX, to get the same kind of loader behavior. Read comments in
mapped_kernel.h for more details.
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pass the proper address for the slave bootstrap routine based on where
the kernel is compiled at.
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now accept the kernel assigned cpuid (instead of the prom assigned
id) as input/index. The only exception is the early boot up code.
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area to store the PROM assigned cpuid that is used by most of the IP27
kernel and prom data strucutures.
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* #include <asm/offset.h> #ifdef'd: init/main.c and $(arch)/tools/offset.c
compile without include/asm-$(ARCH)/offset.h.
* include/asm-$(ARCH)/offset.h is now depending on $(TOPDIR)/.config:
offset.h is beeing rebuilt when .config changes. Please don't count on
that, makedep doesn't do it's job very well in this case and objects
depending on offset.h aren't neccesarily rebuilt :(
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the context register as it should be used, but let's look
into that later.
If there is a problem with the code it will crash after
right after freeing unused kernel memery. I have this code
tested on both UP and SMP though.
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This one survives "make distclean" and "make dep clean vmlinux".
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Instead of encoding bus/slot numbers in the IRQ, have seperate arrays
to store that information.
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pci irq, we need to bump up NR_IRQs to handle more than 4 PCI busses.
io.h: Port numbers are really "unsigned long", since they need to
contain the nasids too.
ip27-pci.c: Encode the nasid into the port number for isp1020 for pio.
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architecture specific standard value. Not entirely at the point
where we can send this to Linus.
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Linus. Our diffs relativ to Linus' latest and greatest is getting
fairly small now.
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all PCI irqs above that. Fix pci_map_irq to not just have 2 bits
for slot number, else irq numbers will not be unique. Include the
bus number as part of the irq for now, so that scsi controllers
on various PCI busses get unique irq numbers.
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make sure for the future that the (C) notice is ok. ``unpublished
proprietary information of Silicon Graphics'' isn't good ...
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machines.
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switching in SMP mode, use PF_USEDFPU to determine whether a program
used the fpu in the last time quantum and so needs the fpu context
to be saved during context switch.
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nasid and widget id get incoded in pci_dev->irq. pcibr_setup() now does
some rudimentary probing for bridge widgets hanging off its xbow.
We're not seeing interrupts from remote devices at the cpu,
so mscsi card's are turned off for now.
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struct of the currently executing thread: handle sign extension on
the watchlo register.
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kernel mode for the first time from user mode (on intr/exception/
syscall etc). If so, we need to set the sp to point to the kernel
stack. On UP kernels, the kernel stack pointer is stored in
the global variable "kernelsp". For SMP kernel, the physical
address of the current task structure is stuffed into the
watchlo/watchhi registers, so on first entry into the kernel,
we need to munge this value properly to setup the sp register.
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doing a clone-vm operation. Also, the intercpu tlbflush code now properly
does its job by flushing the tlbpid only on the current processor, and
not on all.
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<linux/config.h> where necessary.
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