From 2cd3e1c9bf87b60bad3bee59fe02cd3294f7aa33 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 6 Nov 2000 22:59:55 +0000 Subject: Partial support for Galileo EV96100 evaluation board. Patches from Pete Popov of Monta Vista. --- arch/mips/defconfig-ev96100 | 419 ++++++++ arch/mips/galileo-boards/ev96100/Makefile | 27 + arch/mips/galileo-boards/ev96100/int-handler.S | 56 ++ arch/mips/galileo-boards/ev96100/irq.c | 351 +++++++ arch/mips/galileo-boards/ev96100/memory.c | 79 ++ arch/mips/galileo-boards/ev96100/pci-dma.c | 51 + arch/mips/galileo-boards/ev96100/prom.c | 42 + arch/mips/galileo-boards/ev96100/puts.c | 102 ++ arch/mips/galileo-boards/ev96100/rtc.c | 50 + arch/mips/galileo-boards/ev96100/setup.c | 169 ++++ arch/mips/galileo-boards/ev96100/time.c | 278 ++++++ arch/mips/galileo-boards/ev96100/uart.S | 92 ++ arch/mips/galileo-boards/generic/Makefile | 41 + arch/mips/galileo-boards/generic/cmdline.c | 61 ++ arch/mips/galileo-boards/generic/init.c | 176 ++++ arch/mips/galileo-boards/generic/pci.c | 340 +++++++ arch/mips/galileo-boards/generic/printf.c | 53 + arch/mips/galileo-boards/generic/prom-no.c | 50 + arch/mips/galileo-boards/generic/reset.c | 60 ++ arch/mips/kernel/Makefile | 12 +- arch/mips/kernel/setup.c | 6 + arch/mips/kernel/sysmips.c | 44 +- drivers/net/Config.in | 3 + drivers/net/Makefile | 1 + drivers/net/gt96100eth.c | 1252 ++++++++++++++++++++++++ drivers/net/gt96100eth.h | 325 ++++++ include/asm-mips/bootinfo.h | 10 +- include/asm-mips/galileo-boards/ev96100.h | 55 ++ include/asm-mips/galileo-boards/ev96100int.h | 12 + include/asm-mips/galileo-boards/gt64120.h | 320 ++++++ include/asm-mips/galileo-boards/gt96100.h | 432 ++++++++ include/asm-mips/io.h | 52 + include/asm-mips/serial.h | 15 +- 33 files changed, 5020 insertions(+), 16 deletions(-) create mode 100644 arch/mips/defconfig-ev96100 create mode 100644 arch/mips/galileo-boards/ev96100/Makefile create mode 100644 arch/mips/galileo-boards/ev96100/int-handler.S create mode 100644 arch/mips/galileo-boards/ev96100/irq.c create mode 100644 arch/mips/galileo-boards/ev96100/memory.c create mode 100644 arch/mips/galileo-boards/ev96100/pci-dma.c create mode 100644 arch/mips/galileo-boards/ev96100/prom.c create mode 100644 arch/mips/galileo-boards/ev96100/puts.c create mode 100644 arch/mips/galileo-boards/ev96100/rtc.c create mode 100644 arch/mips/galileo-boards/ev96100/setup.c create mode 100644 arch/mips/galileo-boards/ev96100/time.c create mode 100644 arch/mips/galileo-boards/ev96100/uart.S create mode 100644 arch/mips/galileo-boards/generic/Makefile create mode 100644 arch/mips/galileo-boards/generic/cmdline.c create mode 100644 arch/mips/galileo-boards/generic/init.c create mode 100644 arch/mips/galileo-boards/generic/pci.c create mode 100644 arch/mips/galileo-boards/generic/printf.c create mode 100644 arch/mips/galileo-boards/generic/prom-no.c create mode 100644 arch/mips/galileo-boards/generic/reset.c create mode 100644 drivers/net/gt96100eth.c create mode 100644 drivers/net/gt96100eth.h create mode 100644 include/asm-mips/galileo-boards/ev96100.h create mode 100644 include/asm-mips/galileo-boards/ev96100int.h create mode 100644 include/asm-mips/galileo-boards/gt64120.h create mode 100644 include/asm-mips/galileo-boards/gt96100.h diff --git a/arch/mips/defconfig-ev96100 b/arch/mips/defconfig-ev96100 new file mode 100644 index 000000000..31587ceea --- /dev/null +++ b/arch/mips/defconfig-ev96100 @@ -0,0 +1,419 @@ +# +# Automatically generated make config: don't edit +# + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_ALGOR_P4032 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_COBALT_MICRO_SERVER is not set +# CONFIG_DECSTATION is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_ORION is not set +CONFIG_MIPS_EV96100=y +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_SBUS is not set +CONFIG_PCI=y +# CONFIG_ISA is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# CPU selection +# +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +CONFIG_CPU_RM7000=y +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +CONFIG_CPU_ADVANCED=y +CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_WB is not set + +# +# General setup +# +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_KCORE_ELF=y +CONFIG_ELF_KERNEL=y +# CONFIG_BINFMT_IRIX is not set +# CONFIG_FORWARD_KEYBOARD is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_NET=y +# CONFIG_PCI_NAMES is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_SYSCTL is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set +# CONFIG_PCMCIA is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_BLK_DEV_LVM is not set +# CONFIG_LVM_PROC_FS is not set + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_NETLINK is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +# CONFIG_UNIX is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set + +# +# +# +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set +# CONFIG_PHONE_IXJ is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_PCI is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_NET_SB1000 is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_NET_ISA is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_AC3200 is not set +# CONFIG_APRICOT is not set +# CONFIG_CS89x0 is not set +# CONFIG_DE4X5 is not set +CONFIG_TULIP=y +# CONFIG_DGRS is not set +# CONFIG_DM9102 is not set +# CONFIG_EEPRO100 is not set +# CONFIG_LNE390 is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NE3210 is not set +# CONFIG_ES3210 is not set +# CONFIG_RTL8129 is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_JOYSTICK is not set + +# +# Input core support is needed for joysticks +# +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_MINIX_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYSV_FS_WRITE is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_MOUNT_SUBDIR is not set +# CONFIG_NCPFS_NDS_DOMAINS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Input core support +# +# CONFIG_INPUT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_MIPS_FPE_MODULE is not set +# CONFIG_REMOTE_DEBUG is not set +# CONFIG_MAGIC_SYSRQ is not set diff --git a/arch/mips/galileo-boards/ev96100/Makefile b/arch/mips/galileo-boards/ev96100/Makefile new file mode 100644 index 000000000..90034f016 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/Makefile @@ -0,0 +1,27 @@ +# +# Copyright 2000 MontaVista Software Inc. +# Author: MontaVista Software, Inc. +# ppopov@mvista.com or support@mvista.com +# +# Makefile for the Galileo EV96100 board. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +all: ev96100.o + +O_TARGET:= ev96100.o + +O_OBJS:= prom.o time.o rtc.o irq.o int-handler.o setup.o puts.o uart.o pci-dma.o memory.o + +dep: + $(CPP) -M *.c > .depend + +include $(TOPDIR)/Rules.make diff --git a/arch/mips/galileo-boards/ev96100/int-handler.S b/arch/mips/galileo-boards/ev96100/int-handler.S new file mode 100644 index 000000000..19bf163d1 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/int-handler.S @@ -0,0 +1,56 @@ +#include +#include +#include +#include + + .text + .set mips1 + .set macro + .set noat + .align 5 + +NESTED(ev96100IRQ, PT_SIZE, sp) + SAVE_ALL + CLI # Important: mark KERNEL mode ! + + /* We're working with 'reorder' set at this point. */ + /* + * Get pending interrupts + */ + + mfc0 t0,CP0_CAUSE # get pending interrupts + mfc0 t1,CP0_STATUS # get enabled interrupts + and t0,t1 # isolate allowed ones + + # FIX ME add R7000 extensions + andi t0,0xff00 # isolate pending bits + andi a0, t0, CAUSEF_IP7 + beq a0, zero, 1f + move a0, sp # delay slot + jal mips_timer_interrupt + j ret_from_irq + nop + + +1: + beqz t0, 3f # spurious interrupt + move a0,t0 + move a1,sp # delay slot + jal do_IRQ + + mfc0 t0,CP0_STATUS # disable interrupts + ori t0,1 + xori t0,1 + mtc0 t0,CP0_STATUS + nop + nop + nop + + la a1, ret_from_irq + jr a1 + +3: j spurious_interrupt + +/* dbg: .asciz "\nev96100IRQ" */ +END(ev96100IRQ) + diff --git a/arch/mips/galileo-boards/ev96100/irq.c b/arch/mips/galileo-boards/ev96100/irq.c new file mode 100644 index 000000000..0458e643b --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/irq.c @@ -0,0 +1,351 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 interrupt/setup routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_int.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +extern void mips_timer_interrupt(int irq, struct pt_regs *regs); +extern asmlinkage void ev96100IRQ(void); +irq_cpustat_t irq_stat[NR_CPUS]; +unsigned int local_bh_count[NR_CPUS]; +unsigned int local_irq_count[NR_CPUS]; +unsigned long spurious_count = 0; +irq_desc_t irq_desc[NR_IRQS]; +irq_desc_t *irq_desc_base = &irq_desc[0]; + +static struct irqaction timer_action = { + NULL, 0, 0, "R7000 timer/counter", NULL, NULL, +}; + +static struct hw_interrupt_type mips_timer = { + "MIPS CPU Timer", + NULL, + NULL, + NULL, /* unmask_irq */ + NULL, /* mask_irq */ + NULL, /* mask_and_ack */ + 0 +}; + +/* Function for careful CP0 interrupt mask access */ +static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) +{ + unsigned long status = read_32bit_cp0_register(CP0_STATUS); + status &= ~((clr_mask & 0xFF) << 8); + status |= (set_mask & 0xFF) << 8; + write_32bit_cp0_register(CP0_STATUS, status); +} + +static inline void mask_irq(unsigned int irq_nr) +{ + modify_cp0_intmask(irq_nr, 0); +} + +static inline void unmask_irq(unsigned int irq_nr) +{ + modify_cp0_intmask(0, irq_nr); +} + +void disable_irq(unsigned int irq_nr) +{ + unsigned long flags; + + save_and_cli(flags); + mask_irq(irq_nr); + restore_flags(flags); +} + +void enable_irq(unsigned int irq_nr) +{ + unsigned long flags; + +#if 0 + printk("enable irq %d\n", irq_nr); + printk("status reg: %x, cause %x\n", + read_32bit_cp0_register(CP0_STATUS), + read_32bit_cp0_register(CP0_CAUSE)); +#endif + save_and_cli(flags); + unmask_irq(irq_nr); + restore_flags(flags); +#if 0 + printk("new status reg: %x, cause %x\n", + read_32bit_cp0_register(CP0_STATUS), + read_32bit_cp0_register(CP0_CAUSE)); +#endif +} + + +void __init ev96100_time_init() +{ + puts("ev96100 time_init\n"); + +} + +int get_irq_list(char *buf) +{ + int i, len = 0, j; + struct irqaction *action; + + len += sprintf(buf + len, " "); + for (j = 0; j < smp_num_cpus; j++) + len += sprintf(buf + len, "CPU%d ", j); + *(char *) (buf + len++) = '\n'; + + for (i = 0; i < NR_IRQS; i++) { + action = irq_desc[i].action; + if (!action || !action->handler) + continue; + len += sprintf(buf + len, "%3d: ", i); + len += sprintf(buf + len, "%10u ", kstat_irqs(i)); + if (irq_desc[i].handler) + len += + sprintf(buf + len, " %s ", + irq_desc[i].handler->typename); + else + len += sprintf(buf + len, " None "); + len += sprintf(buf + len, " %s", action->name); + for (action = action->next; action; action = action->next) { + len += sprintf(buf + len, ", %s", action->name); + } + len += sprintf(buf + len, "\n"); + } + len += sprintf(buf + len, "BAD: %10lu\n", spurious_count); + return len; +} + +asmlinkage void do_IRQ(unsigned long cause, struct pt_regs *regs) +{ + struct irqaction *action; + int cpu; + int status; + int irq; + + //printk("do_IRQ: cause %x *regs %x\n", cause, regs); + /* + * Service one interrupt only. + * The "priority" is not really defined at this point. + * This will change once we add the R7000 extensions. + */ +// if (cause & CAUSEF_IP7) +// irq = 7; + if (cause & CAUSEF_IP6) + irq = 6; + else if (cause & CAUSEF_IP5) + irq = 5; + else if (cause & CAUSEF_IP4) + irq = 4; + else if (cause & CAUSEF_IP3) + irq = 3; + else if (cause & CAUSEF_IP2) + irq = 2; + else if (cause & CAUSEF_IP1) + irq = 1; + else if (cause & CAUSEF_IP0) + irq = 0; + else + return; /* should not happen */ + + cpu = smp_processor_id(); + irq_enter(cpu); + kstat.irqs[cpu][irq]++; + status = 0; + + if (irq_desc[irq].handler && irq_desc[irq].handler->ack) { + irq_desc[irq].handler->ack(irq); + } + + action = irq_desc[irq].action; + + if (action && action->handler) { + //if (!(action->flags & SA_INTERRUPT)) __sti(); + //printk("irq %d, action->handler %x\n", irq, action->handler); + do { + status |= action->flags; + action->handler(irq, action->dev_id, regs); + action = action->next; + } while (action); + //__cli(); + if (irq_desc[irq].handler) { + printk("handler??\n"); + while (1); + if (irq_desc[irq].handler->end) + irq_desc[irq].handler->end(irq); + else if (irq_desc[irq].handler->enable) + irq_desc[irq].handler->enable(irq); + } + } else { + spurious_count++; + //printk(KERN_DEBUG "Unhandled interrupt %x, disabled\n", irq); + printk("Unhandled interrupt %x, disabled\n", irq); + disable_irq(1 << irq); + if (irq_desc[irq].handler->end) + irq_desc[irq].handler->end(irq); + } + + irq_exit(cpu); + + if (softirq_active(cpu) & softirq_mask(cpu)) + do_softirq(); +} + +int request_irq(unsigned int irq, + void (*handler) (int, void *, struct pt_regs *), + unsigned long irqflags, const char *devname, void *dev_id) +{ + struct irqaction *old, **p, *action; + unsigned long flags; + + /* + * IRQs are number 0 through 7, where 0 corresponds to IP0 and + * 7 corresponds to IP7. IP0 and IP1 are software interrupts. IP7 + * is typically the timer interrupt, unless the R7000 extensions are + * used. + */ + + printk("request_irq %d, handler %x\n", irq, handler); + + if (irq >= NR_IRQS) + return -EINVAL; + if (!handler) { + /* Free */ + for (p = &irq_desc[irq].action; (action = *p) != NULL; + p = &action->next) { + /* Found it - now free it */ + save_flags(flags); + cli(); + *p = action->next; + restore_flags(flags); + kfree(action); + return 0; + } + return -ENOENT; + } + + action = (struct irqaction *) + kmalloc(sizeof(struct irqaction), GFP_KERNEL); + if (!action) + return -ENOMEM; + memset(action, 0, sizeof(struct irqaction)); + + save_flags(flags); + cli(); + + action->handler = handler; + action->flags = irqflags; + action->mask = 0; + action->name = devname; + action->dev_id = dev_id; + action->next = NULL; + + p = &irq_desc[irq].action; + + if ((old = *p) != NULL) { + /* Can't share interrupts unless both agree to */ + if (!(old->flags & action->flags & SA_SHIRQ)) + return -EBUSY; + /* add new interrupt at end of irq queue */ + do { + p = &old->next; + old = *p; + } while (old); + } + *p = action; + printk("action %x, action->handler %x\n", + irq_desc[irq].action, irq_desc[irq].action->handler); + + enable_irq(1 << irq); + restore_flags(flags); + return 0; +} + +void free_irq(unsigned int irq, void *dev_id) +{ + printk("free_irq %d\n", irq); + request_irq(irq, NULL, 0, NULL, dev_id); +} + + +unsigned long probe_irq_on(void) +{ + return 0; +} + +int probe_irq_off(unsigned long irqs) +{ + return 0; +} + +int (*irq_cannonicalize) (int irq); + +int ev96100_irq_cannonicalize(int i) +{ + return i; +} + +void __init init_IRQ(void) +{ + puts("init_IRQ\n"); + memset(irq_desc, 0, sizeof(irq_desc)); + irq_cannonicalize = ev96100_irq_cannonicalize; + + /* + irq_desc[EV96100INT_TIMER].handler = &mips_timer; + irq_desc[EV96100INT_TIMER].action = &timer_action; + irq_desc[EV96100INT_TIMER].action->handler = mips_timer_interrupt; + */ + + set_except_vector(0, ev96100IRQ); +} + +EXPORT_SYMBOL(irq_cannonicalize); diff --git a/arch/mips/galileo-boards/ev96100/memory.c b/arch/mips/galileo-boards/ev96100/memory.c new file mode 100644 index 000000000..1512f13ab --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/memory.c @@ -0,0 +1,79 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 prom memory routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/memory.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include + +#include +#include + + +/* #define DEBUG */ + + /* + * FIX ME!!! + */ + + +int __init page_is_ram(unsigned long pagenr) +{ + return 1; +#if 0 + if ((pagenr << PAGE_SHIFT) < mdesc[3].base + mdesc[3].size) + return 1; + + return 0; +#endif +} + + +static inline unsigned long find_max_low_pfn(void) +{ + return 0; +} + +static inline struct prom_pmemblock *find_largest_memblock(void) +{ +} + +void __init prom_meminit(void) +{ +} + +void prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/galileo-boards/ev96100/pci-dma.c b/arch/mips/galileo-boards/ev96100/pci-dma.c new file mode 100644 index 000000000..b66cfbff4 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/pci-dma.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2000 Ani Joshi + * + * + * Dynamic DMA mapping support. + * + * swiped from i386, and cloned for MIPS by Geert. + * + */ + +#include +#include +#include +#include +#include + +/* + * [jsun] We want to return non-cached area so that data can be consistent + * Apparently on x86, this is not an issue because cache is automatically + * invalidated. + * + * To make we are doing the right thing, I add some extra debug macros. + */ + +void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, + dma_addr_t *dma_handle) +{ + void *ret; + int gfp = GFP_ATOMIC; + + printk("pci_alloc_consistent\n"); + if (hwdev == NULL || hwdev->dma_mask != 0xffffffff) + gfp |= GFP_DMA; + ret = (void *)__get_free_pages(gfp, get_order(size)); + + if (ret != NULL) { + dma_cache_inv((unsigned long)ret, size); + *dma_handle = virt_to_bus(ret); + } + ret = (void*) ((unsigned long)ret | 0xA0000000); + printk("ret %x dma_handle %x\n", ret, *dma_handle); + + return ret; +} + +void pci_free_consistent(struct pci_dev *hwdev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + vaddr = (void*) ((unsigned long)vaddr & ~0xA0000000); + free_pages((unsigned long)vaddr, get_order(size)); +} diff --git a/arch/mips/galileo-boards/ev96100/prom.c b/arch/mips/galileo-boards/ev96100/prom.c new file mode 100644 index 000000000..75c3c8a6c --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/prom.c @@ -0,0 +1,42 @@ + +/* + * ev96100_prom.c + * + * BRIEF MODULE DESCRIPTION + * Prom routines supplied by some boot codes. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * pete_popov@mvista.com or support@mvista.com + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +/* FIX ME */ +void __init prom_printf(char *fmt, ...) +{ +} diff --git a/arch/mips/galileo-boards/ev96100/puts.c b/arch/mips/galileo-boards/ev96100/puts.c new file mode 100644 index 000000000..7c2f231e4 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/puts.c @@ -0,0 +1,102 @@ + + +#include +#include + + +//#define SERIAL_BASE EV96100_UART0_REGS_BASE +#define SERIAL_BASE 0xBD000020 +#define NS16550_BASE SERIAL_BASE + +#define SERA_CMD 0x0D +#define SERA_DATA 0x08 +//#define SERB_CMD 0x05 +#define SERB_CMD 20 +#define SERB_DATA 0x00 +#define TX_BUSY 0x20 + +static const char digits[16] = "0123456789abcdef"; +static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE; + + +void putch(const unsigned char c) +{ + unsigned char ch; + unsigned i; + + do { + ch = com1[SERB_CMD]; + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = c; +} + +void putchar(const unsigned char c) +{ + unsigned char ch; + unsigned i; + + do { + ch = com1[SERB_CMD]; + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = c; +} + +void puts(unsigned char *cp) +{ + unsigned char ch; + unsigned i = 0; + + while (*cp) { + do { + ch = com1[SERB_CMD]; + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = *cp++; + } + putch('\r'); + putch('\n'); +} + +void fputs(unsigned char *cp) +{ + unsigned char ch; + unsigned i; + + while (*cp) { + + do { + ch = com1[SERB_CMD]; + } while (0 == (ch & TX_BUSY)); + com1[SERB_DATA] = *cp++; + } +} + + +void put64(uint64_t ul) +{ + int cnt; + unsigned ch; + + cnt = 16; /* 16 nibbles in a 64 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char) (ul >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} + +void put32(unsigned u) +{ + int cnt; + unsigned ch; + + cnt = 8; /* 8 nibbles in a 32 bit long */ + putch('0'); + putch('x'); + do { + cnt--; + ch = (unsigned char) (u >> cnt * 4) & 0x0F; + putch(digits[ch]); + } while (cnt > 0); +} diff --git a/arch/mips/galileo-boards/ev96100/rtc.c b/arch/mips/galileo-boards/ev96100/rtc.c new file mode 100644 index 000000000..697926815 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/rtc.c @@ -0,0 +1,50 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 rtc routines (no rtc on the EV96100). + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +static unsigned char ev96100_rtc_read_data(unsigned long addr) +{ + return 0; +} + +static void ev96100_rtc_write_data(unsigned char data, unsigned long addr) +{ +} + +static int ev96100_rtc_bcd_mode(void) +{ + return 0; +} + +struct rtc_ops ev96100_rtc_ops = { + &ev96100_rtc_read_data, + &ev96100_rtc_write_data, + &ev96100_rtc_bcd_mode +}; diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c new file mode 100644 index 000000000..9292041f8 --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/setup.c @@ -0,0 +1,169 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 setup. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_setup.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + + +#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE) +extern void console_setup(char *, int *); +char serial_console[20]; +#endif + +#ifdef CONFIG_REMOTE_DEBUG +extern void rs_kgdb_hook(int); +extern void saa9730_kgdb_hook(void); +extern void breakpoint(void); +static int remote_debug = 0; +static int kgdb_on_pci = 0; +#endif + +void (*board_time_init) (struct irqaction * irq); +extern void ev96100_time_init(struct irqaction *irq); + +extern void mips_reboot_setup(void); +extern struct rtc_ops ev96100_rtc_ops; +extern struct resource ioport_resource; + +static void __init ev96100_irq_setup(void) +{ + puts("ev96100_irq_setup"); + init_IRQ(); + +#ifdef CONFIG_REMOTE_DEBUG + /* If local serial I/O used for debug port, enter kgdb at once */ + /* Otherwise, this will be done after the SAA9730 is up */ + if (remote_debug && !kgdb_on_pci) { + set_debug_traps(); + breakpoint(); + } +#endif +} + + +void __init ev96100_setup(void) +{ + + unsigned long mem_size, free_start, free_end, start_pfn, + bootmap_size; + +#ifdef CONFIG_REMOTE_DEBUG + int rs_putDebugChar(char); + char rs_getDebugChar(void); + int saa9730_putDebugChar(char); + char saa9730_getDebugChar(void); + extern int (*putDebugChar) (char); + extern char (*getDebugChar) (void); +#endif + char *argptr; + + irq_setup = ev96100_irq_setup; + + puts("ev96100_setup"); + puts("config reg:"); + put32(read_32bit_cp0_register(CP0_CONFIG)); + puts(""); + + +#ifdef CONFIG_SERIAL_CONSOLE + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS0")) == NULL) { + int i = 0; + char *s = prom_getenv("modetty0"); + while (s[i] >= '0' && s[i] <= '9') + i++; + strcpy(serial_console, "ttyS0,"); + strncpy(serial_console + 6, s, i); + //prom_printf("Config serial console: %s\n", serial_console); + puts("Config serial console: %s\n", serial_console); + console_setup(serial_console, NULL); + } +#endif + +#ifdef CONFIG_REMOTE_DEBUG + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { + int line; + argptr += strlen("kgdb=ttyS"); + if (*argptr != '0' && *argptr != '1') + printk("KGDB: Uknown serial line /dev/ttyS%c, " + "falling back to /dev/ttyS1\n", *argptr); + line = *argptr == '0' ? 0 : 1; + printk("KGDB: Using serial line /dev/ttyS%d for session\n", + line ? 1 : 0); + + if (line == 0) { + rs_kgdb_hook(line); + putDebugChar = rs_putDebugChar; + getDebugChar = rs_getDebugChar; + } else { + saa9730_kgdb_hook(); + putDebugChar = saa9730_putDebugChar; + getDebugChar = saa9730_getDebugChar; + kgdb_on_pci = 1; + } + + prom_printf + ("KGDB: Using serial line /dev/ttyS%d for session, " + "please connect your debugger\n", line ? 1 : 0); + + remote_debug = 1; + /* Breakpoints and stuff are in ev96100_irq_setup() */ + } +#endif + argptr = prom_getcmdline(); + + board_time_init = ev96100_time_init; + rtc_ops = &ev96100_rtc_ops; + mips_reboot_setup(); + + /* + * reassign the start and end from the statically defined start and + * end in kernel/resource. + */ + ioport_resource.start = GT_PCI_IO_BASE; + //ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE; + ioport_resource.end = 0xB1FFFFFF; /* what a hack! */ +} diff --git a/arch/mips/galileo-boards/ev96100/time.c b/arch/mips/galileo-boards/ev96100/time.c new file mode 100644 index 000000000..d5e66fe7b --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/time.c @@ -0,0 +1,278 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 rtc routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/atlas/atlas_rtc.c. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include + + +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) + +extern volatile unsigned long wall_jiffies; +static long last_rtc_update = 0; +unsigned long missed_heart_beats = 0; + +static unsigned long r4k_offset; /* Amount to increment compare reg each time */ +static unsigned long r4k_cur; /* What counter should be at next timer irq */ +extern rwlock_t xtime_lock; + + +static unsigned int timer_tick_count=0; + +static inline void ack_r4ktimer(unsigned long newval) +{ + write_32bit_cp0_register(CP0_COMPARE, newval); +} + +static int set_rtc_mmss(unsigned long nowtime) +{ + /* EV96100 does not have a real time clock */ + int retval = 0; + + return retval; +} + +/* + * There are a lot of conceptually broken versions of the MIPS timer interrupt + * handler floating around. This one is rather different, but the algorithm + * is probably more robust. + */ +static unsigned long alive; +void mips_timer_interrupt(struct pt_regs *regs) +{ + unsigned long status; + unsigned long ret_addr; + int irq = 7; /* FIX ME */ + + if (r4k_offset == 0) { + goto null; + } + + do { + kstat.irqs[0][irq]++; + do_timer(regs); + r4k_cur += r4k_offset; + ack_r4ktimer(r4k_cur); + + } while (((unsigned long)read_32bit_cp0_register(CP0_COUNT) + - r4k_cur) < 0x7fffffff); + return; + +null: + ack_r4ktimer(0); +} + +/* + * Figure out the r4k offset, the amount to increment the compare + * register for each time tick. + * Use the RTC to calculate offset. + */ +static unsigned long __init cal_r4koff(void) +{ + unsigned long count; + count = 300000000/2; + return (count / HZ); +} + +static unsigned long __init get_mips_time(void) +{ + unsigned int year, mon, day, hour, min, sec; + unsigned char save_control; + + year = 2000; + mon = 10; + day = 31; + hour = 0; + min = 0; + sec = 0; + return mktime(year, mon, day, hour, min, sec); +} + + +/* + * called from start_kernel() + */ +void __init time_init(void) +{ + + unsigned int est_freq, flags; + + r4k_offset = cal_r4koff(); + + est_freq = 2*r4k_offset*HZ; + est_freq += 5000; /* round */ + est_freq -= est_freq%10000; + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); + + write_32bit_cp0_register(CP0_COMPARE, r4k_cur); + + /* FIX ME */ + set_cp0_status(ST0_IM, IE_IRQ5); +} + +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) + +/* Cycle counter value at the previous timer interrupt.. */ + +static unsigned int timerhi = 0, timerlo = 0; + +/* + * FIXME: Does playing with the RP bit in c0_status interfere with this code? + */ +static unsigned long do_fast_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + + /* Last jiffy when do_fast_gettimeoffset() was called. */ + static unsigned long last_jiffies=0; + unsigned long quotient; + + /* + * Cached "1/(clocks per usec)*2^32" value. + * It has to be recalculated once each jiffy. + */ + static unsigned long cached_quotient=0; + + tmp = jiffies; + + quotient = cached_quotient; + + if (tmp && last_jiffies != tmp) { + last_jiffies = tmp; + __asm__(".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "lwu\t%0,%2\n\t" + "dsll32\t$1,%1,0\n\t" + "or\t$1,$1,%0\n\t" + "ddivu\t$0,$1,%3\n\t" + "mflo\t$1\n\t" + "dsll32\t%0,%4,0\n\t" + "nop\n\t" + "ddivu\t$0,%0,$1\n\t" + "mflo\t%0\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=&r" (quotient) + :"r" (timerhi), + "m" (timerlo), + "r" (tmp), + "r" (USECS_PER_JIFFY) + :"$1"); + cached_quotient = quotient; + } + + /* Get last timer tick in absolute kernel time */ + count = read_32bit_cp0_register(CP0_COUNT); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + +void do_gettimeofday(struct timeval *tv) +{ + unsigned int flags; + + read_lock_irqsave (&xtime_lock, flags); + *tv = xtime; + tv->tv_usec += do_fast_gettimeoffset(); + + /* + * xtime is atomically updated in timer_bh. jiffies - wall_jiffies + * is nonzero if the timer bottom half hasnt executed yet. + */ + if (jiffies - wall_jiffies) + tv->tv_usec += USECS_PER_JIFFY; + + read_unlock_irqrestore (&xtime_lock, flags); + + if (tv->tv_usec >= 1000000) { + tv->tv_usec -= 1000000; + tv->tv_sec++; + } +} + +void do_settimeofday(struct timeval *tv) +{ + write_lock_irq (&xtime_lock); + + /* This is revolting. We need to set the xtime.tv_usec correctly. + * However, the value in this location is is value at the last tick. + * Discover what correction gettimeofday would have done, and then + * undo it! + */ + tv->tv_usec -= do_fast_gettimeoffset(); + + if (tv->tv_usec < 0) { + tv->tv_usec += 1000000; + tv->tv_sec--; + } + + xtime = *tv; + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; + + write_unlock_irq (&xtime_lock); +} diff --git a/arch/mips/galileo-boards/ev96100/uart.S b/arch/mips/galileo-boards/ev96100/uart.S new file mode 100644 index 000000000..549bbb68d --- /dev/null +++ b/arch/mips/galileo-boards/ev96100/uart.S @@ -0,0 +1,92 @@ + +/* + * Low level serial I/O routines. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_BASE 0xbd000020 +#define SERB_DLABLO 0 +#define SERB_DLABHI 1 +#define SERB_FIFO 2 +#define SERB_DATA 0 +#define SERB_LCR 3 +#define SERB_MCR 4 +#define SERB_CMD 5 + +#define SERA_DLABLO 0x08 +#define SERA_DLABHI 0x09 +#define SERA_DATA 0x08 +#define SERA_LCR 0x0B +#define SERA_MCR 0x0C +#define SERA_CMD 0x0D + +#define TX_BUSY 0x20 + +/* + * To calculate divisor for different baud rates: + * divisor = 3686400/(baud rate x 16), where 3686400 is our + * 3.6864MHz clock input. + */ + +/* + * routine to initialize the serial DUART. Channel A only + */ + .set noreorder + .global init_serial + .ent init_serial +init_serial: + li a0,SERIAL_BASE + +#if 0 + # init channel A + li t0,0x0083 + sb t0,SERA_LCR(a0) # set DLAB + +# li t0,24 # 9600 baud + li t0,2 # 115200 baud + sb t0,SERA_DLABLO(a0) # set divisor + + li t0,0 + sb t0,SERA_DLABHI(a0) + + li t0,0x0003 # 8 data bits + sb t0,SERA_LCR(a0) +#endif + +#if 1 + # init channel B + li t0,0x0083 + sb t0,SERB_LCR(a0) # set DLAB + + li t0,24 + sb t0,SERB_DLABLO(a0) # set divisor for 115200 baud + + li t0,0 + sb t0,SERB_DLABHI(a0) + + li t0,0x0003 # 8 data bits + sb t0,SERB_LCR(a0) + + li t0,0 # no fifo + sb t0,SERB_FIFO(a0) +#endif + + li a0, 0xB4000000 + li t0, 0x002fffff + sw t0, 0x464(a0) + + + jr ra + nop + + .size init_serial, . - init_serial; + .end init_serial + + .set reorder diff --git a/arch/mips/galileo-boards/generic/Makefile b/arch/mips/galileo-boards/generic/Makefile new file mode 100644 index 000000000..0fc5d8b5b --- /dev/null +++ b/arch/mips/galileo-boards/generic/Makefile @@ -0,0 +1,41 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# ######################################################################## +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# ####################################################################### +# +# Makefile for the MIPS boards generic routines under Linux. +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# +# Note 2! The CFLAGS definitions are now in the main makefile... + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +all: galboards.o + +O_TARGET:= galboards.o + +O_OBJS:= pci.o reset.o init.o cmdline.o + +include $(TOPDIR)/Rules.make diff --git a/arch/mips/galileo-boards/generic/cmdline.c b/arch/mips/galileo-boards/generic/cmdline.c new file mode 100644 index 000000000..3574e976c --- /dev/null +++ b/arch/mips/galileo-boards/generic/cmdline.c @@ -0,0 +1,61 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + * + */ +#include +#include +#include + +#include + +/* #define DEBUG_CMDLINE /**/ + +extern int prom_argc; +extern char **prom_argv; + +char arcs_cmdline[CL_SIZE]; + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while(actr < prom_argc) { + strcpy(cp, prom_argv[actr]); + cp += strlen(prom_argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ + --cp; + *cp = '\0'; + +} diff --git a/arch/mips/galileo-boards/generic/init.c b/arch/mips/galileo-boards/generic/init.c new file mode 100644 index 000000000..b488cb349 --- /dev/null +++ b/arch/mips/galileo-boards/generic/init.c @@ -0,0 +1,176 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo PROM library initialisation code. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/generic.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + + +extern char _end; + +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) +/* Environment variable */ + +typedef struct { + char *name; + char *val; +} t_env_var; + +int prom_argc; +char **prom_argv, **prom_envp; + +int init_debug = 0; + +char *prom_getenv(char *envname) +{ + /* + * Return a pointer to the given environment variable. + */ + + t_env_var *env = (t_env_var *) prom_envp; + int i; + + i = strlen(envname); + + while (env->name) { + if (strncmp(envname, env->name, i) == 0) { + return (env->val); + } + env++; + } + return (NULL); +} + +static inline unsigned char str2hexnum(unsigned char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + +int get_ethernet_addr(char *ethernet_addr) +{ + char *ethaddr_str; + + ethaddr_str = prom_getenv("ethaddr"); + if (!ethaddr_str) { + printk("ethaddr not set in boot prom\n"); + return -1; + } + str2eaddr(ethernet_addr, ethaddr_str); + + if (init_debug > 1) { + int i; + printk("get_ethernet_addr: "); + for (i = 0; i < 5; i++) + printk("%02x:", + (unsigned char) *(ethernet_addr + i)); + printk("%02x\n", *(ethernet_addr + i)); + } + + return 0; +} + + +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) +{ + unsigned long mem_size, free_start, free_end, start_pfn, + bootmap_size; + volatile unsigned char *uart; + char ppbuf[8]; + + prom_argc = argc; + prom_argv = argv; + prom_envp = envp; + + //init_serial(); + + mips_machgroup = MACH_GROUP_GALILEO; +#if 0 + prom_ops = &ev96100_prom_ops; + prom_ops->printf = prom_vec[5]; +#endif + puts("Linux running"); + puts(""); + + prom_init_cmdline(); + + //prom_meminit(); + + + /* 64 MB non-upgradable */ + mem_size = 64 << 20; + + free_start = PHYSADDR(PFN_ALIGN(&_end)); + free_end = mem_size; + start_pfn = PFN_UP((unsigned long) &_end); + + /* Register all the contiguous memory with the bootmem allocator + and free it. Be careful about the bootmem freemap. */ + bootmap_size = init_bootmem(start_pfn, mem_size >> PAGE_SHIFT); + + /* Free the entire available memory after the _end symbol. */ + free_start += bootmap_size; + free_bootmem(free_start, free_end - free_start); + + return 0; +} diff --git a/arch/mips/galileo-boards/generic/pci.c b/arch/mips/galileo-boards/generic/pci.c new file mode 100644 index 000000000..c49e86963 --- /dev/null +++ b/arch/mips/galileo-boards/generic/pci.c @@ -0,0 +1,340 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 board specific pci support. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/pci.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +static int +mips_pcibios_config_access(unsigned char access_type, struct pci_dev *dev, + unsigned char where, u32 *data) +{ + unsigned char bus = dev->bus->number; + unsigned char dev_fn = dev->devfn; + u32 intr; + + + if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0))) { + return -1; /* Because of a bug in the galileo (for slot 31). */ + } + + /* Clear cause register bits */ + GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT)); + + /* Setup address */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, + (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) | + (dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | + ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | + GT_PCI0_CFGADDR_CONFIGEN_BIT); + + + if (access_type == PCI_ACCESS_WRITE) { + if (dev_fn != 0) { + *data = le32_to_cpu(*data); + } + GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); + } + else { + GT_READ(GT_PCI0_CFGDATA_OFS, *data); + if (dev_fn != 0) { + *data = le32_to_cpu(*data); + } + } + + /* Check for master or target abort */ + GT_READ(GT_INTRCAUSE_OFS, intr); + + if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) + { + /* Error occured */ + + /* Clear bits */ + GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | + GT_INTRCAUSE_TARABORT0_BIT) ); + + return -1; + } + return 0; +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int +mips_pcibios_read_config_byte (struct pci_dev *dev, int where, u8 *val) +{ + u32 data = 0; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = (data >> ((where & 3) << 3)) & 0xff; +#if 0 + printk("cfg read byte: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); +#endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int +mips_pcibios_read_config_word (struct pci_dev *dev, int where, u16 *val) +{ + u32 data = 0; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = (data >> ((where & 3) << 3)) & 0xffff; +#if 0 + printk("cfg read word: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); +#endif + + return PCIBIOS_SUCCESSFUL; +} + +static int +mips_pcibios_read_config_dword (struct pci_dev *dev, int where, u32 *val) +{ + u32 data = 0; + + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + *val = data; +#if 0 + printk("cfg read dword: bus %d dev_fn %x where %x: val %x\n", + dev->bus->number, dev->devfn, where, *val); +#endif + + return PCIBIOS_SUCCESSFUL; +} + + +static int +mips_pcibios_write_config_byte (struct pci_dev *dev, int where, u8 val) +{ + u32 data = 0; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +static int +mips_pcibios_write_config_word (struct pci_dev *dev, int where, u16 val) +{ + u32 data = 0; + + if (where & 1) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data)) + return -1; + + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + + if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data)) + return -1; + + + return PCIBIOS_SUCCESSFUL; +} + +static int +mips_pcibios_write_config_dword(struct pci_dev *dev, int where, u32 val) +{ + if (where & 3) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &val)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops mips_pci_ops = { + mips_pcibios_read_config_byte, + mips_pcibios_read_config_word, + mips_pcibios_read_config_dword, + mips_pcibios_write_config_byte, + mips_pcibios_write_config_word, + mips_pcibios_write_config_dword +}; + +void __init pcibios_init(void) +{ + + printk("PCI: Probing PCI hardware on host bus 0.\n"); + pci_scan_bus(0, &mips_pci_ops, NULL); + + /* + * Due to a bug in the Galileo system controller, we need to setup + * the PCI BAR for the Galileo internal registers. + * This should be done in the bios/bootprom and will be fixed in + * a later revision of YAMON (the MIPS boards boot prom). + */ + GT_WRITE(GT_PCI0_CFGADDR_OFS, cpu_to_le32( + (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ + (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */ + (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */ + ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */ + GT_PCI0_CFGADDR_CONFIGEN_BIT )); + + /* Perform the write */ + GT_WRITE( GT_PCI0_CFGDATA_OFS, cpu_to_le32(PHYSADDR(MIPS_GT_BASE))); + +} + +int __init +pcibios_enable_device(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + int idx; + struct resource *r; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for(idx=0; idx<6; idx++) { + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (dev->resource[PCI_ROM_RESOURCE].start) + cmd |= PCI_COMMAND_MEMORY; + if (cmd != old_cmd) { + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); + } + return 0; +} + +void __init +pcibios_align_resource(void *data, struct resource *res, unsigned long size) +{ + printk("pcibios_align_resource\n"); +#if 0 /* from ppc */ + struct pci_dev *dev = data; + + if (res->flags & IORESOURCE_IO) { + unsigned long start = res->start; + + if (size > 0x100) { + printk(KERN_ERR "PCI: I/O Region %s/%d too large" + " (%ld bytes)\n", dev->slot_name, + dev->resource - res, size); + } + + if (start & 0x300) { + start = (start + 0x3ff) & ~0x3ff; + res->start = start; + } + } +#endif +} + +char * __init +pcibios_setup(char *str) +{ + /* Nothing to do for now. */ + + return str; +} + +struct pci_fixup pcibios_fixups[] = { + { 0 } +}; + +void __init +pcibios_update_resource(struct pci_dev *dev, struct resource *root, + struct resource *res, int resource) +{ + unsigned long where, size; + u32 reg; + + where = PCI_BASE_ADDRESS_0 + (resource * 4); + size = res->end - res->start; + pci_read_config_dword(dev, where, ®); + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size); + pci_write_config_dword(dev, where, reg); +} + +/* + * Called after each bus is probed, but before its children + * are examined. + */ +void __init pcibios_fixup_bus(struct pci_bus *b) +{ + pci_read_bridge_bases(b); +} + +#endif /* CONFIG_PCI */ diff --git a/arch/mips/galileo-boards/generic/printf.c b/arch/mips/galileo-boards/generic/printf.c new file mode 100644 index 000000000..f731cc257 --- /dev/null +++ b/arch/mips/galileo-boards/generic/printf.c @@ -0,0 +1,53 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Putting things on the screen/serial line using YAMONs facilities. + * + */ +#include +#include +#include +#include +#include + +static char ppbuf[1024]; + +void (*prom_print_str)(unsigned int out, char *s, int len); + +void __init setup_prom_printf(void) +{ + prom_print_str = (void *)*(unsigned int *)YAMON_PROM_PRINT_ADDR; +} + +void __init prom_printf(char *fmt, ...) +{ + va_list args; + int len; + + va_start(args, fmt); + vsprintf(ppbuf, fmt, args); + len = strlen(ppbuf); + + prom_print_str(0, ppbuf, len); + + va_end(args); + return; +} diff --git a/arch/mips/galileo-boards/generic/prom-no.c b/arch/mips/galileo-boards/generic/prom-no.c new file mode 100644 index 000000000..826acad15 --- /dev/null +++ b/arch/mips/galileo-boards/generic/prom-no.c @@ -0,0 +1,50 @@ + +/* + * prom-no.c + * + * BRIEF MODULE DESCRIPTION + * Stubs for prom routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or support@mvista.com + * debbie_chu@mvista.com + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include + +static int no_printf (const char *fmt, ...) +{ + /* nop */ +} + +static void no_flushcache() +{ + /* nop */ +} + +struct prom_ops no_prom_ops = { + &no_printf, + &no_flushcache +}; diff --git a/arch/mips/galileo-boards/generic/reset.c b/arch/mips/galileo-boards/generic/reset.c new file mode 100644 index 000000000..fc080c080 --- /dev/null +++ b/arch/mips/galileo-boards/generic/reset.c @@ -0,0 +1,60 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Galileo EV96100 reset routines. + * + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or support@mvista.com + * + * This file was derived from Carsten Langgaard's + * arch/mips/mips-boards/generic/reset.c + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include + +#include +#include + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ + printk("mips_machine_restart: not implemented\n"); + while (1); +} + +static void mips_machine_halt(void) +{ + printk("mips_machine_halt: not implemented\n"); + while (1); +} + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; +} diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index ea332cb10..2125c2f9c 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -37,10 +37,14 @@ ifndef CONFIG_DECSTATION ifndef CONFIG_ORION ifndef CONFIG_MIPS_ATLAS ifndef CONFIG_MIPS_MALTA - O_OBJS += time.o - ifndef CONFIG_SGI_IP22 - OX_OBJS += irq.o - endif + ifndef CONFIG_MIPS_EV96100 + O_OBJS += time.o + ifndef CONFIG_SGI_IP22 + ifndef CONFIG_MIPS_EV96100 + OX_OBJS += irq.o + endif + endif + endif endif endif endif diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index c067218b6..4e8c64fb6 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -265,6 +265,7 @@ void __init setup_arch(char **cmdline_p) void sgi_setup(void); void ddb_setup(void); void orion_setup(void); + void ev96100_setup(void); /* Save defaults for configuration-dependent routines. */ irq_setup = default_irq_setup; @@ -330,6 +331,11 @@ void __init setup_arch(char **cmdline_p) case MACH_GROUP_ORION: orion_setup(); break; +#endif +#ifdef CONFIG_MIPS_EV96100 + case MACH_GROUP_GALILEO: + ev96100_setup(); + break; #endif default: panic("Unsupported architecture"); diff --git a/arch/mips/kernel/sysmips.c b/arch/mips/kernel/sysmips.c index 7d34f2d8c..baf2f81df 100644 --- a/arch/mips/kernel/sysmips.c +++ b/arch/mips/kernel/sysmips.c @@ -49,7 +49,7 @@ sys_sysmips(int cmd, int arg1, int arg2, int arg3) { int *p; char *name; - int flags, tmp, len, retval, errno; + int tmp, len, retval, errno; switch(cmd) { case SETNAME: { @@ -72,8 +72,6 @@ sys_sysmips(int cmd, int arg1, int arg2, int arg3) } case MIPS_ATOMIC_SET: { - /* This is broken in case of page faults and SMP ... - Risc/OS faults after maximum 20 tries with EAGAIN. */ unsigned int tmp; p = (int *) arg1; @@ -81,16 +79,42 @@ sys_sysmips(int cmd, int arg1, int arg2, int arg3) if (errno) return errno; errno = 0; - save_and_cli(flags); - errno |= __get_user(tmp, p); - errno |= __put_user(arg2, p); - restore_flags(flags); + + __asm__(".set\tpush\t\t\t# sysmips(MIPS_ATOMIC, ...)\n\t" + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "1:\tll\t%0, %4\n\t" + "2:\tmove\t$1, %3\n\t" + "3:\tsc\t$1, %1\n\t" + "beqzl\t$1, 2b\n\t" + "4:\t ll\t%0, %4\n\t" + ".set\tpop\n\t" + ".section\t.fixup,\"ax\"\n" + "5:\tli\t%2, 1\t\t\t# error\n\t" + ".previous\n\t" + ".section\t__ex_table,\"a\"\n\t" + ".dword\t1b, 5b\n\t" + ".dword\t3b, 5b\n\t" + ".dword\t4b, 5b\n\t" + ".previous\n\t" + : "=&r" (tmp), "=o" (* (u32 *) p), "=r" (errno) + : "r" (arg2), "o" (* (u32 *) p), "2" (errno) + : "$1"); if (errno) - return tmp; + return -EFAULT; - return tmp; /* This is broken ... */ - } + /* We're skipping error handling etc. */ + if (current->ptrace & PT_TRACESYS) + syscall_trace(); + + __asm__ __volatile__( + "move\t$29, %0\n\t" + "j\tret_from_sys_call" + : /* No outputs */ + : "r" (&cmd)); + /* Unreached */ + } case MIPS_FIXADE: tmp = current->thread.mflags & ~3; diff --git a/drivers/net/Config.in b/drivers/net/Config.in index df0caa6fc..4957883f9 100644 --- a/drivers/net/Config.in +++ b/drivers/net/Config.in @@ -49,6 +49,9 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then if [ "$CONFIG_MIPS_JAZZ" = "y" ]; then tristate ' MIPS JAZZ onboard SONIC Ethernet support' CONFIG_MIPS_JAZZ_SONIC fi + if [ "$CONFIG_MIPS_GT96100" = "y" ]; then + bool ' MIPS GT96100 Ethernet support' CONFIG_MIPS_GT96100ETH + fi if [ "$CONFIG_SGI_IP27" = "y" ]; then bool ' SGI IOC3 Ethernet' CONFIG_SGI_IOC3_ETH fi diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 61c14198b..145747078 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -263,6 +263,7 @@ obj-$(CONFIG_HPLANCE) += hplance.o 7990.o obj-$(CONFIG_MVME147_NET) += mvme147.o 7990.o obj-$(CONFIG_EQUALIZER) += eql.o obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o +obj-$(CONFIG_MIPS_GT96100ETH) += gt96100eth.o obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o obj-$(CONFIG_BAGETLANCE) += bagetlance.o obj-$(CONFIG_DECLANCE) += declance.o diff --git a/drivers/net/gt96100eth.c b/drivers/net/gt96100eth.c new file mode 100644 index 000000000..6eecd78f1 --- /dev/null +++ b/drivers/net/gt96100eth.c @@ -0,0 +1,1252 @@ +/* + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or support@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Ethernet driver for the MIPS GT96100 Advanced Communication Controller. + * + */ + +#ifndef __mips__ +#error This driver only works with MIPS architectures! +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gt96100eth.h" + +#ifdef GT96100_DEBUG +static int gt96100_debug = GT96100_DEBUG; +#else +static int gt96100_debug = 3; +#endif + +// prototypes +static void *dmaalloc(size_t size, dma_addr_t * dma_handle); +static void dmafree(size_t size, void *vaddr); +static int gt96100_add_hash_entry(struct net_device *dev, + unsigned char *addr); +static void read_mib_counters(struct gt96100_private *gp); +static int read_MII(struct net_device *dev, u32 reg); +static int write_MII(struct net_device *dev, u32 reg, u16 data); +static void dump_MII(struct net_device *dev); +static void update_stats(struct gt96100_private *gp); +static void abort(struct net_device *dev, u32 abort_bits); +static void hard_stop(struct net_device *dev); +static void enable_ether_irq(struct net_device *dev); +static void disable_ether_irq(struct net_device *dev); +static int __init gt96100_probe1(struct net_device *dev, long ioaddr, + int irq, int port_num); +static int gt96100_init(struct net_device *dev); +static int gt96100_open(struct net_device *dev); +static int gt96100_close(struct net_device *dev); +static int gt96100_tx(struct sk_buff *skb, struct net_device *dev); +static int gt96100_rx(struct net_device *dev, u32 status); +static void gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs); +static void gt96100_tx_timeout(struct net_device *dev); +static void gt96100_set_rx_mode(struct net_device *dev); +static struct net_device_stats *gt96100_get_stats(struct net_device *dev); + +static char version[] __devinitdata = + "gt96100eth.c:0.1 stevel@mvista.com\n"; + +// FIX! Need real Ethernet addresses +static unsigned char gt96100_station_addr[2][6] __devinitdata = + { {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}, +{0x01, 0x02, 0x03, 0x04, 0x05, 0x07} +}; + +#define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0)) + +#define RUN_AT(x) (jiffies + (x)) + +// For reading/writing 32-bit words from/to DMA memory +#define cpu_to_dma32 cpu_to_be32 +#define dma32_to_cpu be32_to_cpu + +/* + * Base address and interupt of the GT96100 ethernet controllers + */ +static struct { + unsigned int port; + int irq; +} gt96100_iflist[NUM_INTERFACES] = { + { + GT96100_ETH0_BASE, GT96100_ETHER0_IRQ}, { + GT96100_ETH1_BASE, GT96100_ETHER1_IRQ} +}; + +/* + DMA memory allocation, derived from pci_alloc_consistent. +*/ +static void *dmaalloc(size_t size, dma_addr_t * dma_handle) +{ + void *ret; + + ret = + (void *) __get_free_pages(GFP_ATOMIC | GFP_DMA, + get_order(size)); + + if (ret != NULL) { + dma_cache_inv((unsigned long) ret, size); + if (dma_handle != NULL) + *dma_handle = virt_to_phys(ret); + + /* bump virtual address up to non-cached area */ + ret = KSEG1ADDR(ret); + } + + return ret; +} + +static void dmafree(size_t size, void *vaddr) +{ + vaddr = KSEG0ADDR(vaddr); + free_pages((unsigned long) vaddr, get_order(size)); +} + + +static int read_MII(struct net_device *dev, u32 reg) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + int timedout = 20; + u32 smir = smirOpCode | (gp->phy_addr << smirPhyAdBit) | + (reg << smirRegAdBit); + + // wait for last operation to complete + while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { + // snooze for 1 msec and check again +#if 0 + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(10 * HZ / 10000); +#else + mdelay(1); +#endif + + if (--timedout == 0) { + printk(KERN_ERR "%s: read_MII busy timeout!!\n", + dev->name); + return -1; + } + } + + GT96100_WRITE(GT96100_ETH_SMI_REG, smir); + + timedout = 20; + // wait for read to complete + while (!(smir = GT96100_READ(GT96100_ETH_SMI_REG) & smirReadValid)) { + // snooze for 1 msec and check again +#if 0 + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(10 * HZ / 10000); +#else + mdelay(1); +#endif + + if (--timedout == 0) { + printk(KERN_ERR "%s: read_MII timeout!!\n", + dev->name); + return -1; + } + } + + return (int) (smir & smirDataMask); +} + +static int write_MII(struct net_device *dev, u32 reg, u16 data) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + int timedout = 20; + u32 smir = + (gp->phy_addr << smirPhyAdBit) | (reg << smirRegAdBit) | data; + + // wait for last operation to complete + while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) { + // snooze for 1 msec and check again +#if 0 + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(10 * HZ / 10000); +#else + mdelay(1); +#endif + + if (--timedout == 0) { + printk(KERN_ERR "%s: write_MII busy timeout!!\n", + dev->name); + return -1; + } + } + + GT96100_WRITE(GT96100_ETH_SMI_REG, smir); + return 0; +} + + +static void dump_MII(struct net_device *dev) +{ + int i, val; + + for (i = 0; i < 7; i++) { + if ((val = read_MII(dev, i)) >= 0) + printk("%s: MII Reg %d=%x\n", dev->name, i, val); + } + for (i = 16; i < 21; i++) { + if ((val = read_MII(dev, i)) >= 0) + printk("%s: MII Reg %d=%x\n", dev->name, i, val); + } +} + + +static int +gt96100_add_hash_entry(struct net_device *dev, unsigned char *addr) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + u16 hashResult, stmp; + unsigned char ctmp, hash_ea[6]; + u32 tblEntry, *tblEntryAddr; + int i; + + for (i = 0; i < 6; i++) { + // nibble swap + ctmp = nibswap(addr[i]); + // invert every nibble + hash_ea[i] = ((ctmp & 1) << 3) | ((ctmp & 8) >> 3) | + ((ctmp & 2) << 1) | ((ctmp & 4) >> 1); + hash_ea[i] |= ((ctmp & 0x10) << 3) | ((ctmp & 0x80) >> 3) | + ((ctmp & 0x20) << 1) | ((ctmp & 0x40) >> 1); + } + + if (gp->hash_mode == 0) { + hashResult = ((u16) hash_ea[0] & 0xfc) << 7; + stmp = + ((u16) hash_ea[0] & 0x03) | (((u16) hash_ea[1] & 0x7f) + << 2); + stmp ^= + (((u16) hash_ea[1] >> 7) & 0x01) | ((u16) hash_ea[2] << + 1); + stmp ^= (u16) hash_ea[3] | (((u16) hash_ea[4] & 1) << 8); + hashResult |= stmp; + } else { + return -1; // don't support hash mode 1 + } + + tblEntryAddr = + (u32 *) (&gp->hash_table[((u32) hashResult & 0x7ff) << 3]); + + for (i = 0; i < HASH_HOP_NUMBER; i++) { + if ((*tblEntryAddr & hteValid) + && !(*tblEntryAddr & hteSkip)) { + // This entry is already occupied, go to next entry + tblEntryAddr += 2; + } else { + memset(tblEntryAddr, 0, 8); + tblEntry = hteValid | hteRD; + tblEntry |= (u32) addr[5] << 3; + tblEntry |= (u32) addr[4] << 11; + tblEntry |= (u32) addr[3] << 19; + tblEntry |= ((u32) addr[2] & 0x1f) << 27; + *(tblEntryAddr + 1) = cpu_to_dma32(tblEntry); + tblEntry = ((u32) addr[2] >> 5) & 0x07; + tblEntry |= (u32) addr[1] << 3; + tblEntry |= (u32) addr[0] << 11; + *tblEntryAddr = cpu_to_dma32(tblEntry); + break; + } + } + + if (i >= HASH_HOP_NUMBER) { + printk(KERN_ERR "%s: gt96100_add_hash_entry expired!\n", + dev->name); + return -1; // Couldn't find an unused entry + } + + return 0; +} + + +static void read_mib_counters(struct gt96100_private *gp) +{ + u32 *mib_regs = (u32 *) & gp->mib; + int i; + + for (i = 0; i < sizeof(mib_counters_t) / sizeof(u32); i++) + mib_regs[i] = + GT96100ETH_READ(gp, + GT96100_ETH_MIB_COUNT_BASE + + i * sizeof(u32)); +} + + +static void update_stats(struct gt96100_private *gp) +{ + mib_counters_t *mib = &gp->mib; + struct net_device_stats *stats = &gp->stats; + + read_mib_counters(gp); + + stats->rx_packets = mib->totalFramesReceived; + stats->tx_packets = mib->framesSent; + stats->rx_bytes = mib->totalByteReceived; + stats->tx_bytes = mib->byteSent; + stats->rx_errors = mib->totalFramesReceived - mib->framesReceived; + //the tx error counters are incremented by the ISR + //rx_dropped incremented by gt96100_rx + //tx_dropped incremented by gt96100_tx + stats->multicast = mib->multicastFramesReceived; + // Tx collisions incremented by ISR, so add in MIB Rx collisions + stats->collisions += mib->collision + mib->lateCollision; + stats->rx_length_errors = mib->oversizeFrames + mib->fragments; + // The RxError condition means the Rx DMA encountered a + // CPU owned descriptor, which, if things are working as + // they should, means the Rx ring has overflowed. + stats->rx_over_errors = mib->macRxError; + stats->rx_crc_errors = mib->cRCError; +} + +static void abort(struct net_device *dev, u32 abort_bits) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + int timedout = 100; // wait up to 100 msec for hard stop to complete + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: abort\n", dev->name); + + // Return if neither Rx or Tx abort bits are set + if (!(abort_bits & (sdcmrAR | sdcmrAT))) + return; + + // make sure only the Rx/Tx abort bits are set + abort_bits &= (sdcmrAR | sdcmrAT); + + spin_lock(&gp->lock); + + // abort any Rx/Tx DMA immediately + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits); + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: abort: SDMA comm = %x\n", + dev->name, GT96100ETH_READ(gp, + GT96100_ETH_SDMA_COMM)); + + // wait for abort to complete + while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) { + // snooze for 20 msec and check again +#if 0 + current->state = TASK_INTERRUPTIBLE; + schedule_timeout(10 * HZ / 10000); +#else + mdelay(1); +#endif + + if (--timedout == 0) { + printk(KERN_ERR "%s: abort timeout!!\n", + dev->name); + break; + } + } + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: abort: timedout=%d\n", dev->name, + timedout); + + spin_unlock(&gp->lock); +} + + +static void hard_stop(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: hard stop\n", dev->name); + + disable_ether_irq(dev); + + abort(dev, sdcmrAR | sdcmrAT); + + // disable port + GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0); +} + + +static void enable_ether_irq(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + u32 intMask; + + // unmask interrupts + GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, + icrRxBuffer | icrTxBufferLow | icrTxEndLow | + icrRxError | icrTxErrorLow | icrRxOVR | + icrTxUdr | icrRxBufferQ0 | icrRxErrorQ0 | + icrMIIPhySTC); + + // now route ethernet interrupts to GT Int0 (eth0 and eth1 will be + // sharing it). + // FIX! The kernel's irq code should do this + intMask = GT96100_READ(GT96100_INT0_HIGH_MASK); + intMask |= 1 << gp->port_num; + GT96100_WRITE(GT96100_INT0_HIGH_MASK, intMask); +} + +static void disable_ether_irq(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + u32 intMask; + + // FIX! The kernel's irq code should do this + intMask = GT96100_READ(GT96100_INT0_HIGH_MASK); + intMask &= ~(1 << gp->port_num); + GT96100_WRITE(GT96100_INT0_HIGH_MASK, intMask); + + GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0); +} + + +/* + * Probe for a GT96100 ethernet controller. + */ +int __init gt96100_probe(struct net_device *dev) +{ + unsigned int base_addr = dev ? dev->base_addr : 0; + int i; + +#ifndef CONFIG_MIPS_GT96100ETH + return -ENODEV; +#endif + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: gt96100_probe\n", dev->name); + + if (base_addr >= KSEG0) /* Check a single specified location. */ + return gt96100_probe1(dev, base_addr, dev->irq, 0); + else if (base_addr != 0) /* Don't probe at all. */ + return -ENXIO; + +// for (i = 0; i= 0; i--) { + int base_addr = gt96100_iflist[i].port; +#if 0 + if (check_region(base_addr, GT96100_ETH_IO_SIZE)) { + printk(KERN_ERR + "%s: gt96100_probe: ioaddr 0x%lx taken?\n", + dev->name, base_addr); + continue; + } +#endif + if (gt96100_probe1 + (dev, base_addr, gt96100_iflist[i].irq, i) == 0) + return 0; + } + return -ENODEV; +} + + + +static int __init +gt96100_probe1(struct net_device *dev, long ioaddr, int irq, int port_num) +{ + static unsigned version_printed = 0; + struct gt96100_private *gp = NULL; + int i, retval; + u32 cpuConfig; + + // FIX! probe for GT96100 by reading a suitable register + + if (gt96100_debug > 2) + printk(KERN_INFO "gt96100_probe1: ioaddr 0x%lx, irq %d\n", + ioaddr, irq); + + request_region(ioaddr, GT96100_ETH_IO_SIZE, "GT96100ETH"); + + cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG); + if (cpuConfig & (1 << 12)) { + printk(KERN_ERR + "gt96100_probe1: must be in Big Endian mode!\n"); + retval = -ENODEV; + goto free_region; + } + + if (gt96100_debug > 2) + printk(KERN_INFO + "gt96100_probe1: chip in Big Endian mode - cool\n"); + + /* Allocate a new 'dev' if needed. */ + if (dev == NULL) + dev = init_etherdev(0, sizeof(struct gt96100_private)); + + if (gt96100_debug && version_printed++ == 0) + printk(version); + + if (irq < 0) { + printk(KERN_ERR + "gt96100_probe1: irq unknown - probing not supported\n"); + retval = -ENODEV; + goto free_region; + } + + printk(KERN_INFO "%s: GT-96100 ethernet found at 0x%lx, irq %d\n", + dev->name, ioaddr, irq); + + /* private struct aligned and zeroed by init_etherdev */ + /* Fill in the 'dev' fields. */ + dev->base_addr = ioaddr; + dev->irq = irq; + memcpy(dev->dev_addr, gt96100_station_addr[port_num], + sizeof(dev->dev_addr)); + + printk(KERN_INFO "%s: HW Address ", dev->name); + for (i = 0; i < sizeof(dev->dev_addr); i++) { + printk("%2.2x", dev->dev_addr[i]); + printk(i < 5 ? ":" : "\n"); + } + + /* Initialize our private structure. */ + if (dev->priv == NULL) { + + gp = + (struct gt96100_private *) kmalloc(sizeof(*gp), + GFP_KERNEL); + if (gp == NULL) { + retval = -ENOMEM; + goto free_region; + } + + dev->priv = gp; + } + + gp = dev->priv; + + memset(gp, 0, sizeof(*gp)); // clear it + + gp->port_num = port_num; + gp->io_size = GT96100_ETH_IO_SIZE; + gp->port_offset = port_num * GT96100_ETH_IO_SIZE; + gp->phy_addr = port_num + 1; + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: gt96100_probe1, port %d\n", + dev->name, gp->port_num); + + // Allocate Rx and Tx descriptor rings + if (gp->rx_ring == NULL) { + // All descriptors in ring must be 16-byte aligned + gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE + + + sizeof(gt96100_td_t) * TX_RING_SIZE, + &gp->rx_ring_dma); + if (gp->rx_ring == NULL) { + retval = -ENOMEM; + goto free_region; + } + + gp->tx_ring = + (gt96100_td_t *) (gp->rx_ring + RX_RING_SIZE); + gp->tx_ring_dma = + gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE; + } + + if (gt96100_debug > 2) + printk(KERN_INFO + "%s: gt96100_probe1, rx_ring=%p, tx_ring=%p\n", + dev->name, gp->rx_ring, gp->tx_ring); + + // Allocate Rx Hash Table + if (gp->hash_table == NULL) { + gp->hash_table = (char *) dmaalloc(RX_HASH_TABLE_SIZE, + &gp->hash_table_dma); + if (gp->hash_table == NULL) { + dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE + + sizeof(gt96100_td_t) * TX_RING_SIZE, + gp->rx_ring); + retval = -ENOMEM; + goto free_region; + } + } + + if (gt96100_debug > 2) + printk(KERN_INFO "%s: gt96100_probe1, hash=%p\n", + dev->name, gp->hash_table); + + spin_lock_init(&gp->lock); + + dev->open = gt96100_open; + dev->hard_start_xmit = gt96100_tx; + dev->stop = gt96100_close; + dev->get_stats = gt96100_get_stats; + //dev->do_ioctl = gt96100_ioctl; + dev->set_multicast_list = gt96100_set_rx_mode; + dev->tx_timeout = gt96100_tx_timeout; + dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT; + + /* Fill in the fields of the device structure with ethernet values. */ + ether_setup(dev); + return 0; + + free_region: + release_region(ioaddr, gp->io_size); + unregister_netdev(dev); + if (dev->priv != NULL) + kfree(dev->priv); + kfree(dev); + printk(KERN_ERR "%s: gt96100_probe1 failed. Returns %d\n", + dev->name, retval); + return retval; +} + + +static int gt96100_init(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + unsigned long flags; + u32 phyAD, ciu; + int i; + + if (gt96100_debug > 2) + printk("%s: gt96100_init: dev=%p\n", dev->name, dev); + + // Stop and disable Port + hard_stop(dev); + + spin_lock_irqsave(&gp->lock, flags); + + // First things first, set-up hash table + memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it + gp->hash_mode = 0; + // Add a single entry to hash table - our ethernet address + gt96100_add_hash_entry(dev, dev->dev_addr); + // Set-up DMA ptr to hash table + GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma); + if (gt96100_debug > 2) + printk("%s: gt96100_init: Hash Tbl Ptr=%x\n", dev->name, + GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR)); + + // Setup Tx descriptor ring + for (i = 0; i < TX_RING_SIZE; i++) { + gp->tx_ring[i].cmdstat = 0; // CPU owns + gp->tx_ring[i].byte_cnt = 0; + gp->tx_ring[i].buff_ptr = 0; + gp->tx_ring[i].next = + cpu_to_dma32(gp->tx_ring_dma + + sizeof(gt96100_td_t) * (i + 1)); + } + /* Wrap the ring. */ + gp->tx_ring[i - 1].next = cpu_to_dma32(gp->tx_ring_dma); + + // setup only the lowest priority TxCDP reg + GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, + gp->tx_ring_dma); + GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0); + if (gt96100_debug > 2) + printk("%s: gt96100_init: Curr Tx Desc Ptr0=%x\n", + dev->name, GT96100ETH_READ(gp, + GT96100_ETH_CURR_TX_DESC_PTR0)); + + // Setup Rx descriptor ring + for (i = 0; i < RX_RING_SIZE; i++) { + dma_addr_t rx_buff_dma; + gp->rx_ring[i].next = + cpu_to_dma32(gp->rx_ring_dma + + sizeof(gt96100_rd_t) * (i + 1)); + if (gp->rx_buff[i] == NULL) + gp->rx_buff[i] = + dmaalloc(PKT_BUF_SZ, &rx_buff_dma); + else + rx_buff_dma = virt_to_phys(gp->rx_buff[i]); + if (gp->rx_buff[i] == NULL) + break; + gp->rx_ring[i].buff_ptr = cpu_to_dma32(rx_buff_dma); + gp->rx_ring[i].buff_cnt_sz = + cpu_to_dma32(PKT_BUF_SZ << rdBuffSzBit); + // Give ownership to device, enable interrupt + gp->rx_ring[i].cmdstat = + cpu_to_dma32((u32) (rxOwn | rxEI)); + } + + if (i != RX_RING_SIZE) { + int j; + for (j = 0; j < RX_RING_SIZE; j++) { + if (gp->rx_buff[j]) { + dmafree(PKT_BUF_SZ, gp->rx_buff[j]); + gp->rx_buff[j] = NULL; + } + } + printk(KERN_ERR "%s: Rx ring allocation failed.\n", + dev->name); + spin_unlock_irqrestore(&gp->lock, flags); + return -ENOMEM; + } + + /* Wrap the ring. */ + gp->rx_ring[i - 1].next = cpu_to_dma32(gp->rx_ring_dma); + + // Set our MII PHY device address + phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG); + phyAD &= ~(0x1f << (gp->port_num * 5)); + phyAD |= gp->phy_addr << (gp->port_num * 5); + GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD); + + if (gt96100_debug > 2) + printk("%s: gt96100_init: PhyAD=%x\n", dev->name, + GT96100_READ(GT96100_ETH_PHY_ADDR_REG)); + + // Clear all the RxFDP and RXCDP regs... + for (i = 0; i < 4; i++) { + GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0 + i * 4, + 0); + GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0 + i * 4, + 0); + } + // and setup only the lowest priority RxFDP and RxCDP regs + GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0, + gp->rx_ring_dma); + GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0, + gp->rx_ring_dma); + if (gt96100_debug > 2) + printk("%s: gt96100_init: 1st/Curr Rx Desc Ptr0=%x/%x\n", + dev->name, GT96100ETH_READ(gp, + GT96100_ETH_1ST_RX_DESC_PTR0), + GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0)); + + // init Rx/Tx indeces and pkt counters + gp->rx_next_out = gp->tx_next_in = gp->tx_next_out = 0; + gp->tx_count = 0; + + // setup DMA + + // FIX! this should be done by Kernel setup code + ciu = GT96100_READ(GT96100_CIU_ARBITER_CONFIG); + ciu |= (0x0c << (gp->port_num * 2)); // set Ether DMA req priority to high + // FIX! setting the following bit causes the EV96100 board to hang!!! + //ciu |= (1 << (24+gp->port_num)); // pull Ethernet port out of Reset??? + // FIX! endian mode??? + ciu &= ~(1 << 31); // set desc endianess to Big + GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, ciu); + if (gt96100_debug > 2) + printk("%s: gt96100_init: CIU Config=%x/%x\n", dev->name, + ciu, GT96100_READ(GT96100_CIU_ARBITER_CONFIG)); + + // We want the Rx/Tx DMA to write/read data to/from memory in + // Big Endian mode. Also set DMA Burst Size to 8 64Bit words. + // FIX! endian mode??? + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG, + //sdcrBLMR | sdcrBLMT | + (0xf << sdcrRCBit) | sdcrRIFB | (3 << sdcrBSZBit)); + if (gt96100_debug > 2) + printk("%s: gt96100_init: SDMA Config=%x\n", dev->name, + GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG)); + + // start Rx DMA + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD); + if (gt96100_debug > 2) + printk("%s: gt96100_init: SDMA Comm=%x\n", dev->name, + GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM)); + + // enable interrupts + enable_ether_irq(dev); + + /* + * Disable all Type-of-Service queueing. All Rx packets will be + * treated normally and will be sent to the lowest priority + * queue. + * + * Disable flow-control for now. FIX! support flow control? + */ + // clear all the MIB ctr regs + // Enable reg clear on read. FIX! desc of this bit is inconsistent + // in the GT-96100A datasheet. + GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, + pcxrFCTL | pcxrFCTLen | pcxrFLP); + read_mib_counters(gp); + GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT, + pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrMIBclrMode); + + if (gt96100_debug > 2) + printk("%s: gt96100_init: Port Config Ext=%x\n", dev->name, + GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT)); + + // enable this port (set hash size to 1/2K) + GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS); + if (gt96100_debug > 2) + printk("%s: gt96100_init: Port Config=%x\n", dev->name, + GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG)); + + // we should now be receiving frames + if (gt96100_debug > 2) + dump_MII(dev); + + spin_unlock_irqrestore(&gp->lock, flags); + return 0; +} + + +static int gt96100_open(struct net_device *dev) +{ + int retval; + + MOD_INC_USE_COUNT; + + if (gt96100_debug > 2) + printk("%s: gt96100_open: dev=%p\n", dev->name, dev); + + if ((retval = request_irq(dev->irq, >96100_interrupt, + SA_SHIRQ, dev->name, dev))) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, + dev->irq); + MOD_DEC_USE_COUNT; + return retval; + } + // Initialize and startup the GT-96100 ethernet port + if ((retval = gt96100_init(dev))) { + printk(KERN_ERR "%s: error in gt96100_init\n", dev->name); + free_irq(dev->irq, dev); + MOD_DEC_USE_COUNT; + return retval; + } + + netif_start_queue(dev); + + if (gt96100_debug > 2) + printk("%s: gt96100_open: Initialization done.\n", + dev->name); + + return 0; +} + +static int gt96100_close(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + int i; + + if (gt96100_debug > 2) + printk("%s: gt96100_close: dev=%p\n", dev->name, dev); + + // stop the device + if (netif_device_present(dev)) { + netif_stop_queue(dev); + hard_stop(dev); + } + // free the Rx DMA buffers + for (i = 0; i < RX_RING_SIZE; i++) { + if (gp->rx_buff[i]) { + dmafree(PKT_BUF_SZ, gp->rx_buff[i]); + gp->rx_buff[i] = NULL; + } + } + + free_irq(dev->irq, dev); + + MOD_DEC_USE_COUNT; + return 0; +} + + +static int gt96100_tx(struct sk_buff *skb, struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + unsigned long flags; + int nextIn; + + if (gt96100_debug > 2) + printk("%s: gt96100_tx: skb->len=%d, skb->data=%p\n", + dev->name, skb->len, skb->data); + + spin_lock_irqsave(&gp->lock, flags); + + if (gp->tx_count >= TX_RING_SIZE) { + printk(KERN_WARNING + "%s: Tx Ring full, refusing to send buffer.\n", + dev->name); + gp->stats.tx_dropped++; + spin_unlock_irqrestore(&gp->lock, flags); + return 1; + } + // Prepare the Descriptor at tx_next_in + nextIn = gp->tx_next_in; + + if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) { + printk(KERN_ERR "%s: gt96100_tx: TxOwn bit wrong!!\n", + dev->name); + } + + gp->tx_skbuff[nextIn] = skb; + gp->tx_ring[nextIn].byte_cnt = + cpu_to_dma32(skb->len << tdByteCntBit); + gp->tx_ring[nextIn].buff_ptr = + cpu_to_dma32(virt_to_phys(skb->data)); + // Give ownership to device, set first and last desc, enable interrupt + // Setting of ownership bit must be *last*! + gp->tx_ring[nextIn].cmdstat = + cpu_to_dma32((u32) (txOwn | txEI | txFirst | txLast)); + + // increment tx_next_in with wrap + gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE; + // If count is zero, DMA should be stopped, so restart + if (gp->tx_count == 0) { + if (GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & + psrTxLow) printk(KERN_WARNING + "%s: Tx count zero but Tx queue running!\n", + dev->name); + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, + sdcmrERD | sdcmrTXDL); + } + // increment count and stop queue if full + if (++gp->tx_count == TX_RING_SIZE) + netif_stop_queue(dev); + + dev->trans_start = jiffies; + spin_unlock_irqrestore(&gp->lock, flags); + + return 0; +} + + +static int gt96100_rx(struct net_device *dev, u32 status) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + struct sk_buff *skb; + int pkt_len, nextOut; + gt96100_rd_t *rd; + u32 cmdstat; + + if (gt96100_debug > 2) + printk("%s: gt96100_rx: dev=%p, status = %x\n", + dev->name, dev, status); + + // Continue until we reach the current descriptor pointer + for (nextOut = gp->rx_next_out; + nextOut != + (GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0) - + gp->rx_ring_dma) / sizeof(gt96100_rd_t); + nextOut = (nextOut + 1) % RX_RING_SIZE) { + + rd = &gp->rx_ring[nextOut]; + cmdstat = dma32_to_cpu(rd->cmdstat); + + if (cmdstat & (u32) rxOwn) { + cmdstat &= ~((u32) rxOwn); + rd->cmdstat = cpu_to_dma32(cmdstat); + printk(KERN_ERR + "%s: gt96100_rx: ownership bit wrong!\n", + dev->name); + } + // must be first and last (ie only) buffer of packet + if (!(cmdstat & (u32) rxFirst) + || !(cmdstat & (u32) rxLast)) { + printk(KERN_ERR + "%s: gt96100_rx: desc not first and last!\n", + dev->name); + continue; + } + // drop this received pkt if there were any errors + if ((cmdstat & (u32) rxErrorSummary) + || (status & icrRxErrorQ0)) { + // update the detailed rx error counters that are not covered + // by the MIB counters. + if (cmdstat & (u32) rxOverrun) + gp->stats.rx_fifo_errors++; + continue; + } + + pkt_len = dma32_to_cpu(rd->buff_cnt_sz) & rdByteCntMask; + + /* Create new skb. */ + skb = dev_alloc_skb(pkt_len + 2); + if (skb == NULL) { + printk(KERN_ERR + "%s: Memory squeeze, dropping packet.\n", + dev->name); + gp->stats.rx_dropped++; + continue; + } + skb->dev = dev; + skb_reserve(skb, 2); /* 16 byte IP header align */ + skb_put(skb, pkt_len); /* Make room */ + eth_copy_and_sum(skb, gp->rx_buff[nextOut], pkt_len, 0); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); /* pass the packet to upper layers */ + + // now we can release ownership of this desc back to device + cmdstat |= (u32) rxOwn; + rd->cmdstat = cpu_to_dma32(cmdstat); + + dev->last_rx = jiffies; + } + + gp->rx_next_out = nextOut; + return 0; +} + + +static void gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + u32 status; + + if (dev == NULL) { + printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name); + return; + } + + status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE); + // ACK interrupts +#if 0 + GT96100ETH_CLRBIT(gp, GT96100_ETH_INT_CAUSE, + icrEtherIntSum | icrRxBufferQ1 | icrRxBufferQ2 | + icrRxBufferQ3 | icrRxBufferQ0 | icrTxBufferHigh | + icrTxEndHigh | icrTxBufferLow | icrTxEndLow | + icrTxErrorHigh | icrTxErrorLow | icrTxUdr); +#else + GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0); +#endif + + if ((status & icrEtherIntSum) == 0) { + // not our interrupt + //printk("%s: isr: no ints? icr=%x,cp0_cause=%x\n", + // dev->name, status, read_32bit_cp0_register(CP0_CAUSE)); + return; + } + + if (gt96100_debug > 3) + printk("%s: isr: entry, icr=%x\n", dev->name, status); + + if (status & (icrRxBufferQ1 | icrRxBufferQ2 | icrRxBufferQ3)) { + printk(KERN_ERR "%s: isr: Rx intr in unused queues!?\n", + dev->name); + } + + if (status & icrRxBufferQ0) { + gt96100_rx(dev, status); + } + + if (status & (icrTxBufferHigh | icrTxEndHigh)) { + printk(KERN_ERR "%s: isr: Tx intr in unused queue!?\n", + dev->name); + } + + if (status & icrMIIPhySTC) { + u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS); + printk("%s: port status:\n", dev->name); + printk + ("%s: %s MBit/s, %s-duplex, flow-control %s, link is %s,\n", + dev->name, psr & psrSpeed ? "100" : "10", + psr & psrDuplex ? "full" : "half", + psr & psrFctl ? "disabled" : "enabled", + psr & psrLink ? "up" : "down"); + printk + ("%s: TxLowQ is %s, TxHighQ is %s, Transmitter is %s\n", + dev->name, psr & psrTxLow ? "running" : "stopped", + psr & psrTxHigh ? "running" : "stopped", + psr & psrTxInProg ? "on" : "off"); + gp->last_psr = psr; + } + + if (status & (icrTxBufferLow | icrTxEndLow)) { + int nextOut; + gt96100_td_t *td; + u32 cmdstat; + + // Continue until we reach the current descriptor pointer + for (nextOut = gp->tx_next_out; + nextOut != + (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0) - + gp->tx_ring_dma) / sizeof(gt96100_td_t); + nextOut = (nextOut + 1) % TX_RING_SIZE) { + + td = &gp->tx_ring[nextOut]; + cmdstat = dma32_to_cpu(td->cmdstat); + + if (gt96100_debug > 2) + printk("%s: isr: Tx desc cmdstat=%x\n", + dev->name, cmdstat); + + if (cmdstat & (u32) txOwn) { + cmdstat &= ~((u32) txOwn); + td->cmdstat = cpu_to_dma32(cmdstat); + printk(KERN_ERR + "%s: isr: Tx ownership bit wrong!\n", + dev->name); + } + // increment Tx error stats + if (cmdstat & (u32) txErrorSummary) { + if (gt96100_debug > 2) + printk + ("%s: gt96100_interrupt: Tx error, cmdstat = %x\n", + dev->name, cmdstat); + gp->stats.tx_errors++; + if (cmdstat & (u32) txReTxLimit) + gp->stats.collisions++; + if (cmdstat & (u32) txUnderrun) + gp->stats.tx_fifo_errors++; + if (cmdstat & (u32) txLateCollision) + gp->stats.tx_window_errors++; + } + // Wake the queue if the ring was full + if (gp->tx_count == TX_RING_SIZE) + netif_wake_queue(dev); + + // decrement tx ring buffer count + if (gp->tx_count) + gp->tx_count--; + + // free the skb + if (gp->tx_skbuff[nextOut]) { + if (gt96100_debug > 2) + printk + ("%s: isr: good Tx, skb=%p\n", + dev->name, + gp->tx_skbuff[nextOut]); + dev_kfree_skb_irq(gp->tx_skbuff[nextOut]); + gp->tx_skbuff[nextOut] = NULL; + } else { + printk(KERN_ERR "%s: isr: no skb!\n", + dev->name); + } + } + + if (gp->tx_count == 0 && nextOut != gp->tx_next_in) { + // FIX! this should probably be a panic + printk(KERN_ERR + "%s: isr: warning! Tx queue inconsistent\n", + dev->name); + } + + gp->tx_next_out = nextOut; + + if ((status & icrTxEndLow) && gp->tx_count != 0) { + // we must restart the DMA + if (gt96100_debug > 2) + printk("%s: isr: Restarting Tx DMA\n", + dev->name); + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, + sdcmrERD | sdcmrTXDL); + } + } + // Now check TX errors (RX errors were handled in gt96100_rx) + + if (status & icrTxErrorHigh) { + printk(KERN_ERR + "%s: isr: Tx resource error in unused queue!?\n", + dev->name); + } + + if (status & icrTxErrorLow) { + printk(KERN_ERR "%s: isr: Tx resource error\n", dev->name); + } + + if (status & icrTxUdr) { + printk(KERN_ERR "%s: isr: Tx underrun error\n", dev->name); + } + + if (gt96100_debug > 3) + printk("%s: isr: exit, icr=%x\n", + dev->name, GT96100ETH_READ(gp, + GT96100_ETH_INT_CAUSE)); +} + + +/* + * The Tx ring has been full longer than the watchdog timeout + * value, meaning that the interrupt routine has not been freeing + * up space in the Tx ring buffer. + */ +static void gt96100_tx_timeout(struct net_device *dev) +{ +// struct gt96100_private *gp = (struct gt96100_private *)dev->priv; + + printk(KERN_ERR "%s: gt96100_tx_timeout: dev=%p\n", dev->name, + dev); + + // FIX! do something, like reset the device +} + + +static void gt96100_set_rx_mode(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + unsigned long flags; + struct dev_mc_list *mcptr; + + if (gt96100_debug > 2) + printk("%s: gt96100_set_rx_mode: dev=%p, flags=%x\n", + dev->name, dev, dev->flags); + + // stop the Receiver DMA + abort(dev, sdcmrAR); + + spin_lock_irqsave(&gp->lock, flags); + + if (dev->flags & IFF_PROMISC) + GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, + pcrEN | pcrHS | pcrPM); + + memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear hash table + // Add our ethernet address + gt96100_add_hash_entry(dev, dev->dev_addr); + + if (dev->mc_count) { + for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) { + gt96100_add_hash_entry(dev, mcptr->dmi_addr); + } + } + // restart Rx DMA + GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD); + + spin_unlock_irqrestore(&gp->lock, flags); +} + +static struct net_device_stats *gt96100_get_stats(struct net_device *dev) +{ + struct gt96100_private *gp = (struct gt96100_private *) dev->priv; + unsigned long flags; + + if (gt96100_debug > 2) + printk("%s: gt96100_get_stats: dev=%p\n", dev->name, dev); + + if (netif_device_present(dev)) { + spin_lock_irqsave(&gp->lock, flags); + update_stats(gp); + spin_unlock_irqrestore(&gp->lock, flags); + } + + return &gp->stats; +} + +module_init(gt96100_probe); diff --git a/drivers/net/gt96100eth.h b/drivers/net/gt96100eth.h new file mode 100644 index 000000000..2bca8d8ef --- /dev/null +++ b/drivers/net/gt96100eth.h @@ -0,0 +1,325 @@ +/* + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or support@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Ethernet driver definitions for the MIPS GT96100 Advanced + * Communication Controller. + * + */ +#ifndef _GT96100ETH_H +#define _GT96100ETH_H + +#include + +/* Keep the ring sizes a power of two for efficiency. */ +#define TX_RING_SIZE 16 +#define RX_RING_SIZE 32 +#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ + +#define RX_HASH_TABLE_SIZE 16384 +#define HASH_HOP_NUMBER 12 + +#define NUM_INTERFACES 2 + +#define GT96100ETH_TX_TIMEOUT HZ + +#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG) +#define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE) + +#ifdef CONFIG_MIPS_EV96100 +#define GT96100_ETHER0_IRQ 4 +#define GT96100_ETHER1_IRQ 4 +#else +#define GT96100_ETHER0_IRQ -1 +#define GT96100_ETHER1_IRQ -1 +#endif + +#define GT96100ETH_READ(gp, offset) \ + GT96100_READ((gp->port_offset + offset)) + +#define GT96100ETH_WRITE(gp, offset, data) \ + GT96100_WRITE((gp->port_offset + offset), data) + +#define GT96100ETH_SETBIT(gp, offset, bits) {\ + u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \ + GT96100ETH_WRITE(gp, offset, val); } + +#define GT96100ETH_CLRBIT(gp, offset, bits) {\ + u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \ + GT96100ETH_WRITE(gp, offset, val); } + + +/* Bit definitions of the SMI Reg */ +enum { + smirDataMask = 0xffff, + smirPhyAdMask = 0x1f << 16, + smirPhyAdBit = 16, + smirRegAdMask = 0x1f << 21, + smirRegAdBit = 21, + smirOpCode = 1 << 26, + smirReadValid = 1 << 27, + smirBusy = 1 << 28 +}; + +/* Bit definitions of the Port Config Reg */ +enum pcr_bits { + pcrPM = 1, + pcrRBM = 2, + pcrPBF = 4, + pcrEN = 1 << 7, + pcrLPBKMask = 0x3 << 8, + pcrLPBKBit = 8, + pcrFC = 1 << 10, + pcrHS = 1 << 12, + pcrHM = 1 << 13, + pcrHDM = 1 << 14, + pcrHD = 1 << 15, + pcrISLMask = 0x7 << 28, + pcrISLBit = 28, + pcrACCS = 1 << 31 +}; + +/* Bit definitions of the Port Config Extend Reg */ +enum pcxr_bits { + pcxrIGMP = 1, + pcxrSPAN = 2, + pcxrPAR = 4, + pcxrPRIOtxMask = 0x7 << 3, + pcxrPRIOtxBit = 3, + pcxrPRIOrxMask = 0x3 << 6, + pcxrPRIOrxBit = 6, + pcxrPRIOrxOverride = 1 << 8, + pcxrDPLXen = 1 << 9, + pcxrFCTLen = 1 << 10, + pcxrFLP = 1 << 11, + pcxrFCTL = 1 << 12, + pcxrMFLMask = 0x3 << 14, + pcxrMFLBit = 14, + pcxrMIBclrMode = 1 << 16, + pcxrSpeed = 1 << 18, + pcxrSpeeden = 1 << 19, + pcxrRMIIen = 1 << 20, + pcxrDSCPen = 1 << 21 +}; + +/* Bit definitions of the Port Command Reg */ +enum pcmr_bits { + pcmrFJ = 1 << 15 +}; + + +/* Bit definitions of the Port Status Reg */ +enum psr_bits { + psrSpeed = 1, + psrDuplex = 2, + psrFctl = 4, + psrLink = 8, + psrPause = 1 << 4, + psrTxLow = 1 << 5, + psrTxHigh = 1 << 6, + psrTxInProg = 1 << 7 +}; + +/* Bit definitions of the SDMA Config Reg */ +enum sdcr_bits { + sdcrRCMask = 0xf << 2, + sdcrRCBit = 2, + sdcrBLMR = 1 << 6, + sdcrBLMT = 1 << 7, + sdcrPOVR = 1 << 8, + sdcrRIFB = 1 << 9, + sdcrBSZMask = 0x3 << 12, + sdcrBSZBit = 12 +}; + +/* Bit definitions of the SDMA Command Reg */ +enum sdcmr_bits { + sdcmrERD = 1 << 7, + sdcmrAR = 1 << 15, + sdcmrSTDH = 1 << 16, + sdcmrSTDL = 1 << 17, + sdcmrTXDH = 1 << 23, + sdcmrTXDL = 1 << 24, + sdcmrAT = 1 << 31 +}; + +/* Bit definitions of the Interrupt Cause Reg */ +enum icr_bits { + icrRxBuffer = 1, + icrTxBufferHigh = 1 << 2, + icrTxBufferLow = 1 << 3, + icrTxEndHigh = 1 << 6, + icrTxEndLow = 1 << 7, + icrRxError = 1 << 8, + icrTxErrorHigh = 1 << 10, + icrTxErrorLow = 1 << 11, + icrRxOVR = 1 << 12, + icrTxUdr = 1 << 13, + icrRxBufferQ0 = 1 << 16, + icrRxBufferQ1 = 1 << 17, + icrRxBufferQ2 = 1 << 18, + icrRxBufferQ3 = 1 << 19, + icrRxErrorQ0 = 1 << 20, + icrRxErrorQ1 = 1 << 21, + icrRxErrorQ2 = 1 << 22, + icrRxErrorQ3 = 1 << 23, + icrMIIPhySTC = 1 << 28, + icrSMIdone = 1 << 29, + icrEtherIntSum = 1 << 31 +}; + + +/* The Rx and Tx descriptor lists. */ + +typedef struct { + u32 cmdstat; + u32 byte_cnt; + u32 buff_ptr; + u32 next; +} gt96100_td_t; + +#define tdByteCntBit 16 + +typedef struct { + u32 cmdstat; + u32 buff_cnt_sz; + u32 buff_ptr; + u32 next; +} gt96100_rd_t; + +#define rdBuffSzBit 16 +#define rdByteCntMask 0xffff + + +/* Values for the Tx command-status descriptor entry. */ +enum td_cmdstat { + txOwn = 1 << 31, + txAutoMode = 1 << 30, + txEI = 1 << 23, + txGenCRC = 1 << 22, + txPad = 1 << 18, + txFirst = 1 << 17, + txLast = 1 << 16, + txErrorSummary = 1 << 15, + txReTxCntMask = 0x0f << 10, + txReTxCntBit = 10, + txCollision = 1 << 9, + txReTxLimit = 1 << 8, + txUnderrun = 1 << 6, + txLateCollision = 1 << 5 +}; + +#define TxReTxCntBit 10 + +/* Values for the Rx command-status descriptor entry. */ +enum rd_cmdstat { + rxOwn = 1 << 31, + rxAutoMode = 1 << 30, + rxEI = 1 << 23, + rxFirst = 1 << 17, + rxLast = 1 << 16, + rxErrorSummary = 1 << 15, + rxIGMP = 1 << 14, + rxHashExpired = 1 << 13, + rxMissedFrame = 1 << 12, + rxFrameType = 1 << 11, + rxShortFrame = 1 << 8, + rxMaxFrameLen = 1 << 7, + rxOverrun = 1 << 6, + rxCollision = 1 << 4, + rxCRCError = 1 +}; + +/* Bit fields of a Hash Table Entry */ +enum hash_table_entry { + hteValid = 1, + hteSkip = 2, + hteRD = 4 +}; + +// The MIB counters +typedef struct { + u32 byteReceived; + u32 byteSent; + u32 framesReceived; + u32 framesSent; + u32 totalByteReceived; + u32 totalFramesReceived; + u32 broadcastFramesReceived; + u32 multicastFramesReceived; + u32 cRCError; + u32 oversizeFrames; + u32 fragments; + u32 jabber; + u32 collision; + u32 lateCollision; + u32 frames64; + u32 frames65_127; + u32 frames128_255; + u32 frames256_511; + u32 frames512_1023; + u32 frames1024_MaxSize; + u32 macRxError; + u32 droppedFrames; + u32 outMulticastFrames; + u32 outBroadcastFrames; + u32 undersizeFrames; +} mib_counters_t; + + +struct gt96100_private { + gt96100_rd_t *rx_ring; + gt96100_td_t *tx_ring; + // The Rx and Tx rings must be 16-byte aligned + dma_addr_t rx_ring_dma; + dma_addr_t tx_ring_dma; + char *hash_table; + // The Hash Table must be 8-byte aligned + dma_addr_t hash_table_dma; + int hash_mode; + + // The Rx buffers must be 8-byte aligned + char *rx_buff[RX_RING_SIZE]; + // Tx buffers (tx_skbuff[i]->data) with less than 8 bytes + // of payload must be 8-byte aligned + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + int rx_next_out; /* The next free ring entry to receive */ + int tx_next_in; /* The next free ring entry to send */ + int tx_next_out; /* The last ring entry the ISR processed */ + int tx_count; /* current # of pkts waiting to be sent in Tx ring */ + + mib_counters_t mib; + struct net_device_stats stats; + + int io_size; + int port_num; // 0 or 1 + u32 port_offset; + + int phy_addr; // PHY address + u32 last_psr; // last value of the port status register + + int options; /* User-settable misc. driver options. */ + int drv_flags; + unsigned char phys[2]; /* MII device addresses. */ + spinlock_t lock; /* Serialise access to device */ +}; + +#endif diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 447192b20..4084ba601 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -23,9 +23,10 @@ #define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ #define MACH_GROUP_BAGET 9 /* Baget */ #define MACH_GROUP_ORION 10 /* CoSine Orion */ +#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards*/ #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", \ - "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion" } + "SNI", "ACN", "SGI", "Cobalt", "NEC DDB", "Baget", "Orion", "Galileo" } /* * Valid machtype values for group unknown (low order halfword of mips_machtype) @@ -114,6 +115,13 @@ #define GROUP_BAGET_NAMES { "BT23-201", "BT23-202" } +/* + * Valid machtype for group GALILEO + */ +#define MACH_EV96100 0 /* EV96100 */ + +#define GROUP_GALILEO_NAMES { "EV96100" } + /* * Valid cputype values */ diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h new file mode 100644 index 000000000..92a34cf7e --- /dev/null +++ b/include/asm-mips/galileo-boards/ev96100.h @@ -0,0 +1,55 @@ +/* + * + */ +#ifndef _MIPS_EV96100_H +#define _MIPS_EV96100_H + +#include + +/* + * GT64120 config space base address + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) +#define MIPS_GT_BASE GT64120_BASE + +/* + * PCI Bus allocation + */ +#define GT_PCI_MEM_BASE 0x12000000 +#define GT_PCI_MEM_SIZE 0x02000000 +#define GT_PCI_IO_BASE 0x10000000 +#define GT_PCI_IO_SIZE 0x02000000 +#define GT_ISA_IO_BASE PCI_IO_BASE + +/* + * Duart I/O ports. + */ +#define EV96100_COM1_BASE_ADDR (0x1d000000 + 0x20) +#define EV96100_COM2_BASE_ADDR (0x1d000000 + 0x00) + + +/* + * EV96100 interrupt controller register base. + */ +#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) + +/* + * EV96100 UART register base. + */ +#define EV96100_UART0_REGS_BASE (KSEG1ADDR(EV96100_COM1_BASE_ADDR)) +#define EV96100_UART1_REGS_BASE (KSEG1ADDR(EV96100_COM2_BASE_ADDR)) +#define EV96100_BASE_BAUD ( 3686400 / 16 ) + + +/* + * Because of an error/peculiarity in the Galileo chip, we need to swap the + * bytes when running bigendian. + */ + +#define GT_WRITE(ofs, data) \ + *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) +#define GT_READ(ofs, data) \ + data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) + + +#endif /* !(_MIPS_EV96100_H) */ diff --git a/include/asm-mips/galileo-boards/ev96100int.h b/include/asm-mips/galileo-boards/ev96100int.h new file mode 100644 index 000000000..47d0016bb --- /dev/null +++ b/include/asm-mips/galileo-boards/ev96100int.h @@ -0,0 +1,12 @@ +/* + * + */ +#ifndef _MIPS_EV96100INT_H +#define _MIPS_EV96100INT_H + +#define EV96100INT_UART_0 6 /* IP 6 */ +#define EV96100INT_TIMER 7 /* IP 7 */ + +extern void ev96100int_init(void); + +#endif /* !(_MIPS_EV96100_H) */ diff --git a/include/asm-mips/galileo-boards/gt64120.h b/include/asm-mips/galileo-boards/gt64120.h new file mode 100644 index 000000000..c2229af97 --- /dev/null +++ b/include/asm-mips/galileo-boards/gt64120.h @@ -0,0 +1,320 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Register definitions for Galileo 64120 system controller. + * + */ +#ifndef GT64120_H +#define GT64120_H + +#define MSK(n) ((1 << (n)) - 1) + +/************************************************************************ + * Register offset addresses + ************************************************************************/ + +#define GT_CPU_OFS 0x000 + +#define GT_INTRCAUSE_OFS 0xc18 +#define GT_PCI0_CFGADDR_OFS 0xcf8 +#define GT_PCI0_CFGDATA_OFS 0xcfc +#define GT_SDRAM_BM_OFS 0x478 +#define GT_SDRAM_ADDRDECODE_OFS 0x47c +#define GT_SDRAM_B0_OFS 0x44c +#define GT_SDRAM_B2_OFS 0x454 +#define GT_SDRAM_CFG_OFS 0x448 +#define GT_SDRAM_OPMODE_OFS 0x474 + +#define GT_ISD_OFS 0x068 + +#define GT_SCS10LD_OFS 0x008 +#define GT_SCS10HD_OFS 0x010 +#define GT_SCS32LD_OFS 0x018 +#define GT_SCS32HD_OFS 0x020 +#define GT_CS20LD_OFS 0x028 +#define GT_CS20HD_OFS 0x030 +#define GT_CS3BOOTLD_OFS 0x038 +#define GT_CS3BOOTHD_OFS 0x040 +#define GT_PCI0IOLD_OFS 0x048 +#define GT_PCI0IOHD_OFS 0x050 +#define GT_PCI0M0LD_OFS 0x058 +#define GT_PCI0M0HD_OFS 0x060 +#define GT_PCI0M1LD_OFS 0x080 +#define GT_PCI0M1HD_OFS 0x088 +#define GT_PCI1IOLD_OFS 0x090 +#define GT_PCI1IOHD_OFS 0x098 +#define GT_PCI1M0LD_OFS 0x0a0 +#define GT_PCI1M0HD_OFS 0x0a8 +#define GT_PCI1M1LD_OFS 0x0b0 +#define GT_PCI1M1HD_OFS 0x0b8 + +#define GT_SCS0LD_OFS 0x400 +#define GT_SCS0HD_OFS 0x404 +#define GT_SCS1LD_OFS 0x408 +#define GT_SCS1HD_OFS 0x40c +#define GT_SCS2LD_OFS 0x410 +#define GT_SCS2HD_OFS 0x414 +#define GT_SCS3LD_OFS 0x418 +#define GT_SCS3HD_OFS 0x41c +#define GT_CS0LD_OFS 0x420 +#define GT_CS0HD_OFS 0x424 +#define GT_CS1LD_OFS 0x428 +#define GT_CS1HD_OFS 0x42c +#define GT_CS2LD_OFS 0x430 +#define GT_CS2HD_OFS 0x434 +#define GT_CS3LD_OFS 0x438 +#define GT_CS3HD_OFS 0x43c +#define GT_BOOTLD_OFS 0x440 +#define GT_BOOTHD_OFS 0x444 + +#define GT_PCI0_BS_SCS10_OFS 0Xc08 +#define GT_PCI0_BS_SCS32_OFS 0xc0c +#define GT_PCI0_BARE_OFS 0Xc3c + +#define GT_PCI0_TOR_OFS 0xc04 + +#define GT_PCI0_IACK_OFS 0xc34 + + +/************************************************************************ + * Register encodings + ************************************************************************/ + +#define GT_CPU_WR_SHF 16 +#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) +#define GT_CPU_WR_BIT GT_CPU_WR_MSK +#define GT_CPU_WR_DXDXDXDX 0 +#define GT_CPU_WR_DDDD 1 + + +#define GT_CFGADDR_CFGEN_SHF 31 +#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) +#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK + +#define GT_CFGADDR_BUSNUM_SHF 16 +#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) + +#define GT_CFGADDR_DEVNUM_SHF 11 +#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) + +#define GT_CFGADDR_FUNCNUM_SHF 8 +#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) + +#define GT_CFGADDR_REGNUM_SHF 2 +#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) + + +#define GT_SDRAM_BM_ORDER_SHF 2 +#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) +#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK +#define GT_SDRAM_BM_ORDER_SUB 1 +#define GT_SDRAM_BM_ORDER_LIN 0 + +#define GT_SDRAM_BM_RSVD_ALL1 0xFFB + + +#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 +#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) +#define GT_SDRAM_ADDRDECODE_ADDR_0 0 +#define GT_SDRAM_ADDRDECODE_ADDR_1 1 +#define GT_SDRAM_ADDRDECODE_ADDR_2 2 +#define GT_SDRAM_ADDRDECODE_ADDR_3 3 +#define GT_SDRAM_ADDRDECODE_ADDR_4 4 +#define GT_SDRAM_ADDRDECODE_ADDR_5 5 +#define GT_SDRAM_ADDRDECODE_ADDR_6 6 +#define GT_SDRAM_ADDRDECODE_ADDR_7 7 + + +#define GT_SDRAM_B0_CASLAT_SHF 0 +#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) +#define GT_SDRAM_B0_CASLAT_2 1 +#define GT_SDRAM_B0_CASLAT_3 2 + +#define GT_SDRAM_B0_FTDIS_SHF 2 +#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) +#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK + +#define GT_SDRAM_B0_SRASPRCHG_SHF 3 +#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) +#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK +#define GT_SDRAM_B0_SRASPRCHG_2 0 +#define GT_SDRAM_B0_SRASPRCHG_3 1 + +#define GT_SDRAM_B0_B0COMPAB_SHF 4 +#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) +#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK + +#define GT_SDRAM_B0_64BITINT_SHF 5 +#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) +#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK +#define GT_SDRAM_B0_64BITINT_2 0 +#define GT_SDRAM_B0_64BITINT_4 1 + +#define GT_SDRAM_B0_BW_SHF 6 +#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) +#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK +#define GT_SDRAM_B0_BW_32 0 +#define GT_SDRAM_B0_BW_64 1 + +#define GT_SDRAM_B0_BLODD_SHF 7 +#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) +#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK + +#define GT_SDRAM_B0_PAR_SHF 8 +#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) +#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK + +#define GT_SDRAM_B0_BYPASS_SHF 9 +#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) +#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK + +#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 +#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) +#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK +#define GT_SDRAM_B0_SRAS2SCAS_2 0 +#define GT_SDRAM_B0_SRAS2SCAS_3 1 + +#define GT_SDRAM_B0_SIZE_SHF 11 +#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) +#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK +#define GT_SDRAM_B0_SIZE_16M 0 +#define GT_SDRAM_B0_SIZE_64M 1 + +#define GT_SDRAM_B0_EXTPAR_SHF 12 +#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) +#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK + +#define GT_SDRAM_B0_BLEN_SHF 13 +#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) +#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK +#define GT_SDRAM_B0_BLEN_8 0 +#define GT_SDRAM_B0_BLEN_4 1 + + +#define GT_SDRAM_CFG_REFINT_SHF 0 +#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) + +#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 +#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) +#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK + +#define GT_SDRAM_CFG_RMW_SHF 15 +#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) +#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK + +#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 +#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) +#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK + +#define GT_SDRAM_CFG_DUPCNTL_SHF 19 +#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) +#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK + +#define GT_SDRAM_CFG_DUPBA_SHF 20 +#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) +#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK + +#define GT_SDRAM_CFG_DUPEOT0_SHF 21 +#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) +#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK + +#define GT_SDRAM_CFG_DUPEOT1_SHF 22 +#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) +#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK + +#define GT_SDRAM_OPMODE_OP_SHF 0 +#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) +#define GT_SDRAM_OPMODE_OP_NORMAL 0 +#define GT_SDRAM_OPMODE_OP_NOP 1 +#define GT_SDRAM_OPMODE_OP_PRCHG 2 +#define GT_SDRAM_OPMODE_OP_MODE 3 +#define GT_SDRAM_OPMODE_OP_CBR 4 + + +#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 +#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) +#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK + +#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 +#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) +#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK + +#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 +#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) +#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK + +#define GT_PCI0_BARE_INTIODIS_SHF 3 +#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) +#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK + +#define GT_PCI0_BARE_INTMEMDIS_SHF 4 +#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) +#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK + +#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 +#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) +#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK + +#define GT_PCI0_BARE_CS20DIS_SHF 6 +#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) +#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK + +#define GT_PCI0_BARE_SCS32DIS_SHF 7 +#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) +#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK + +#define GT_PCI0_BARE_SCS10DIS_SHF 8 +#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) +#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK + + +#define GT_INTRCAUSE_MASABORT0_SHF 18 +#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) +#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK + +#define GT_INTRCAUSE_TARABORT0_SHF 19 +#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) +#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK + + +#define GT_PCI0_CFGADDR_REGNUM_SHF 2 +#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) +#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 +#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) +#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 +#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) +#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 +#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) +#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 +#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) +#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK + + +/************************************************************************ + * Misc + ************************************************************************/ + +#define GT_DEF_BASE 0x14000000 +#define GT_DEF_PCI0_MEM0_BASE 0x12000000 +#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ +#define GT_LATTIM_MIN 6 /* Minimum lat */ + +#endif /* #ifndef GT64120_H */ diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h new file mode 100644 index 000000000..4c48bd96c --- /dev/null +++ b/include/asm-mips/galileo-boards/gt96100.h @@ -0,0 +1,432 @@ +/* + * Copyright 2000 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * stevel@mvista.com or support@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Register offsets of the MIPS GT96100 Advanced Communication Controller. + * + */ +#ifndef _GT96100_H +#define _GT96100_H + +/* + * Galileo GT96100 internal register base. + */ +#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000)) + +#define GT96100_WRITE(ofs, data) \ + *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data) +#define GT96100_READ(ofs) \ + le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs)) + +#define GT96100_ETH_IO_SIZE 0x4000 + +/************************************************************************ + * Register offset addresses follow + ************************************************************************/ + +/* CPU Interface Control Registers */ +#define GT96100_CPU_INTERF_CONFIG 0x000000 + +/* Ethernet Ports */ +#define GT96100_ETH_PHY_ADDR_REG 0x080800 +#define GT96100_ETH_SMI_REG 0x080810 +/* + These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to + get offsets to port 1 registers. +*/ +#define GT96100_ETH_PORT_CONFIG 0x084800 +#define GT96100_ETH_PORT_CONFIG_EXT 0x084808 +#define GT96100_ETH_PORT_COMM 0x084810 +#define GT96100_ETH_PORT_STATUS 0x084818 +#define GT96100_ETH_SER_PARAM 0x084820 +#define GT96100_ETH_HASH_TBL_PTR 0x084828 +#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830 +#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838 +#define GT96100_ETH_SDMA_CONFIG 0x084840 +#define GT96100_ETH_SDMA_COMM 0x084848 +#define GT96100_ETH_INT_CAUSE 0x084850 +#define GT96100_ETH_INT_MASK 0x084858 +#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880 +#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884 +#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888 +#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C +#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0 +#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4 +#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8 +#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC +#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0 +#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4 +#define GT96100_ETH_MIB_COUNT_BASE 0x085800 + +/* SDMAs */ +#define GT96100_SDMA_GROUP_CONFIG 0x101AF0 +/* SDMA Group 0 */ +#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900 +#define GT96100_SDMA_G0_CHAN0_COMM 0x000908 +#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900 +#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910 +#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900 +#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910 +#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914 +#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900 +#define GT96100_SDMA_G0_CHAN1_COMM 0x010908 +#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900 +#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910 +#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900 +#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910 +#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914 +#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900 +#define GT96100_SDMA_G0_CHAN2_COMM 0x020908 +#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900 +#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910 +#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900 +#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910 +#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914 +#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900 +#define GT96100_SDMA_G0_CHAN3_COMM 0x030908 +#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900 +#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910 +#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900 +#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910 +#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914 +#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900 +#define GT96100_SDMA_G0_CHAN4_COMM 0x040908 +#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900 +#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910 +#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900 +#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910 +#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914 +#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900 +#define GT96100_SDMA_G0_CHAN5_COMM 0x050908 +#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900 +#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910 +#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900 +#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910 +#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914 +#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900 +#define GT96100_SDMA_G0_CHAN6_COMM 0x060908 +#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900 +#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910 +#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900 +#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910 +#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914 +#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900 +#define GT96100_SDMA_G0_CHAN7_COMM 0x070908 +#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900 +#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910 +#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900 +#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910 +#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914 +/* SDMA Group 1 */ +#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900 +#define GT96100_SDMA_G1_CHAN0_COMM 0x100908 +#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900 +#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910 +#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900 +#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910 +#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914 +#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900 +#define GT96100_SDMA_G1_CHAN1_COMM 0x110908 +#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900 +#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910 +#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900 +#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910 +#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914 +#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900 +#define GT96100_SDMA_G1_CHAN2_COMM 0x120908 +#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900 +#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910 +#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900 +#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910 +#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914 +#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900 +#define GT96100_SDMA_G1_CHAN3_COMM 0x130908 +#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900 +#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910 +#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900 +#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910 +#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914 +#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900 +#define GT96100_SDMA_G1_CHAN4_COMM 0x140908 +#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900 +#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910 +#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900 +#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910 +#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914 +#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900 +#define GT96100_SDMA_G1_CHAN5_COMM 0x150908 +#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900 +#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910 +#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900 +#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910 +#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914 +#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900 +#define GT96100_SDMA_G1_CHAN6_COMM 0x160908 +#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900 +#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910 +#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900 +#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910 +#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914 +#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900 +#define GT96100_SDMA_G1_CHAN7_COMM 0x170908 +#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900 +#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910 +#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900 +#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910 +#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914 +/* MPSCs */ +#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00 +#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04 +#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08 +#define GT96100_MPSC_CHAN0_REG1 0x000A0C +#define GT96100_MPSC_CHAN0_REG2 0x000A10 +#define GT96100_MPSC_CHAN0_REG3 0x000A14 +#define GT96100_MPSC_CHAN0_REG4 0x000A18 +#define GT96100_MPSC_CHAN0_REG5 0x000A1C +#define GT96100_MPSC_CHAN0_REG6 0x000A20 +#define GT96100_MPSC_CHAN0_REG7 0x000A24 +#define GT96100_MPSC_CHAN0_REG8 0x000A28 +#define GT96100_MPSC_CHAN0_REG9 0x000A2C +#define GT96100_MPSC_CHAN0_REG10 0x000A30 +#define GT96100_MPSC_CHAN0_REG11 0x000A34 +#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00 +#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04 +#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08 +#define GT96100_MPSC_CHAN1_REG1 0x008A0C +#define GT96100_MPSC_CHAN1_REG2 0x008A10 +#define GT96100_MPSC_CHAN1_REG3 0x008A14 +#define GT96100_MPSC_CHAN1_REG4 0x008A18 +#define GT96100_MPSC_CHAN1_REG5 0x008A1C +#define GT96100_MPSC_CHAN1_REG6 0x008A20 +#define GT96100_MPSC_CHAN1_REG7 0x008A24 +#define GT96100_MPSC_CHAN1_REG8 0x008A28 +#define GT96100_MPSC_CHAN1_REG9 0x008A2C +#define GT96100_MPSC_CHAN1_REG10 0x008A30 +#define GT96100_MPSC_CHAN1_REG11 0x008A34 +#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00 +#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04 +#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08 +#define GT96100_MPSC_CHAN2_REG1 0x010A0C +#define GT96100_MPSC_CHAN2_REG2 0x010A10 +#define GT96100_MPSC_CHAN2_REG3 0x010A14 +#define GT96100_MPSC_CHAN2_REG4 0x010A18 +#define GT96100_MPSC_CHAN2_REG5 0x010A1C +#define GT96100_MPSC_CHAN2_REG6 0x010A20 +#define GT96100_MPSC_CHAN2_REG7 0x010A24 +#define GT96100_MPSC_CHAN2_REG8 0x010A28 +#define GT96100_MPSC_CHAN2_REG9 0x010A2C +#define GT96100_MPSC_CHAN2_REG10 0x010A30 +#define GT96100_MPSC_CHAN2_REG11 0x010A34 +#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00 +#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04 +#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08 +#define GT96100_MPSC_CHAN3_REG1 0x018A0C +#define GT96100_MPSC_CHAN3_REG2 0x018A10 +#define GT96100_MPSC_CHAN3_REG3 0x018A14 +#define GT96100_MPSC_CHAN3_REG4 0x018A18 +#define GT96100_MPSC_CHAN3_REG5 0x018A1C +#define GT96100_MPSC_CHAN3_REG6 0x018A20 +#define GT96100_MPSC_CHAN3_REG7 0x018A24 +#define GT96100_MPSC_CHAN3_REG8 0x018A28 +#define GT96100_MPSC_CHAN3_REG9 0x018A2C +#define GT96100_MPSC_CHAN3_REG10 0x018A30 +#define GT96100_MPSC_CHAN3_REG11 0x018A34 +#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00 +#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04 +#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08 +#define GT96100_MPSC_CHAN4_REG1 0x020A0C +#define GT96100_MPSC_CHAN4_REG2 0x020A10 +#define GT96100_MPSC_CHAN4_REG3 0x020A14 +#define GT96100_MPSC_CHAN4_REG4 0x020A18 +#define GT96100_MPSC_CHAN4_REG5 0x020A1C +#define GT96100_MPSC_CHAN4_REG6 0x020A20 +#define GT96100_MPSC_CHAN4_REG7 0x020A24 +#define GT96100_MPSC_CHAN4_REG8 0x020A28 +#define GT96100_MPSC_CHAN4_REG9 0x020A2C +#define GT96100_MPSC_CHAN4_REG10 0x020A30 +#define GT96100_MPSC_CHAN4_REG11 0x020A34 +#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00 +#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04 +#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08 +#define GT96100_MPSC_CHAN5_REG1 0x028A0C +#define GT96100_MPSC_CHAN5_REG2 0x028A10 +#define GT96100_MPSC_CHAN5_REG3 0x028A14 +#define GT96100_MPSC_CHAN5_REG4 0x028A18 +#define GT96100_MPSC_CHAN5_REG5 0x028A1C +#define GT96100_MPSC_CHAN5_REG6 0x028A20 +#define GT96100_MPSC_CHAN5_REG7 0x028A24 +#define GT96100_MPSC_CHAN5_REG8 0x028A28 +#define GT96100_MPSC_CHAN5_REG9 0x028A2C +#define GT96100_MPSC_CHAN5_REG10 0x028A30 +#define GT96100_MPSC_CHAN5_REG11 0x028A34 +#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00 +#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04 +#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08 +#define GT96100_MPSC_CHAN6_REG1 0x030A0C +#define GT96100_MPSC_CHAN6_REG2 0x030A10 +#define GT96100_MPSC_CHAN6_REG3 0x030A14 +#define GT96100_MPSC_CHAN6_REG4 0x030A18 +#define GT96100_MPSC_CHAN6_REG5 0x030A1C +#define GT96100_MPSC_CHAN6_REG6 0x030A20 +#define GT96100_MPSC_CHAN6_REG7 0x030A24 +#define GT96100_MPSC_CHAN6_REG8 0x030A28 +#define GT96100_MPSC_CHAN6_REG9 0x030A2C +#define GT96100_MPSC_CHAN6_REG10 0x030A30 +#define GT96100_MPSC_CHAN6_REG11 0x030A34 +#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00 +#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04 +#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08 +#define GT96100_MPSC_CHAN7_REG1 0x038A0C +#define GT96100_MPSC_CHAN7_REG2 0x038A10 +#define GT96100_MPSC_CHAN7_REG3 0x038A14 +#define GT96100_MPSC_CHAN7_REG4 0x038A18 +#define GT96100_MPSC_CHAN7_REG5 0x038A1C +#define GT96100_MPSC_CHAN7_REG6 0x038A20 +#define GT96100_MPSC_CHAN7_REG7 0x038A24 +#define GT96100_MPSC_CHAN7_REG8 0x038A28 +#define GT96100_MPSC_CHAN7_REG9 0x038A2C +#define GT96100_MPSC_CHAN7_REG10 0x038A30 +#define GT96100_MPSC_CHAN7_REG11 0x038A34 +/* FlexTDMs */ +/* TDPR0 - Transmit Dual Port RAM. block size 0xff */ +#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00 +#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00 +#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00 +#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00 +/* RDPR0 - Receive Dual Port RAM. block size 0xff */ +#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00 +#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00 +#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00 +#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00 +#define GT96100_FXTDM0_TX_READ_PTR 0x008B00 +#define GT96100_FXTDM0_RX_READ_PTR 0x008B04 +#define GT96100_FXTDM0_CONFIG 0x008B08 +#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C +#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10 +#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14 +#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18 +#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00 +#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00 +#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00 +#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00 +#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00 +#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00 +#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00 +#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00 +#define GT96100_FXTDM1_TX_READ_PTR 0x018B00 +#define GT96100_FXTDM1_RX_READ_PTR 0x018B04 +#define GT96100_FXTDM1_CONFIG 0x018B08 +#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C +#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10 +#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14 +#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18 +#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00 +#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00 +#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00 +#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00 +#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00 +#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00 +#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00 +#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00 +#define GT96100_FLTDM2_TX_READ_PTR 0x028B00 +#define GT96100_FLTDM2_RX_READ_PTR 0x028B04 +#define GT96100_FLTDM2_CONFIG 0x028B08 +#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C +#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10 +#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14 +#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18 +#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00 +#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00 +#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00 +#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00 +#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00 +#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00 +#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00 +#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00 +#define GT96100_FXTDM3_TX_READ_PTR 0x038B00 +#define GT96100_FXTDM3_RX_READ_PTR 0x038B04 +#define GT96100_FXTDM3_CONFIG 0x038B08 +#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C +#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10 +#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14 +#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18 +/* Baud Rate Generators */ +#define GT96100_BRG0_CONFIG 0x102A00 +#define GT96100_BRG0_BAUD_TUNE 0x102A04 +#define GT96100_BRG1_CONFIG 0x102A08 +#define GT96100_BRG1_BAUD_TUNE 0x102A0C +#define GT96100_BRG2_CONFIG 0x102A10 +#define GT96100_BRG2_BAUD_TUNE 0x102A14 +#define GT96100_BRG3_CONFIG 0x102A18 +#define GT96100_BRG3_BAUD_TUNE 0x102A1C +#define GT96100_BRG4_CONFIG 0x102A20 +#define GT96100_BRG4_BAUD_TUNE 0x102A24 +#define GT96100_BRG5_CONFIG 0x102A28 +#define GT96100_BRG5_BAUD_TUNE 0x102A2C +#define GT96100_BRG6_CONFIG 0x102A30 +#define GT96100_BRG6_BAUD_TUNE 0x102A34 +#define GT96100_BRG7_CONFIG 0x102A38 +#define GT96100_BRG7_BAUD_TUNE 0x102A3C +/* Routing Registers */ +#define GT96100_ROUTE_MAIN 0x101A00 +#define GT96100_ROUTE_RX_CLOCK 0x101A10 +#define GT96100_ROUTE_TX_CLOCK 0x101A20 +/* General Purpose Ports */ +#define GT96100_GPP_CONFIG0 0x100A00 +#define GT96100_GPP_CONFIG1 0x100A04 +#define GT96100_GPP_CONFIG2 0x100A08 +#define GT96100_GPP_CONFIG3 0x100A0C +#define GT96100_GPP_IO0 0x100A20 +#define GT96100_GPP_IO1 0x100A24 +#define GT96100_GPP_IO2 0x100A28 +#define GT96100_GPP_IO3 0x100A2C +#define GT96100_GPP_DATA0 0x100A40 +#define GT96100_GPP_DATA1 0x100A44 +#define GT96100_GPP_DATA2 0x100A48 +#define GT96100_GPP_DATA3 0x100A4C +#define GT96100_GPP_LEVEL0 0x100A60 +#define GT96100_GPP_LEVEL1 0x100A64 +#define GT96100_GPP_LEVEL2 0x100A68 +#define GT96100_GPP_LEVEL3 0x100A6C +/* Watchdog */ +#define GT96100_WD_CONFIG 0x101A80 +#define GT96100_WD_VALUE 0x101A84 +/* Communication Unit Arbiter */ +#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0 +/* PCI Arbiters */ +#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0 +#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4 +/* CIU Arbiter */ +#define GT96100_CIU_ARBITER_CONFIG 0x101AC0 +/* Interrupt Controller */ +#define GT96100_MAIN_CAUSE 0x000C18 +#define GT96100_INT0_MAIN_MASK 0x000C1C +#define GT96100_INT1_MAIN_MASK 0x000C24 +#define GT96100_HIGH_CAUSE 0x000C98 +#define GT96100_INT0_HIGH_MASK 0x000C9C +#define GT96100_INT1_HIGH_MASK 0x000CA4 +#define GT96100_INT0_SELECT 0x000C70 +#define GT96100_INT1_SELECT 0x000C74 +#define GT96100_SERIAL_CAUSE 0x103A00 +#define GT96100_SERINT0_MASK 0x103A80 +#define GT96100_SERINT1_MASK 0x103A88 + +#endif /* _GT96100_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 3af11a591..d8b09483d 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -317,6 +317,57 @@ __OUTS(b,b,1) __OUTS(h,w,2) __OUTS(w,l,4) + +#ifdef CONFIG_MIPS_EV96100 + +#include + +#define inb(port) in_8((u8 *)((port)+mips_io_port_base)) +#define outb(val, port) out_8((u8 *)((port)+mips_io_port_base), (val)) +#define inw(port) in_16((u16 *)((port)+mips_io_port_base)) +#define outw(val, port) out_16((u16 *)((port)+mips_io_port_base), (val)) +#define inl(port) in_32((u32 *)((port)+mips_io_port_base)) +#define outl(val, port) out_32((u32 *)((port)+mips_io_port_base), (val)) + +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) + +extern inline unsigned char in_8(const unsigned char *addr) +{ + return *KSEG1ADDR(addr); +} + +extern inline void out_8(unsigned char *addr, unsigned int val) +{ + *KSEG1ADDR(addr) = (unsigned char)val; +} + +extern inline unsigned short in_16(const unsigned short *addr) +{ + return (le16_to_cpu(*KSEG1ADDR(addr))); +} + +extern inline void out_16(unsigned short *addr, unsigned int val) +{ + *KSEG1ADDR(addr) = cpu_to_le16((unsigned short)val); +} + +extern inline unsigned int in_32(const unsigned int *addr) +{ + return (le32_to_cpu(*KSEG1ADDR(addr))); +} + +extern inline void out_32(unsigned int *addr, unsigned int val) +{ + *KSEG1ADDR(addr) = cpu_to_le32((unsigned int)val); +} + +#else + /* * Note that due to the way __builtin_constant_p() works, you * - can't use it inside an inline function (it will never be true) @@ -412,6 +463,7 @@ __OUTS(w,l,4) ((__builtin_constant_p((port)) && (port) < 32768) ? \ __inslc((port),(addr),(count)) : \ __insl((port),(addr),(count))) +#endif #define IO_SPACE_LIMIT 0xffff diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index f255684b4..519cacc25 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -76,6 +76,18 @@ #define JAZZ_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_MIPS_EV96100 +#include +#include +#define EV96100_SERIAL_PORT_DEFNS \ + { baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \ + irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \ + iomem_base: EV96100_UART0_REGS_BASE }, +#else +#define EV96100_SERIAL_PORT_DEFNS +#endif + + #define STD_SERIAL_PORT_DEFNS \ /* UART CLK PORT IRQ FLAGS */ \ { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ @@ -152,7 +164,8 @@ #endif #define SERIAL_PORT_DFNS \ + EV96100_SERIAL_PORT_DEFNS \ JAZZ_SERIAL_PORT_DEFNS \ STD_SERIAL_PORT_DEFNS \ EXTRA_SERIAL_PORT_DEFNS \ - HUB6_SERIAL_PORT_DFNS + HUB6_SERIAL_PORT_DFNS -- cgit v1.2.3