From c7fc24dc4420057f103afe8fc64524ebc25c5d37 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 25 Aug 1998 09:12:35 +0000
Subject:  o Merge with Linux 2.1.116.  o New Newport console code.  o New G364
 console code.

---
 drivers/char/rocket_int.h | 90 +++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 80 insertions(+), 10 deletions(-)

(limited to 'drivers/char/rocket_int.h')

diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h
index 8b2ea2212..604e8733b 100644
--- a/drivers/char/rocket_int.h
+++ b/drivers/char/rocket_int.h
@@ -482,6 +482,18 @@ Call:     sDisCTSFlowCtl(ChP)
    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 }
 
+/***************************************************************************
+Function: sDisIXANY
+Purpose:  Disable IXANY Software Flow Control
+Call:     sDisIXANY(ChP)
+          CHANNEL_T *ChP; Ptr to channel structure
+*/
+#define sDisIXANY(ChP) \
+{ \
+   (ChP)->R[0x0e] = 0x86; \
+   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
+}
+
 /***************************************************************************
 Function: DisParity
 Purpose:  Disable parity
@@ -572,6 +584,18 @@ Call:     sEnCTSFlowCtl(ChP)
    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 }
 
+/***************************************************************************
+Function: sEnIXANY
+Purpose:  Enable IXANY Software Flow Control
+Call:     sEnIXANY(ChP)
+          CHANNEL_T *ChP; Ptr to channel structure
+*/
+#define sEnIXANY(ChP) \
+{ \
+   (ChP)->R[0x0e] = 0x21; \
+   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
+}
+
 /***************************************************************************
 Function: EnParity
 Purpose:  Enable parity
@@ -646,6 +670,18 @@ Call:     sEnTransmit(ChP)
    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 }
 
+/***************************************************************************
+Function: sEnTxSoftFlowCtl
+Purpose:  Enable Tx Software Flow Control
+Call:     sEnTxSoftFlowCtl(ChP)
+          CHANNEL_T *ChP; Ptr to channel structure
+*/
+#define sEnTxSoftFlowCtl(ChP) \
+{ \
+   (ChP)->R[0x06] = 0xc5; \
+   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
+}
+
 /***************************************************************************
 Function: sGetAiopIntStatus
 Purpose:  Get the AIOP interrupt status
@@ -984,6 +1020,32 @@ Call:     sSetStop2(ChP)
    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 }
 
+/***************************************************************************
+Function: sSetTxXOFFChar
+Purpose:  Set the Tx XOFF flow control character
+Call:     sSetTxXOFFChar(ChP,Ch)
+          CHANNEL_T *ChP; Ptr to channel structure
+          Byte_t Ch; The value to set the Tx XOFF character to
+*/
+#define sSetTxXOFFChar(ChP,CH) \
+{ \
+   (ChP)->R[0x07] = (CH); \
+   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
+}
+
+/***************************************************************************
+Function: sSetTxXONChar
+Purpose:  Set the Tx XON flow control character
+Call:     sSetTxXONChar(ChP,Ch)
+          CHANNEL_T *ChP; Ptr to channel structure
+          Byte_t Ch; The value to set the Tx XON character to
+*/
+#define sSetTxXONChar(ChP,CH) \
+{ \
+   (ChP)->R[0x0b] = (CH); \
+   sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
+}
+
 /***************************************************************************
 Function: sStartRxProcessor
 Purpose:  Start a channel's receive processor
@@ -1133,17 +1195,25 @@ struct r_port {
 #undef PCI_DEVICE_ID_RP32INTF
 #endif
 
-#define PCI_VENDOR_ID_RP               0x11fe
-#define PCI_DEVICE_ID_RP32INTF         0x0001
-#define PCI_DEVICE_ID_RP8INTF          0x0002
-#define PCI_DEVICE_ID_RP16INTF         0x0003
-#define PCI_DEVICE_ID_RP8OCTA          0x0005
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
 
-#ifndef RP4QUAD
-#define PCI_DEVICE_ID_RP4QUAD	       0x0004
+#ifndef PCI_DEVICE_ID_RP4QUAD
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
 #endif
-#ifndef RP8J
-#define PCI_DEVICE_ID_RP8J	       0x0006
+#ifndef PCI_DEVICE_ID_RP8J
+#define PCI_DEVICE_ID_RP8J		0x0006
 #endif
-
+#ifndef PCI_DEVICE_ID_RPP4
+#define PCI_DEVICE_ID_RPP4		0x000A
+#endif
+#ifndef PCI_DEVICE_ID_RPP8
+#define PCI_DEVICE_ID_RPP8		0x000B
+#endif
+#ifndef PCI_DEVICE_ID_RP8M
+#define PCI_DEVICE_ID_RP8M		0x000C
+#endif	
 
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