From 1385617929e09545f9858785ea3dc1068fedfde1 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 5 Jun 2001 23:24:07 +0000
Subject: Support 512mb RAM configuration for Momenco Ocelot.  Patch from David
 Woodhouse (dwmw2@infradead.org).

---
 include/asm-mips/mipsregs.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'include/asm-mips/mipsregs.h')

diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 76da1b3aa..f45669442 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -72,6 +72,12 @@
 #define CP0_IWATCH $18
 #define CP0_DWATCH $19
 
+/* 
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+
 /*
  * Coprocessor 1 (FPU) register names
  */
@@ -165,6 +171,16 @@
         : "=r" (__res));                                        \
         __res;})
 
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
 /*
  * For now use this only with interrupts disabled!
  */
-- 
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