From 8ecd5b87ddd65325753a989b80a64c60294adbab Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 13 Dec 2000 19:43:03 +0000
Subject: First batch of PMC Ocelot CP7000 patches.

---
 include/asm-mips/pmc/ev64120.h    | 59 +++++++++++++++++++++++++++++++++++++++
 include/asm-mips/pmc/ev64120int.h | 32 +++++++++++++++++++++
 2 files changed, 91 insertions(+)
 create mode 100644 include/asm-mips/pmc/ev64120.h
 create mode 100644 include/asm-mips/pmc/ev64120int.h

(limited to 'include/asm-mips/pmc')

diff --git a/include/asm-mips/pmc/ev64120.h b/include/asm-mips/pmc/ev64120.h
new file mode 100644
index 000000000..74ad8c510
--- /dev/null
+++ b/include/asm-mips/pmc/ev64120.h
@@ -0,0 +1,59 @@
+/*
+ * This is a direct copy of the ev96100.h file, with a global search and
+ * replace.  The numbers are the same.
+ *
+ * The reason I'm duplicating this is so that the 64120/96100
+ * defines won't be confusing in the source code.
+ */
+#ifndef _ASM_PMC_CP7000_H
+#define _ASM_PMC_CP7000_H
+
+#include <asm/addrspace.h>
+
+/*
+ *   GT64120 config space base address
+ */
+#define GT64120_BASE    (KSEG1ADDR(0x14000000))
+#define MIPS_GT_BASE    GT64120_BASE
+ 
+/*
+ *   PCI Bus allocation
+ */
+#define GT_PCI_MEM_BASE    0x12000000
+#define GT_PCI_MEM_SIZE    0x02000000
+#define GT_PCI_IO_BASE     0x10000000
+#define GT_PCI_IO_SIZE     0x02000000
+#define GT_ISA_IO_BASE     PCI_IO_BASE          
+
+/*
+ *   Duart I/O ports.
+ */
+#define EV64120_COM1_BASE_ADDR  (0x1d000000 + 0x20) 
+#define EV64120_COM2_BASE_ADDR  (0x1d000000 + 0x00)
+
+
+/*
+ *   EV64120 interrupt controller register base.
+ */
+#define EV64120_ICTRL_REGS_BASE   (KSEG1ADDR(0x1f000000))
+
+/*
+ *   EV64120 UART register base.
+ */
+#define EV64120_UART0_REGS_BASE    (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
+#define EV64120_UART1_REGS_BASE    (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
+#define EV64120_BASE_BAUD ( 3686400 / 16 )
+
+
+/*
+ * Because of an error/peculiarity in the Galileo chip, we need to swap the 
+ * bytes when running bigendian.
+ */
+
+#define GT_WRITE(ofs, data)  \
+	*(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
+#define GT_READ(ofs, data)   \
+	*data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
+    
+
+#endif /* _ASM_PMC_CP7000_H */
diff --git a/include/asm-mips/pmc/ev64120int.h b/include/asm-mips/pmc/ev64120int.h
new file mode 100644
index 000000000..463f6b39d
--- /dev/null
+++ b/include/asm-mips/pmc/ev64120int.h
@@ -0,0 +1,32 @@
+#ifndef _ASM_PMC_CP7000INT_H
+#define _ASM_PMC_CP7000INT_H
+
+#define INT_CAUSE_MAIN 0
+#define INT_CAUSE_HIGH 1
+
+#define MAX_CAUSE_REGS 4
+#define MAX_CAUSE_REG_WIDTH 32
+
+void hook_irq_handler (int int_cause , int bit_num , void *isr_ptr);
+int disable_galileo_irq (int int_cause , int bit_num);
+int enable_galileo_irq (int int_cause , int bit_num);
+
+extern struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
+
+/*
+ * PCI interrupts will come in on either the INTA or INTD interrups lines,
+ * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
+ * boards, they all either come in on IntD or they all come in on IntA, they
+ * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
+ * "requested" interrupt numbers and go through the list whenever we get an
+ * IntA/D.
+ *
+ * All PCI interrupts have numbers >= 20 by arbitrary convention.  Any
+ * interrupt < 8 is an interrupt that is maskable on MIPS.
+ */
+
+#define TIMER	4
+#define INTA	2
+#define INTD	5
+
+#endif /* _ASM_PMC_CP7000INT_H */
-- 
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