From 706a11128cbe9c614436350e5ff807b6d6ac79ea Mon Sep 17 00:00:00 2001 From: Kanoj Sarcar Date: Thu, 29 Jun 2000 18:29:59 +0000 Subject: Tlb miss handling updates: need to fill in the processor id only once during bootup. --- include/asm-mips64/mmu_context.h | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'include/asm-mips64') diff --git a/include/asm-mips64/mmu_context.h b/include/asm-mips64/mmu_context.h index 7f70157c4..0a31078da 100644 --- a/include/asm-mips64/mmu_context.h +++ b/include/asm-mips64/mmu_context.h @@ -17,6 +17,19 @@ #include #include +/* + * For the fast tlb miss handlers, we currently keep a per cpu array + * of pointers to the current pgd for each processor. Also, the proc. + * id is stuffed into the context register. This should be changed to + * use the processor id via current->processor, where current is stored + * in watchhi/lo. The context register should be used to contiguously + * map the page tables. + */ +#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ + pgd_current[smp_processor_id()] = (unsigned long)(pgd) +#define TLBMISS_HANDLER_SETUP() \ + set_context((unsigned long) smp_processor_id() << (23 + 3)); \ + TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) extern unsigned long pgd_current[]; #ifndef CONFIG_SMP @@ -88,8 +101,7 @@ extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, get_new_cpu_mmu_context(next, cpu); set_entryhi(CPU_CONTEXT(cpu, next) & 0xff); - set_context((unsigned long) smp_processor_id() << (23 + 3)); - pgd_current[smp_processor_id()] = next->pgd; + TLBMISS_HANDLER_SETUP_PGD(next->pgd); } /* @@ -115,8 +127,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) get_new_cpu_mmu_context(next, smp_processor_id()); set_entryhi(CPU_CONTEXT(smp_processor_id(), next) & 0xff); - set_context((unsigned long) smp_processor_id() << (23 + 3)); - pgd_current[smp_processor_id()] = next->pgd; + TLBMISS_HANDLER_SETUP_PGD(next->pgd); } #endif /* _ASM_MMU_CONTEXT_H */ -- cgit v1.2.3