From 1385617929e09545f9858785ea3dc1068fedfde1 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 5 Jun 2001 23:24:07 +0000
Subject: Support 512mb RAM configuration for Momenco Ocelot.  Patch from David
 Woodhouse (dwmw2@infradead.org).

---
 include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h | 10 ++++++----
 include/asm-mips/mipsregs.h                           | 16 ++++++++++++++++
 include/asm-mips/pgtable.h                            | 10 ++++++++++
 include/asm-mips/serial.h                             |  2 +-
 4 files changed, 33 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
index 9984048f2..b87658a66 100644
--- a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
+++ b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h
@@ -19,14 +19,16 @@
 #include <asm/byteorder.h>		/* for cpu_to_le32() */
 
 /*
- * PCI address allocatoin 
+ * PCI address allocation 
  */
-#define GT_PCI_MEM_BASE    GT_DEF_PCI0_MEM0_BASE
+#define GT_PCI_MEM_BASE    (0x22000000)
 #define GT_PCI_MEM_SIZE    GT_DEF_PCI0_MEM0_SIZE
-#define GT_PCI_IO_BASE     GT_DEF_PCI0_IO_BASE
+#define GT_PCI_IO_BASE     (0x20000000)
 #define GT_PCI_IO_SIZE     GT_DEF_PCI0_IO_SIZE
 
-#define GT64120_BASE       (KSEG1ADDR(GT_DEF_BASE))
+extern unsigned long gt64120_base;
+
+#define GT64120_BASE       (gt64120_base)
 
 /*
  * Because of an error/peculiarity in the Galileo chip, we need to swap the
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 76da1b3aa..f45669442 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -72,6 +72,12 @@
 #define CP0_IWATCH $18
 #define CP0_DWATCH $19
 
+/* 
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+
 /*
  * Coprocessor 1 (FPU) register names
  */
@@ -165,6 +171,16 @@
         : "=r" (__res));                                        \
         __res;})
 
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+        __asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+        "cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+        : "=r" (__res));                                        \
+        __res;})
+
 /*
  * For now use this only with interrupts disabled!
  */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 6b4ebcbc3..605d48080 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -59,6 +59,16 @@ extern void (*_flush_icache_page)(struct vm_area_struct *vma,
 extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 			       unsigned long entryhi, unsigned long pagemask);
 
+/*
+ * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
+ *	starting at the top and working down. This is for populating the
+ *	TLB before trap_init() puts the TLB miss handler in place. It 
+ *	should be used only for entries matching the actual page tables,
+ *	to prevent inconsistencies.
+ */
+extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
+			       unsigned long entryhi, unsigned long pagemask);
+
 
 /* Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 6d5634aa3..6c33daa38 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -234,7 +234,7 @@
 #define OCELOT_BASE_BAUD ( 20000000 / 16 )
 
 #define OCELOT_SERIAL1_IRQ	4
-#define OCELOT_SERIAL1_BASE	0xbd000020
+#define OCELOT_SERIAL1_BASE	0xe0001020
 
 #define _OCELOT_SERIAL_INIT(int, base)					\
 	{ baud_base: OCELOT_BASE_BAUD, irq: int, flags: STD_COM_FLAGS,	\
-- 
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