From 1d793fade8b063fde3cf275bf1a5c2d381292cd9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 24 Aug 1998 17:24:11 +0000 Subject: CVS !@#%$@$#%$ ... --- include/asm-alpha/apecs.h | 573 ------------------------------------- include/asm-alpha/bitops.h | 71 ++++- include/asm-alpha/byteorder.h | 6 +- include/asm-alpha/cia.h | 591 -------------------------------------- include/asm-alpha/compiler.h | 74 +++++ include/asm-alpha/core_apecs.h | 627 +++++++++++++++++++++++++++++++++++++++++ include/asm-alpha/core_cia.h | 601 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 1365 insertions(+), 1178 deletions(-) delete mode 100644 include/asm-alpha/apecs.h delete mode 100644 include/asm-alpha/cia.h create mode 100644 include/asm-alpha/compiler.h create mode 100644 include/asm-alpha/core_apecs.h create mode 100644 include/asm-alpha/core_cia.h (limited to 'include') diff --git a/include/asm-alpha/apecs.h b/include/asm-alpha/apecs.h deleted file mode 100644 index 36ac35922..000000000 --- a/include/asm-alpha/apecs.h +++ /dev/null @@ -1,573 +0,0 @@ -#ifndef __ALPHA_APECS__H__ -#define __ALPHA_APECS__H__ - -#include - -/* - * APECS is the internal name for the 2107x chipset which provides - * memory controller and PCI access for the 21064 chip based systems. - * - * This file is based on: - * - * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets - * Data Sheet - * - * EC-N0648-72 - * - * - * david.rusling@reo.mts.dec.com Initial Version. - * - */ -#include - -#ifdef CONFIG_ALPHA_XL -/* - An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address - that get passed through the PCI<->ISA bridge chip. So we've gotta use - both windows to max out the physical memory we can DMA to. Sigh... - - If we try a window at 0 for 1GB as a work-around, we run into conflicts - with ISA/PCI bus memory which can't be relocated, like VGA aperture and - BIOS ROMs. So we must put the windows high enough to avoid these areas. - - We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, - and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. - Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually - be used for that range (via virt_to_bus()). - - Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb, - to keep virt_to_bus() from returning an address in the first window, for - a data area that goes beyond the 64Mb first DMA window. Sigh... - The fudge factor MUST match with MAX_DMA_ADDRESS, but - we can't just use that here, because of header file looping... :-( - - Window 1 will be used for all DMA from the ISA bus; yes, that does - limit what memory an ISA floppy or soundcard or Ethernet can touch, but - it's also a known limitation on other platforms as well. We use the - same technique that is used on INTEL platforms with similar limitation: - set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init(). - We trust that any ISA bus device drivers will *always* ask for DMAable - memory explicitly via kmalloc()/get_free_pages() flags arguments. - - Note that most PCI bus devices' drivers do *not* explicitly ask for - DMAable memory; they count on being able to DMA to any memory they - get from kmalloc()/get_free_pages(). They will also use window 1 for - any physical memory accesses below 64Mb; the rest will be handled by - window 2, maxing out at 1Gb of memory. I trust this is enough... :-) - - We hope that the area before the first window is large enough so that - there will be no overlap at the top end (64Mb). We *must* locate the - PCI cards' memory just below window 1, so that there's still the - possibility of being able to access it via SPARSE space. This is - important for cards such as the Matrox Millennium, whose Xserver - wants to access memory-mapped registers in byte and short lengths. - - Note that the XL is treated differently from the AVANTI, even though - for most other things they are identical. It didn't seem reasonable to - make the AVANTI support pay for the limitations of the XL. It is true, - however, that an XL kernel will run on an AVANTI without problems. - -*/ -#define APECS_XL_DMA_WIN1_BASE (64*1024*1024) -#define APECS_XL_DMA_WIN1_SIZE (64*1024*1024) -#define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024) -#define APECS_XL_DMA_WIN2_BASE (1024*1024*1024) -#define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024) - -#else /* CONFIG_ALPHA_XL */ - -/* these are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64 */ -#ifdef CONFIG_ALPHA_SRM_SETUP -/* if we are using the SRM PCI setup, we'll need to use variables instead */ -#define APECS_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define APECS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) - -extern unsigned int APECS_DMA_WIN_BASE; -extern unsigned int APECS_DMA_WIN_SIZE; - -#else /* SRM_SETUP */ -#define APECS_DMA_WIN_BASE (1024*1024*1024) -#define APECS_DMA_WIN_SIZE (1024*1024*1024) -#endif /* SRM_SETUP */ - -#endif /* CONFIG_ALPHA_XL */ - -/* - * 21071-DA Control and Status registers. - * These are used for PCI memory access. - */ -#define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) -#define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) -#define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) -#define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) -#define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) -#define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) - -#define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) -#define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) - -#define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) -#define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) - -#define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) -#define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) - -#define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) -#define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) -#define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) - -#define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) - -#define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) -#define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) -#define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) -#define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) -#define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) -#define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) -#define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) -#define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) - -#define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) -#define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) -#define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) -#define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) -#define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) -#define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) -#define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) -#define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) - -#define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) - - -/* - * 21071-CA Control and Status registers. - * These are used to program memory timing, - * configure memory and initialise the B-Cache. - */ -#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) -#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) -#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) -#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) -#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) -#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) -#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) -#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) -#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) -#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) -#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) -#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) -#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) - -/* Bank x Base Address Register */ -#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) -#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) -#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) -#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) -#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) -#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) -#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) -#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) -#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) - -/* Bank x Configuration Register */ -#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) -#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) -#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) -#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) -#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) -#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) -#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) -#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) -#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) - -/* Bank x Timing Register A */ -#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) -#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) -#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) -#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) -#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) -#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) -#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) -#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) -#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) - -/* Bank x Timing Register B */ -#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) -#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) -#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) -#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) -#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) -#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) -#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) -#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) -#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) - - -/* - * Memory spaces: - */ -#define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) -#define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) -#define APECS_IO (IDENT_ADDR + 0x1c0000000UL) -#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) -#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) - -/* - * Bit definitions for I/O Controller status register 0: - */ -#define APECS_IOC_STAT0_CMD 0xf -#define APECS_IOC_STAT0_ERR (1<<4) -#define APECS_IOC_STAT0_LOST (1<<5) -#define APECS_IOC_STAT0_THIT (1<<6) -#define APECS_IOC_STAT0_TREF (1<<7) -#define APECS_IOC_STAT0_CODE_SHIFT 8 -#define APECS_IOC_STAT0_CODE_MASK 0x7 -#define APECS_IOC_STAT0_P_NBR_SHIFT 13 -#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff - -#define HAE_ADDRESS APECS_IOC_HAXR1 - -#ifdef __KERNEL__ - -/* - * Translate physical memory address as seen on (PCI) bus into - * a kernel virtual address and vv. - */ -/* NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent - virt_to_bus() from returning an address in the first window, for a - data area that goes beyond the 64Mb first DMA window. Sigh... - This MUST match with MAX_DMA_ADDRESS for consistency, but - we can't just use that here, because of header file looping... :-( -*/ -extern inline unsigned long virt_to_bus(void * address) -{ - unsigned long paddr = virt_to_phys(address); -#ifdef CONFIG_ALPHA_XL - if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID) - return paddr + APECS_XL_DMA_WIN1_BASE; - else - return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */ -#else /* CONFIG_ALPHA_XL */ - return paddr + APECS_DMA_WIN_BASE; -#endif /* CONFIG_ALPHA_XL */ -} - -extern inline void * bus_to_virt(unsigned long address) -{ - /* - * This check is a sanity check but also ensures that bus - * address 0 maps to virtual address 0 which is useful to - * detect null "pointers" (the NCR driver is much simpler if - * NULL pointers are preserved). - */ -#ifdef CONFIG_ALPHA_XL - if (address < APECS_XL_DMA_WIN1_BASE) - return 0; - else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE)) - return phys_to_virt(address - APECS_XL_DMA_WIN1_BASE); - else /* should be more checking here, maybe? */ - return phys_to_virt(address - APECS_XL_DMA_WIN2_BASE); -#else /* CONFIG_ALPHA_XL */ - if (address < APECS_DMA_WIN_BASE) - return 0; - return phys_to_virt(address - APECS_DMA_WIN_BASE); -#endif /* CONFIG_ALPHA_XL */ -} - -/* - * I/O functions: - * - * Unlike Jensen, the APECS machines have no concept of local - * I/O---everything goes over the PCI bus. - * - * There is plenty room for optimization here. In particular, - * the Alpha's insb/insw/extb/extw should be useful in moving - * data to/from the right byte-lanes. - */ - -#define vuip volatile unsigned int * - -extern inline unsigned int __inb(unsigned long addr) -{ - long result = *(vuip) ((addr << 5) + APECS_IO + 0x00); - result >>= (addr & 3) * 8; - return 0xffUL & result; -} - -extern inline void __outb(unsigned char b, unsigned long addr) -{ - unsigned int w; - - asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); - *(vuip) ((addr << 5) + APECS_IO + 0x00) = w; - mb(); -} - -extern inline unsigned int __inw(unsigned long addr) -{ - long result = *(vuip) ((addr << 5) + APECS_IO + 0x08); - result >>= (addr & 3) * 8; - return 0xffffUL & result; -} - -extern inline void __outw(unsigned short b, unsigned long addr) -{ - unsigned int w; - - asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); - *(vuip) ((addr << 5) + APECS_IO + 0x08) = w; - mb(); -} - -extern inline unsigned int __inl(unsigned long addr) -{ - return *(vuip) ((addr << 5) + APECS_IO + 0x18); -} - -extern inline void __outl(unsigned int b, unsigned long addr) -{ - *(vuip) ((addr << 5) + APECS_IO + 0x18) = b; - mb(); -} - - -/* - * Memory functions. 64-bit and 32-bit accesses are done through - * dense memory space, everything else through sparse space. - */ -extern inline unsigned long __readb(unsigned long addr) -{ - unsigned long result, shift, msb; - - shift = (addr & 0x3) * 8; - if (addr >= (1UL << 24)) { - msb = addr & 0xf8000000; - addr -= msb; - if (msb != hae.cache) { - set_hae(msb); - } - } - result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00); - result >>= shift; - return 0xffUL & result; -} - -extern inline unsigned long __readw(unsigned long addr) -{ - unsigned long result, shift, msb; - - shift = (addr & 0x3) * 8; - if (addr >= (1UL << 24)) { - msb = addr & 0xf8000000; - addr -= msb; - if (msb != hae.cache) { - set_hae(msb); - } - } - result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08); - result >>= shift; - return 0xffffUL & result; -} - -extern inline unsigned long __readl(unsigned long addr) -{ - return *(vuip) (addr + APECS_DENSE_MEM); -} - -extern inline void __writeb(unsigned char b, unsigned long addr) -{ - unsigned long msb; - - if (addr >= (1UL << 24)) { - msb = addr & 0xf8000000; - addr -= msb; - if (msb != hae.cache) { - set_hae(msb); - } - } - *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101; -} - -extern inline void __writew(unsigned short b, unsigned long addr) -{ - unsigned long msb; - - if (addr >= (1UL << 24)) { - msb = addr & 0xf8000000; - addr -= msb; - if (msb != hae.cache) { - set_hae(msb); - } - } - *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001; -} - -extern inline void __writel(unsigned int b, unsigned long addr) -{ - *(vuip) (addr + APECS_DENSE_MEM) = b; -} - -#define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) - -#define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) - -#define readl(a) __readl((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) - -#undef vuip - -extern unsigned long apecs_init (unsigned long mem_start, - unsigned long mem_end); - -#endif /* __KERNEL__ */ - -/* - * Data structure for handling APECS machine checks: - */ -#ifdef CONFIG_ALPHA_MIKASA -struct el_apecs_sysdata_mcheck { - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_base3; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long coma_cnfg3; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; - - unsigned long pceb_vid; - unsigned long pceb_did; - unsigned long pceb_revision; - unsigned long pceb_command; - unsigned long pceb_status; - unsigned long pceb_latency; - unsigned long pceb_control; - unsigned long pceb_arbcon; - unsigned long pceb_arbpri; - - unsigned long esc_id; - unsigned long esc_revision; - unsigned long esc_int0; - unsigned long esc_int1; - unsigned long esc_elcr0; - unsigned long esc_elcr1; - unsigned long esc_last_eisa; - unsigned long esc_nmi_stat; - - unsigned long pci_ir; - unsigned long pci_imr; - unsigned long svr_mgr; -}; -#else /* CONFIG_ALPHA_MIKASA */ -/* this for the normal APECS machines */ -struct el_apecs_sysdata_mcheck { - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; -}; -#endif /* CONFIG_ALPHA_MIKASA */ - -struct el_procdata { - unsigned long paltemp[32]; /* PAL TEMP REGS. */ - /* EV4-specific fields */ - unsigned long exc_addr; /* Address of excepting instruction. */ - unsigned long exc_sum; /* Summary of arithmetic traps. */ - unsigned long exc_mask; /* Exception mask (from exc_sum). */ - unsigned long iccsr; /* IBox hardware enables. */ - unsigned long pal_base; /* Base address for PALcode. */ - unsigned long hier; /* Hardware Interrupt Enable. */ - unsigned long hirr; /* Hardware Interrupt Request. */ - unsigned long csr; /* D-stream fault info. */ - unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */ - unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ - unsigned long abox_ctl; /* ABox Control Register. */ - unsigned long biu_stat; /* BIU Status. */ - unsigned long biu_addr; /* BUI Address. */ - unsigned long biu_ctl; /* BIU Control. */ - unsigned long fill_syndrome;/* For correcting ECC errors. */ - unsigned long fill_addr; /* Cache block which was being read */ - unsigned long va; /* Effective VA of fault or miss. */ - unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/ -}; - - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ADDR(x) (0x80 | (x)) -#define RTC_ALWAYS_BCD 0 - -#endif /* __ALPHA_APECS__H__ */ diff --git a/include/asm-alpha/bitops.h b/include/asm-alpha/bitops.h index 70c857af7..140f5783a 100644 --- a/include/asm-alpha/bitops.h +++ b/include/asm-alpha/bitops.h @@ -46,10 +46,10 @@ extern __inline__ void clear_bit(unsigned long nr, volatile void * addr) __asm__ __volatile__( "1: ldl_l %0,%1\n" - " and %0,%3,%2\n\t" - " beq %2,2f\n\t" - " xor %0,%3,%0\n\t" - " stl_c %0,%1\n\t" + " and %0,%3,%2\n" + " beq %2,2f\n" + " xor %0,%3,%0\n" + " stl_c %0,%1\n" " beq %0,3f\n" "2:\n" ".section .text2,\"ax\"\n" @@ -66,8 +66,8 @@ extern __inline__ void change_bit(unsigned long nr, volatile void * addr) __asm__ __volatile__( "1: ldl_l %0,%1\n" - " xor %0,%2,%0\n\t" - " stl_c %0,%1\n\t" + " xor %0,%2,%0\n" + " stl_c %0,%1\n" " beq %0,3f\n" ".section .text2,\"ax\"\n" "3: br 1b\n" @@ -109,10 +109,10 @@ extern __inline__ unsigned long test_and_clear_bit(unsigned long nr, __asm__ __volatile__( "1: ldl_l %0,%1\n" - " and %0,%3,%2\n\t" - " beq %2,2f\n\t" - " xor %0,%3,%0\n\t" - " stl_c %0,%1\n\t" + " and %0,%3,%2\n" + " beq %2,2f\n" + " xor %0,%3,%0\n" + " stl_c %0,%1\n" " beq %0,3f\n" "2:\n" ".section .text2,\"ax\"\n" @@ -133,9 +133,9 @@ extern __inline__ unsigned long test_and_change_bit(unsigned long nr, __asm__ __volatile__( "1: ldl_l %0,%1\n" - " and %0,%3,%2\n\t" - " xor %0,%3,%0\n\t" - " stl_c %0,%1\n\t" + " and %0,%3,%2\n" + " xor %0,%3,%0\n" + " stl_c %0,%1\n" " beq %0,3f\n" ".section .text2,\"ax\"\n" "3: br 1b\n" @@ -172,6 +172,11 @@ extern inline unsigned long ffz_b(unsigned long x) extern inline unsigned long ffz(unsigned long word) { +#ifdef __alpha_cix__ + /* Whee. EV6 can calculate it directly. */ + unsigned long result; + __asm__("ctlz %1,%0" : "=r"(result) : "r"(~word)); +#else unsigned long bits, qofs, bofs; __asm__("cmpbge %1,%2,%0" : "=r"(bits) : "r"(word), "r"(~0UL)); @@ -180,8 +185,48 @@ extern inline unsigned long ffz(unsigned long word) bofs = ffz_b(bits); return qofs*8 + bofs; +#endif } +#ifdef __KERNEL__ + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +extern inline int ffs(int word) +{ + int result = ffz(~word); + return word ? result+1 : 0; +} + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#ifdef __alpha_cix__ +/* Whee. EV6 can calculate it directly. */ +extern __inline__ unsigned long hweight64(unsigned long w) +{ + unsigned long result; + __asm__("ctpop %1,%0" : "=r"(result) : "r"(w)); + return result; +} + +#define hweight32(x) hweight64((x) & 0xfffffffful) +#define hweight16(x) hweight64((x) & 0xfffful) +#define hweight8(x) hweight64((x) & 0xfful) +#else +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) +#endif + +#endif /* __KERNEL__ */ + /* * Find next zero bit in a bitmap reasonably efficiently.. */ diff --git a/include/asm-alpha/byteorder.h b/include/asm-alpha/byteorder.h index b8afddcd5..e574bb6e7 100644 --- a/include/asm-alpha/byteorder.h +++ b/include/asm-alpha/byteorder.h @@ -3,7 +3,11 @@ #include -#ifdef __GNUC__ +/* EGCS 1.1 can, without scheduling, do just as good as we do here + with the standard macros. And since it can schedule, it does even + better in the end. */ + +#if defined(__GNUC__) && __GNUC_MINOR__ < 91 static __inline__ __const__ __u32 ___arch__swab32(__u32 x) { diff --git a/include/asm-alpha/cia.h b/include/asm-alpha/cia.h deleted file mode 100644 index 38269eaae..000000000 --- a/include/asm-alpha/cia.h +++ /dev/null @@ -1,591 +0,0 @@ -#ifndef __ALPHA_CIA__H__ -#define __ALPHA_CIA__H__ - -#include -#include - -/* - * CIA is the internal name for the 2117x chipset which provides - * memory controller and PCI access for the 21164 chip based systems. - * - * This file is based on: - * - * DECchip 21171 Core Logic Chipset - * Technical Reference Manual - * - * EC-QE18B-TE - * - * david.rusling@reo.mts.dec.com Initial Version. - * - */ - -/*------------------------------------------------------------------------** -** ** -** EB164 I/O procedures ** -** ** -** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** -** inportbxt: 8 bits only ** -** inport: alias of inportw ** -** outport: alias of outportw ** -** ** -** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** -** inmembxt: 8 bits only ** -** inmem: alias of inmemw ** -** outmem: alias of outmemw ** -** ** -**------------------------------------------------------------------------*/ - - -/* CIA ADDRESS BIT DEFINITIONS - * - * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | \_/ \_/ - * | | | - * +-- IO space, not cached. Byte Enable --+ | - * Transfer Length --+ - * - * - * - * Byte Transfer - * Enable Length Transfer Byte Address - * adr<6:5> adr<4:3> Length Enable Adder - * --------------------------------------------- - * 00 00 Byte 1110 0x000 - * 01 00 Byte 1101 0x020 - * 10 00 Byte 1011 0x040 - * 11 00 Byte 0111 0x060 - * - * 00 01 Word 1100 0x008 - * 01 01 Word 1001 0x028 <= Not supported in this code. - * 10 01 Word 0011 0x048 - * - * 00 10 Tribyte 1000 0x010 - * 01 10 Tribyte 0001 0x030 - * - * 10 11 Longword 0000 0x058 - * - * Note that byte enables are asserted low. - * - */ - -#define BYTE_ENABLE_SHIFT 5 -#define TRANSFER_LENGTH_SHIFT 3 - -#define MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */ -#define MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ -#define MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ - -#ifdef CONFIG_ALPHA_SRM_SETUP -/* if we are using the SRM PCI setup, we'll need to use variables instead */ -#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024) -#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) - -extern unsigned int CIA_DMA_WIN_BASE; -extern unsigned int CIA_DMA_WIN_SIZE; - -#else /* SRM_SETUP */ -#define CIA_DMA_WIN_BASE (1024*1024*1024) -#define CIA_DMA_WIN_SIZE (1024*1024*1024) -#endif /* SRM_SETUP */ - -/* - * 21171-CA Control and Status Registers (p4-1) - */ -#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL) -#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) -#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL) -#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL) -#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL) -#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL) -#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL) -#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL) - -/* - * 21171-CA Diagnostic Registers (p4-2) - */ -#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL) -#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) - -/* - * 21171-CA Performance Monitor registers (p4-3) - */ -#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) -#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) - -/* - * 21171-CA Error registers (p4-3) - */ -#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL) -#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL) -#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL) -#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL) -#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL) -#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL) -#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL) -#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL) -#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) -#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) -#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL) - -/* - * 2117A-CA PCI Address Translation Registers. - */ -#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL) - -#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL) -#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL) -#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL) - -#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL) -#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL) -#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL) - -#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL) -#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL) -#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL) - -#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL) -#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL) -#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL) - -/* - * 21171-CA System configuration registers (p4-3) - */ -#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL) -#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL) -#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL) -#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL) -#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL) -#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL) -#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL) -#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL) -#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL) -#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL) -#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL) -#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL) - -/* - * Memory spaces: - */ -#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL) -#define CIA_CONF (IDENT_ADDR + 0x8700000000UL) -#define CIA_IO (IDENT_ADDR + 0x8580000000UL) -#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) -#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL) -#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL) -#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) - -/* - * ALCOR's GRU ASIC registers - */ -#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL) -#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL) -#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL) -#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL) -#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL) - -#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL) -#define GRU_SCR (IDENT_ADDR + 0x8780000300UL) -#define GRU_LED (IDENT_ADDR + 0x8780000800UL) -#define GRU_RESET (IDENT_ADDR + 0x8780000900UL) - -#if defined(CONFIG_ALPHA_ALCOR) -#define GRU_INT_REQ_BITS 0x800fffffUL -#elif defined(CONFIG_ALPHA_XLT) -#define GRU_INT_REQ_BITS 0x80003fffUL -#else -#define GRU_INT_REQ_BITS 0xffffffffUL -#endif - -/* - * Bit definitions for I/O Controller status register 0: - */ -#define CIA_IOC_STAT0_CMD 0xf -#define CIA_IOC_STAT0_ERR (1<<4) -#define CIA_IOC_STAT0_LOST (1<<5) -#define CIA_IOC_STAT0_THIT (1<<6) -#define CIA_IOC_STAT0_TREF (1<<7) -#define CIA_IOC_STAT0_CODE_SHIFT 8 -#define CIA_IOC_STAT0_CODE_MASK 0x7 -#define CIA_IOC_STAT0_P_NBR_SHIFT 13 -#define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff - -#define HAE_ADDRESS CIA_IOC_HAE_MEM - -#ifdef __KERNEL__ - -/* - * Translate physical memory address as seen on (PCI) bus into - * a kernel virtual address and vv. - */ -extern inline unsigned long virt_to_bus(void * address) -{ - return virt_to_phys(address) + CIA_DMA_WIN_BASE; -} - -extern inline void * bus_to_virt(unsigned long address) -{ - return phys_to_virt(address - CIA_DMA_WIN_BASE); -} - -/* - * I/O functions: - * - * CIA (the 2117x PCI/memory support chipset for the EV5 (21164) - * series of processors uses a sparse address mapping scheme to - * get at PCI memory and I/O. - */ - -#define vuip volatile unsigned int * - -extern inline unsigned int __inb(unsigned long addr) -{ - long result = *(vuip) ((addr << 5) + CIA_IO + 0x00); - result >>= (addr & 3) * 8; - return 0xffUL & result; -} - -extern inline void __outb(unsigned char b, unsigned long addr) -{ - unsigned int w; - - asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); - *(vuip) ((addr << 5) + CIA_IO + 0x00) = w; - mb(); -} - -extern inline unsigned int __inw(unsigned long addr) -{ - long result = *(vuip) ((addr << 5) + CIA_IO + 0x08); - result >>= (addr & 3) * 8; - return 0xffffUL & result; -} - -extern inline void __outw(unsigned short b, unsigned long addr) -{ - unsigned int w; - - asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b)); - *(vuip) ((addr << 5) + CIA_IO + 0x08) = w; - mb(); -} - -extern inline unsigned int __inl(unsigned long addr) -{ - return *(vuip) ((addr << 5) + CIA_IO + 0x18); -} - -extern inline void __outl(unsigned int b, unsigned long addr) -{ - *(vuip) ((addr << 5) + CIA_IO + 0x18) = b; - mb(); -} - - -/* - * Memory functions. 64-bit and 32-bit accesses are done through - * dense memory space, everything else through sparse space. - * - * For reading and writing 8 and 16 bit quantities we need to - * go through one of the three sparse address mapping regions - * and use the HAE_MEM CSR to provide some bits of the address. - * The following few routines use only sparse address region 1 - * which gives 1Gbyte of accessible space which relates exactly - * to the amount of PCI memory mapping *into* system address space. - * See p 6-17 of the specification but it looks something like this: - * - * 21164 Address: - * - * 3 2 1 - * 9876543210987654321098765432109876543210 - * 1ZZZZ0.PCI.QW.Address............BBLL - * - * ZZ = SBZ - * BB = Byte offset - * LL = Transfer length - * - * PCI Address: - * - * 3 2 1 - * 10987654321098765432109876543210 - * HHH....PCI.QW.Address........ 00 - * - * HHH = 31:29 HAE_MEM CSR - * - */ - -#ifdef CONFIG_ALPHA_SRM_SETUP - -extern unsigned long cia_sm_base_r1, cia_sm_base_r2, cia_sm_base_r3; - -extern inline unsigned long __readb(unsigned long addr) -{ - unsigned long result, shift, work; - - if ((addr >= cia_sm_base_r1) && - (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) - work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); - else - if ((addr >= cia_sm_base_r2) && - (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) - work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); - else - if ((addr >= cia_sm_base_r3) && - (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) - work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); - else - { -#if 0 - printk("__readb: address 0x%lx not covered by HAE\n", addr); -#endif - return 0x0ffUL; - } - shift = (addr & 0x3) << 3; - result = *(vuip) work; - result >>= shift; - return 0x0ffUL & result; -} - -extern inline unsigned long __readw(unsigned long addr) -{ - unsigned long result, shift, work; - - if ((addr >= cia_sm_base_r1) && - (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) - work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x08); - else - if ((addr >= cia_sm_base_r2) && - (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) - work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x08); - else - if ((addr >= cia_sm_base_r3) && - (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) - work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x08); - else - { -#if 0 - printk("__readw: address 0x%lx not covered by HAE\n", addr); -#endif - return 0x0ffffUL; - } - shift = (addr & 0x3) << 3; - result = *(vuip) work; - result >>= shift; - return 0x0ffffUL & result; -} - -extern inline void __writeb(unsigned char b, unsigned long addr) -{ - unsigned long work; - - if ((addr >= cia_sm_base_r1) && - (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) - work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); - else - if ((addr >= cia_sm_base_r2) && - (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) - work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); - else - if ((addr >= cia_sm_base_r3) && - (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) - work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); - else - { -#if 0 - printk("__writeb: address 0x%lx not covered by HAE\n", addr); -#endif - return; - } - *(vuip) work = b * 0x01010101; -} - -extern inline void __writew(unsigned short b, unsigned long addr) -{ - unsigned long work; - - if ((addr >= cia_sm_base_r1) && - (addr <= (cia_sm_base_r1 + MEM_R1_MASK))) - work = (((addr & MEM_R1_MASK) << 5) + CIA_SPARSE_MEM + 0x00); - else - if ((addr >= cia_sm_base_r2) && - (addr <= (cia_sm_base_r2 + MEM_R2_MASK))) - work = (((addr & MEM_R2_MASK) << 5) + CIA_SPARSE_MEM_R2 + 0x00); - else - if ((addr >= cia_sm_base_r3) && - (addr <= (cia_sm_base_r3 + MEM_R3_MASK))) - work = (((addr & MEM_R3_MASK) << 5) + CIA_SPARSE_MEM_R3 + 0x00); - else - { -#if 0 - printk("__writew: address 0x%lx not covered by HAE\n", addr); -#endif - return; - } - *(vuip) work = b * 0x00010001; -} - -#else /* SRM_SETUP */ - -extern inline unsigned long __readb(unsigned long addr) -{ - unsigned long result, shift, msb; - - shift = (addr & 0x3) * 8 ; - msb = addr & 0xE0000000 ; - addr &= MEM_R1_MASK ; - if (msb != hae.cache) { - set_hae(msb); - } - result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) ; - result >>= shift; - return 0xffUL & result; -} - -extern inline unsigned long __readw(unsigned long addr) -{ - unsigned long result, shift, msb; - - shift = (addr & 0x3) * 8; - msb = addr & 0xE0000000 ; - addr &= MEM_R1_MASK ; - if (msb != hae.cache) { - set_hae(msb); - } - result = *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08); - result >>= shift; - return 0xffffUL & result; -} - -extern inline void __writeb(unsigned char b, unsigned long addr) -{ - unsigned long msb ; - - msb = addr & 0xE0000000 ; - addr &= MEM_R1_MASK ; - if (msb != hae.cache) { - set_hae(msb); - } - *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = b * 0x01010101; -} - -extern inline void __writew(unsigned short b, unsigned long addr) -{ - unsigned long msb ; - - msb = addr & 0xE0000000 ; - addr &= MEM_R1_MASK ; - if (msb != hae.cache) { - set_hae(msb); - } - *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = b * 0x00010001; -} - -#endif /* SRM_SETUP */ - -extern inline unsigned long __readl(unsigned long addr) -{ - return *(vuip) (addr + CIA_DENSE_MEM); -} - -extern inline void __writel(unsigned int b, unsigned long addr) -{ - *(vuip) (addr + CIA_DENSE_MEM) = b; -} - -#define inb(port) \ -(__builtin_constant_p((port))?__inb(port):_inb(port)) - -#define outb(x, port) \ -(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) - -#define readl(a) __readl((unsigned long)(a)) -#define writel(v,a) __writel((v),(unsigned long)(a)) - -#undef vuip - -extern unsigned long cia_init (unsigned long mem_start, - unsigned long mem_end); - -#endif /* __KERNEL__ */ - -/* - * Data structure for handling CIA machine checks: - */ -/* ev5-specific info: */ -struct el_procdata { - unsigned long shadow[8]; /* PALmode shadow registers */ - unsigned long paltemp[24]; /* PAL temporary registers */ - /* EV5-specific fields */ - unsigned long exc_addr; /* Address of excepting instruction. */ - unsigned long exc_sum; /* Summary of arithmetic traps. */ - unsigned long exc_mask; /* Exception mask (from exc_sum). */ - unsigned long exc_base; /* PALbase at time of exception. */ - unsigned long isr; /* Interrupt summary register. */ - unsigned long icsr; /* Ibox control register. */ - unsigned long ic_perr_stat; - unsigned long dc_perr_stat; - unsigned long va; /* Effective VA of fault or miss. */ - unsigned long mm_stat; - unsigned long sc_addr; - unsigned long sc_stat; - unsigned long bc_tag_addr; - unsigned long ei_addr; - unsigned long fill_syn; - unsigned long ei_stat; - unsigned long ld_lock; -}; - -/* system-specific info: */ -struct el_CIA_sysdata_mcheck { - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; -}; - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ADDR(x) (0x80 | (x)) -#define RTC_ALWAYS_BCD 0 - -#endif /* __ALPHA_CIA__H__ */ diff --git a/include/asm-alpha/compiler.h b/include/asm-alpha/compiler.h new file mode 100644 index 000000000..5656ce953 --- /dev/null +++ b/include/asm-alpha/compiler.h @@ -0,0 +1,74 @@ +#ifndef __ALPHA_COMPILER_H +#define __ALPHA_COMPILER_H + +/* + * Herein are macros we use when describing various patterns we want to GCC. + * In all cases we can get better schedules out of the compiler if we hide + * as little as possible inside inline assembly. However, we want to be + * able to know what we'll get out before giving up inline assembly. Thus + * these tests and macros. + */ + +/* + * EGCS (of varying versions) does a good job of using insxl and extxl. + */ + +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 +#define __kernel_insbl(val, shift) \ + (((unsigned long)(val) & 0xfful) << ((shift) * 8)) +#define __kernel_inswl(val, shift) \ + (((unsigned long)(val) & 0xfffful) << ((shift) * 8)) +#else +#define __kernel_insbl(val, shift) \ + ({ unsigned long __kir; \ + __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ + __kir; }) +#define __kernel_inswl(val, shift) \ + ({ unsigned long __kir; \ + __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ + __kir; }) +#endif + +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 92 +#define __kernel_extbl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfful) +#define __kernel_extwl(val, shift) (((val) >> (((shift) & 7) * 8)) & 0xfffful) +#else +#define __kernel_extbl(val, shift) \ + ({ unsigned long __kir; \ + __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ + __kir; }) +#define __kernel_extwl(val, shift) \ + ({ unsigned long __kir; \ + __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val)); \ + __kir; }) +#endif + + +/* + * Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX + * extension is enabled. Previous versions did not define anything + * we could test during compilation, so allow users to tell us when + * the compiler will DTRT. + */ + +#if defined(HAVE_BWX) || defined(__alpha_bwx__) +#define __kernel_ldbu(mem) (mem) +#define __kernel_ldwu(mem) (mem) +#define __kernel_stb(val,mem) ((mem) = (val)) +#define __kernel_stw(val,mem) ((mem) = (val)) +#else +#define __kernel_ldbu(mem) \ + ({ unsigned char __kir; \ + __asm__("ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \ + __kir; }) +#define __kernel_ldwu(mem) \ + ({ unsigned short __kir; \ + __asm__("ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \ + __kir; }) +#define __kernel_stb(val,mem) \ + __asm__("stb %1,%0" : "=m"(mem) : "r"(val)) +#define __kernel_stw(val,mem) \ + __asm__("stw %1,%0" : "=m"(mem) : "r"(val)) +#endif + +#endif /* __ALPHA_COMPILER_H */ diff --git a/include/asm-alpha/core_apecs.h b/include/asm-alpha/core_apecs.h new file mode 100644 index 000000000..a8f0bd6ef --- /dev/null +++ b/include/asm-alpha/core_apecs.h @@ -0,0 +1,627 @@ +#ifndef __ALPHA_APECS__H__ +#define __ALPHA_APECS__H__ + +#include +#include +#include + +/* + * APECS is the internal name for the 2107x chipset which provides + * memory controller and PCI access for the 21064 chip based systems. + * + * This file is based on: + * + * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets + * Data Sheet + * + * EC-N0648-72 + * + * + * david.rusling@reo.mts.dec.com Initial Version. + * + */ + +/* + An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address + that get passed through the PCI<->ISA bridge chip. So we've gotta use + both windows to max out the physical memory we can DMA to. Sigh... + + If we try a window at 0 for 1GB as a work-around, we run into conflicts + with ISA/PCI bus memory which can't be relocated, like VGA aperture and + BIOS ROMs. So we must put the windows high enough to avoid these areas. + + We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, + and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. + Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually + be used for that range (via virt_to_bus()). + + Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb, + to keep virt_to_bus() from returning an address in the first window, for + a data area that goes beyond the 64Mb first DMA window. Sigh... + The fudge factor MUST match with MAX_DMA_ADDRESS, but + we can't just use that here, because of header file looping... :-( + + Window 1 will be used for all DMA from the ISA bus; yes, that does + limit what memory an ISA floppy or sound card or Ethernet can touch, but + it's also a known limitation on other platforms as well. We use the + same technique that is used on INTEL platforms with similar limitation: + set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init(). + We trust that any ISA bus device drivers will *always* ask for DMAable + memory explicitly via kmalloc()/get_free_pages() flags arguments. + + Note that most PCI bus devices' drivers do *not* explicitly ask for + DMAable memory; they count on being able to DMA to any memory they + get from kmalloc()/get_free_pages(). They will also use window 1 for + any physical memory accesses below 64Mb; the rest will be handled by + window 2, maxing out at 1Gb of memory. I trust this is enough... :-) + + We hope that the area before the first window is large enough so that + there will be no overlap at the top end (64Mb). We *must* locate the + PCI cards' memory just below window 1, so that there's still the + possibility of being able to access it via SPARSE space. This is + important for cards such as the Matrox Millennium, whose Xserver + wants to access memory-mapped registers in byte and short lengths. + + Note that the XL is treated differently from the AVANTI, even though + for most other things they are identical. It didn't seem reasonable to + make the AVANTI support pay for the limitations of the XL. It is true, + however, that an XL kernel will run on an AVANTI without problems. +*/ +#define APECS_XL_DMA_WIN1_BASE (64*1024*1024) +#define APECS_XL_DMA_WIN1_SIZE (64*1024*1024) +#define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024) +#define APECS_XL_DMA_WIN2_BASE (1024*1024*1024) +#define APECS_XL_DMA_WIN2_SIZE (1024*1024*1024) + + +/* These are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64. */ + +#define APECS_DMA_WIN_BASE_DEFAULT (1024*1024*1024) +#define APECS_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) + +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) +#define APECS_DMA_WIN_BASE alpha_mv.dma_win_base +#define APECS_DMA_WIN_SIZE alpha_mv.dma_win_size +#else +#define APECS_DMA_WIN_BASE APECS_DMA_WIN_BASE_DEFAULT +#define APECS_DMA_WIN_SIZE APECS_DMA_WIN_SIZE_DEFAULT +#endif + + +/* + * 21071-DA Control and Status registers. + * These are used for PCI memory access. + */ +#define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) +#define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) +#define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) +#define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) +#define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) +#define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) + +#define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) +#define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) + +#define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) +#define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) + +#define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) +#define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) + +#define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) +#define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) +#define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) + +#define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) + +#define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) +#define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) +#define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) +#define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) +#define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) +#define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) +#define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) +#define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) + +#define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) +#define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) +#define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) +#define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) +#define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) +#define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) +#define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) +#define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) + +#define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) + + +/* + * 21071-CA Control and Status registers. + * These are used to program memory timing, + * configure memory and initialise the B-Cache. + */ +#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) +#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) +#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) +#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) +#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) +#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) +#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) +#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) +#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) +#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) +#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) +#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) +#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) + +/* Bank x Base Address Register */ +#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) +#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) +#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) +#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) +#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) +#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) +#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) +#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) +#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) + +/* Bank x Configuration Register */ +#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) +#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) +#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) +#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) +#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) +#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) +#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) +#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) +#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) + +/* Bank x Timing Register A */ +#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) +#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) +#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) +#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) +#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) +#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) +#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) +#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) +#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) + +/* Bank x Timing Register B */ +#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) +#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) +#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) +#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) +#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) +#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) +#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) +#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) +#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) + + +/* + * Memory spaces: + */ +#define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) +#define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) +#define APECS_IO (IDENT_ADDR + 0x1c0000000UL) +#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) +#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) + + +/* + * Bit definitions for I/O Controller status register 0: + */ +#define APECS_IOC_STAT0_CMD 0xf +#define APECS_IOC_STAT0_ERR (1<<4) +#define APECS_IOC_STAT0_LOST (1<<5) +#define APECS_IOC_STAT0_THIT (1<<6) +#define APECS_IOC_STAT0_TREF (1<<7) +#define APECS_IOC_STAT0_CODE_SHIFT 8 +#define APECS_IOC_STAT0_CODE_MASK 0x7 +#define APECS_IOC_STAT0_P_NBR_SHIFT 13 +#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff + +#define APECS_HAE_ADDRESS APECS_IOC_HAXR1 + + +/* + * Data structure for handling APECS machine checks: + */ + +struct el_apecs_mikasa_sysdata_mcheck +{ + unsigned long coma_gcr; + unsigned long coma_edsr; + unsigned long coma_ter; + unsigned long coma_elar; + unsigned long coma_ehar; + unsigned long coma_ldlr; + unsigned long coma_ldhr; + unsigned long coma_base0; + unsigned long coma_base1; + unsigned long coma_base2; + unsigned long coma_base3; + unsigned long coma_cnfg0; + unsigned long coma_cnfg1; + unsigned long coma_cnfg2; + unsigned long coma_cnfg3; + unsigned long epic_dcsr; + unsigned long epic_pear; + unsigned long epic_sear; + unsigned long epic_tbr1; + unsigned long epic_tbr2; + unsigned long epic_pbr1; + unsigned long epic_pbr2; + unsigned long epic_pmr1; + unsigned long epic_pmr2; + unsigned long epic_harx1; + unsigned long epic_harx2; + unsigned long epic_pmlt; + unsigned long epic_tag0; + unsigned long epic_tag1; + unsigned long epic_tag2; + unsigned long epic_tag3; + unsigned long epic_tag4; + unsigned long epic_tag5; + unsigned long epic_tag6; + unsigned long epic_tag7; + unsigned long epic_data0; + unsigned long epic_data1; + unsigned long epic_data2; + unsigned long epic_data3; + unsigned long epic_data4; + unsigned long epic_data5; + unsigned long epic_data6; + unsigned long epic_data7; + + unsigned long pceb_vid; + unsigned long pceb_did; + unsigned long pceb_revision; + unsigned long pceb_command; + unsigned long pceb_status; + unsigned long pceb_latency; + unsigned long pceb_control; + unsigned long pceb_arbcon; + unsigned long pceb_arbpri; + + unsigned long esc_id; + unsigned long esc_revision; + unsigned long esc_int0; + unsigned long esc_int1; + unsigned long esc_elcr0; + unsigned long esc_elcr1; + unsigned long esc_last_eisa; + unsigned long esc_nmi_stat; + + unsigned long pci_ir; + unsigned long pci_imr; + unsigned long svr_mgr; +}; + +/* This for the normal APECS machines. */ +struct el_apecs_sysdata_mcheck +{ + unsigned long coma_gcr; + unsigned long coma_edsr; + unsigned long coma_ter; + unsigned long coma_elar; + unsigned long coma_ehar; + unsigned long coma_ldlr; + unsigned long coma_ldhr; + unsigned long coma_base0; + unsigned long coma_base1; + unsigned long coma_base2; + unsigned long coma_cnfg0; + unsigned long coma_cnfg1; + unsigned long coma_cnfg2; + unsigned long epic_dcsr; + unsigned long epic_pear; + unsigned long epic_sear; + unsigned long epic_tbr1; + unsigned long epic_tbr2; + unsigned long epic_pbr1; + unsigned long epic_pbr2; + unsigned long epic_pmr1; + unsigned long epic_pmr2; + unsigned long epic_harx1; + unsigned long epic_harx2; + unsigned long epic_pmlt; + unsigned long epic_tag0; + unsigned long epic_tag1; + unsigned long epic_tag2; + unsigned long epic_tag3; + unsigned long epic_tag4; + unsigned long epic_tag5; + unsigned long epic_tag6; + unsigned long epic_tag7; + unsigned long epic_data0; + unsigned long epic_data1; + unsigned long epic_data2; + unsigned long epic_data3; + unsigned long epic_data4; + unsigned long epic_data5; + unsigned long epic_data6; + unsigned long epic_data7; +}; + +struct el_apecs_procdata +{ + unsigned long paltemp[32]; /* PAL TEMP REGS. */ + /* EV4-specific fields */ + unsigned long exc_addr; /* Address of excepting instruction. */ + unsigned long exc_sum; /* Summary of arithmetic traps. */ + unsigned long exc_mask; /* Exception mask (from exc_sum). */ + unsigned long iccsr; /* IBox hardware enables. */ + unsigned long pal_base; /* Base address for PALcode. */ + unsigned long hier; /* Hardware Interrupt Enable. */ + unsigned long hirr; /* Hardware Interrupt Request. */ + unsigned long csr; /* D-stream fault info. */ + unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */ + unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ + unsigned long abox_ctl; /* ABox Control Register. */ + unsigned long biu_stat; /* BIU Status. */ + unsigned long biu_addr; /* BUI Address. */ + unsigned long biu_ctl; /* BIU Control. */ + unsigned long fill_syndrome;/* For correcting ECC errors. */ + unsigned long fill_addr; /* Cache block which was being read */ + unsigned long va; /* Effective VA of fault or miss. */ + unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/ +}; + + +#ifdef __KERNEL__ + +#ifndef __EXTERN_INLINE +#define __EXTERN_INLINE extern inline +#define __IO_EXTERN_INLINE +#endif + +/* + * Translate physical memory address as seen on (PCI) bus into + * a kernel virtual address and vv. + */ + +/* + * NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent + * virt_to_bus() from returning an address in the first window, for a + * data area that goes beyond the 64Mb first DMA window. Sigh... + * This MUST match with MAX_DMA_ADDRESS for consistency, but + * we can't just use that here, because of header file looping... :-( + */ + +__EXTERN_INLINE unsigned long apecs_virt_to_bus(void * address) +{ + unsigned long paddr = virt_to_phys(address); + return paddr + APECS_DMA_WIN_BASE; +} + +static inline unsigned long apecs_xl_virt_to_bus(void * address) +{ + unsigned long paddr = virt_to_phys(address); + if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID) + return paddr + APECS_XL_DMA_WIN1_BASE; + else + return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */ +} + +__EXTERN_INLINE void * apecs_bus_to_virt(unsigned long address) +{ + /* + * This check is a sanity check but also ensures that bus + * address 0 maps to virtual address 0 which is useful to + * detect null "pointers" (the NCR driver is much simpler if + * NULL pointers are preserved). + */ + if (address < APECS_DMA_WIN_BASE) + return 0; + return phys_to_virt(address - APECS_DMA_WIN_BASE); +} + +static inline void * apecs_xl_bus_to_virt(unsigned long address) +{ + /* + * This check is a sanity check but also ensures that bus + * address 0 maps to virtual address 0 which is useful to + * detect null "pointers" (the NCR driver is much simpler if + * NULL pointers are preserved). + */ + if (address < APECS_XL_DMA_WIN1_BASE) + return 0; + else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE)) + address -= APECS_XL_DMA_WIN1_BASE; + else /* should be more checking here, maybe? */ + address -= APECS_XL_DMA_WIN2_BASE; + return phys_to_virt(address); +} + +/* + * I/O functions: + * + * Unlike Jensen, the APECS machines have no concept of local + * I/O---everything goes over the PCI bus. + * + * There is plenty room for optimization here. In particular, + * the Alpha's insb/insw/extb/extw should be useful in moving + * data to/from the right byte-lanes. + */ + +#define vip volatile int * +#define vuip volatile unsigned int * +#define vulp volatile unsigned long * + +__EXTERN_INLINE unsigned int apecs_inb(unsigned long addr) +{ + long result = *(vip) ((addr << 5) + APECS_IO + 0x00); + return __kernel_extbl(result, addr & 3); +} + +__EXTERN_INLINE void apecs_outb(unsigned char b, unsigned long addr) +{ + unsigned int w; + + w = __kernel_insbl(b, addr & 3); + *(vuip) ((addr << 5) + APECS_IO + 0x00) = w; + mb(); +} + +__EXTERN_INLINE unsigned int apecs_inw(unsigned long addr) +{ + long result = *(vip) ((addr << 5) + APECS_IO + 0x08); + return __kernel_extwl(result, addr & 3); +} + +__EXTERN_INLINE void apecs_outw(unsigned short b, unsigned long addr) +{ + unsigned int w; + + w = __kernel_inswl(b, addr & 3); + *(vuip) ((addr << 5) + APECS_IO + 0x08) = w; + mb(); +} + +__EXTERN_INLINE unsigned int apecs_inl(unsigned long addr) +{ + return *(vuip) ((addr << 5) + APECS_IO + 0x18); +} + +__EXTERN_INLINE void apecs_outl(unsigned int b, unsigned long addr) +{ + *(vuip) ((addr << 5) + APECS_IO + 0x18) = b; + mb(); +} + + +/* + * Memory functions. 64-bit and 32-bit accesses are done through + * dense memory space, everything else through sparse space. + */ + +__EXTERN_INLINE unsigned long apecs_readb(unsigned long addr) +{ + unsigned long result, msb; + + if (addr >= (1UL << 24)) { + msb = addr & 0xf8000000; + addr -= msb; + set_hae(msb); + } + result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x00); + return __kernel_extbl(result, addr & 3); +} + +__EXTERN_INLINE unsigned long apecs_readw(unsigned long addr) +{ + unsigned long result, msb; + + if (addr >= (1UL << 24)) { + msb = addr & 0xf8000000; + addr -= msb; + set_hae(msb); + } + result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x08); + return __kernel_extwl(result, addr & 3); +} + +__EXTERN_INLINE unsigned long apecs_readl(unsigned long addr) +{ + return *(vuip) (addr + APECS_DENSE_MEM); +} + +__EXTERN_INLINE unsigned long apecs_readq(unsigned long addr) +{ + return *(vulp) (addr + APECS_DENSE_MEM); +} + +__EXTERN_INLINE void apecs_writeb(unsigned char b, unsigned long addr) +{ + unsigned long msb; + + if (addr >= (1UL << 24)) { + msb = addr & 0xf8000000; + addr -= msb; + set_hae(msb); + } + *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101; +} + +__EXTERN_INLINE void apecs_writew(unsigned short b, unsigned long addr) +{ + unsigned long msb; + + if (addr >= (1UL << 24)) { + msb = addr & 0xf8000000; + addr -= msb; + set_hae(msb); + } + *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001; +} + +__EXTERN_INLINE void apecs_writel(unsigned int b, unsigned long addr) +{ + *(vuip) (addr + APECS_DENSE_MEM) = b; +} + +__EXTERN_INLINE void apecs_writeq(unsigned long b, unsigned long addr) +{ + *(vulp) (addr + APECS_DENSE_MEM) = b; +} + +/* Find the DENSE memory area for a given bus address. */ + +__EXTERN_INLINE unsigned long apecs_dense_mem(unsigned long addr) +{ + return APECS_DENSE_MEM; +} + +#undef vip +#undef vuip +#undef vulp + +#ifdef __WANT_IO_DEF + +#ifdef CONFIG_ALPHA_XL +#define virt_to_bus apecs_xl_virt_to_bus +#define bus_to_virt apecs_xl_bus_to_virt +#else +#define virt_to_bus apecs_virt_to_bus +#define bus_to_virt apecs_bus_to_virt +#endif + +#define __inb apecs_inb +#define __inw apecs_inw +#define __inl apecs_inl +#define __outb apecs_outb +#define __outw apecs_outw +#define __outl apecs_outl +#define __readb apecs_readb +#define __readw apecs_readw +#define __readl apecs_readl +#define __readq apecs_readq +#define __writeb apecs_writeb +#define __writew apecs_writew +#define __writel apecs_writel +#define __writeq apecs_writeq +#define dense_mem apecs_dense_mem + +#define inb(port) \ +(__builtin_constant_p((port))?__inb(port):_inb(port)) + +#define outb(x, port) \ +(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + +#define readl(a) __readl((unsigned long)(a)) +#define readq(a) __readq((unsigned long)(a)) +#define writel(v,a) __writel((v),(unsigned long)(a)) +#define writeq(v,a) __writeq((v),(unsigned long)(a)) + +#endif /* __WANT_IO_DEF */ + +#ifdef __IO_EXTERN_INLINE +#undef __EXTERN_INLINE +#undef __IO_EXTERN_INLINE +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ALPHA_APECS__H__ */ diff --git a/include/asm-alpha/core_cia.h b/include/asm-alpha/core_cia.h new file mode 100644 index 000000000..32fd81f2e --- /dev/null +++ b/include/asm-alpha/core_cia.h @@ -0,0 +1,601 @@ +#ifndef __ALPHA_CIA__H__ +#define __ALPHA_CIA__H__ + +#include +#include +#include + +/* + * CIA is the internal name for the 2117x chipset which provides + * memory controller and PCI access for the 21164 chip based systems. + * + * This file is based on: + * + * DECchip 21171 Core Logic Chipset + * Technical Reference Manual + * + * EC-QE18B-TE + * + * david.rusling@reo.mts.dec.com Initial Version. + * + */ + +/*------------------------------------------------------------------------** +** ** +** EB164 I/O procedures ** +** ** +** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers ** +** inportbxt: 8 bits only ** +** inport: alias of inportw ** +** outport: alias of outportw ** +** ** +** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers ** +** inmembxt: 8 bits only ** +** inmem: alias of inmemw ** +** outmem: alias of outmemw ** +** ** +**------------------------------------------------------------------------*/ + + +/* CIA ADDRESS BIT DEFINITIONS + * + * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | \_/ \_/ + * | | | + * +-- IO space, not cached. Byte Enable --+ | + * Transfer Length --+ + * + * + * + * Byte Transfer + * Enable Length Transfer Byte Address + * adr<6:5> adr<4:3> Length Enable Adder + * --------------------------------------------- + * 00 00 Byte 1110 0x000 + * 01 00 Byte 1101 0x020 + * 10 00 Byte 1011 0x040 + * 11 00 Byte 0111 0x060 + * + * 00 01 Word 1100 0x008 + * 01 01 Word 1001 0x028 <= Not supported in this code. + * 10 01 Word 0011 0x048 + * + * 00 10 Tribyte 1000 0x010 + * 01 10 Tribyte 0001 0x030 + * + * 10 11 Longword 0000 0x058 + * + * Note that byte enables are asserted low. + * + */ + +#define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */ +#define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */ +#define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */ + +#define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024) +#define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024) + +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP) +#define CIA_DMA_WIN_BASE alpha_mv.dma_win_base +#define CIA_DMA_WIN_SIZE alpha_mv.dma_win_size +#else +#define CIA_DMA_WIN_BASE CIA_DMA_WIN_SIZE_DEFAULT +#define CIA_DMA_WIN_SIZE CIA_DMA_WIN_SIZE_DEFAULT +#endif + +/* + * 21171-CA Control and Status Registers (p4-1) + */ +#define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL) +#define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL) +#define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL) +#define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL) +#define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL) +#define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL) +#define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL) +#define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL) + +/* + * 21171-CA Diagnostic Registers (p4-2) + */ +#define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL) +#define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL) + +/* + * 21171-CA Performance Monitor registers (p4-3) + */ +#define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL) +#define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL) + +/* + * 21171-CA Error registers (p4-3) + */ +#define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL) +#define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL) +#define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL) +#define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL) +#define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL) +#define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL) +#define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL) +#define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL) +#define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL) +#define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL) +#define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL) + +/* + * 2117A-CA PCI Address Translation Registers. + */ +#define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL) + +#define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL) +#define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL) +#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL) + +#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL) +#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL) +#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL) + +#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL) +#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL) +#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL) + +#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL) +#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL) +#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL) + +/* + * 21171-CA System configuration registers (p4-3) + */ +#define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL) +#define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL) +#define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL) +#define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL) +#define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL) +#define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL) +#define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL) +#define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL) +#define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL) +#define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL) +#define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL) +#define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL) + +/* + * Memory spaces: + */ +#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL) +#define CIA_CONF (IDENT_ADDR + 0x8700000000UL) +#define CIA_IO (IDENT_ADDR + 0x8580000000UL) +#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL) +#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL) +#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL) +#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL) + +/* + * ALCOR's GRU ASIC registers + */ +#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL) +#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL) +#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL) +#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL) +#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL) + +#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL) +#define GRU_SCR (IDENT_ADDR + 0x8780000300UL) +#define GRU_LED (IDENT_ADDR + 0x8780000800UL) +#define GRU_RESET (IDENT_ADDR + 0x8780000900UL) + +#define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL +#define XLT_GRU_INT_REQ_BITS 0x80003fffUL +#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0) + + +/* + * Bit definitions for I/O Controller status register 0: + */ +#define CIA_IOC_STAT0_CMD 0xf +#define CIA_IOC_STAT0_ERR (1<<4) +#define CIA_IOC_STAT0_LOST (1<<5) +#define CIA_IOC_STAT0_THIT (1<<6) +#define CIA_IOC_STAT0_TREF (1<<7) +#define CIA_IOC_STAT0_CODE_SHIFT 8 +#define CIA_IOC_STAT0_CODE_MASK 0x7 +#define CIA_IOC_STAT0_P_NBR_SHIFT 13 +#define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff + +#define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM + +/* + * Data structure for handling CIA machine checks. + */ + +/* EV5-specific info. */ +struct el_CIA_procdata { + unsigned long shadow[8]; /* PALmode shadow registers */ + unsigned long paltemp[24]; /* PAL temporary registers */ + /* EV5-specific fields */ + unsigned long exc_addr; /* Address of excepting instruction. */ + unsigned long exc_sum; /* Summary of arithmetic traps. */ + unsigned long exc_mask; /* Exception mask (from exc_sum). */ + unsigned long exc_base; /* PALbase at time of exception. */ + unsigned long isr; /* Interrupt summary register. */ + unsigned long icsr; /* Ibox control register. */ + unsigned long ic_perr_stat; + unsigned long dc_perr_stat; + unsigned long va; /* Effective VA of fault or miss. */ + unsigned long mm_stat; + unsigned long sc_addr; + unsigned long sc_stat; + unsigned long bc_tag_addr; + unsigned long ei_addr; + unsigned long fill_syn; + unsigned long ei_stat; + unsigned long ld_lock; +}; + +/* System-specific info. */ +struct el_CIA_sysdata_mcheck { + unsigned long coma_gcr; + unsigned long coma_edsr; + unsigned long coma_ter; + unsigned long coma_elar; + unsigned long coma_ehar; + unsigned long coma_ldlr; + unsigned long coma_ldhr; + unsigned long coma_base0; + unsigned long coma_base1; + unsigned long coma_base2; + unsigned long coma_cnfg0; + unsigned long coma_cnfg1; + unsigned long coma_cnfg2; + unsigned long epic_dcsr; + unsigned long epic_pear; + unsigned long epic_sear; + unsigned long epic_tbr1; + unsigned long epic_tbr2; + unsigned long epic_pbr1; + unsigned long epic_pbr2; + unsigned long epic_pmr1; + unsigned long epic_pmr2; + unsigned long epic_harx1; + unsigned long epic_harx2; + unsigned long epic_pmlt; + unsigned long epic_tag0; + unsigned long epic_tag1; + unsigned long epic_tag2; + unsigned long epic_tag3; + unsigned long epic_tag4; + unsigned long epic_tag5; + unsigned long epic_tag6; + unsigned long epic_tag7; + unsigned long epic_data0; + unsigned long epic_data1; + unsigned long epic_data2; + unsigned long epic_data3; + unsigned long epic_data4; + unsigned long epic_data5; + unsigned long epic_data6; + unsigned long epic_data7; +}; + + +#ifdef __KERNEL__ + +#ifndef __EXTERN_INLINE +#define __EXTERN_INLINE extern inline +#define __IO_EXTERN_INLINE +#endif + +/* + * Translate physical memory address as seen on (PCI) bus into + * a kernel virtual address and vv. + */ + +__EXTERN_INLINE unsigned long cia_virt_to_bus(void * address) +{ + return virt_to_phys(address) + CIA_DMA_WIN_BASE; +} + +__EXTERN_INLINE void * cia_bus_to_virt(unsigned long address) +{ + return phys_to_virt(address - CIA_DMA_WIN_BASE); +} + +/* + * I/O functions: + * + * CIA (the 2117x PCI/memory support chipset for the EV5 (21164) + * series of processors uses a sparse address mapping scheme to + * get at PCI memory and I/O. + */ + +#define vip volatile int * +#define vuip volatile unsigned int * +#define vulp volatile unsigned long * + +__EXTERN_INLINE unsigned int cia_inb(unsigned long addr) +{ + long result; + result = *(vip) ((addr << 5) + CIA_IO + 0x00); + return __kernel_extbl(result, addr & 3); +} + +__EXTERN_INLINE void cia_outb(unsigned char b, unsigned long addr) +{ + unsigned int w = __kernel_insbl(b, addr & 3); + *(vuip) ((addr << 5) + CIA_IO + 0x00) = w; + wmb(); +} + +__EXTERN_INLINE unsigned int cia_inw(unsigned long addr) +{ + long result; + result = *(vip) ((addr << 5) + CIA_IO + 0x08); + return __kernel_extwl(result, addr & 3); +} + +__EXTERN_INLINE void cia_outw(unsigned short b, unsigned long addr) +{ + unsigned int w = __kernel_inswl(b, addr & 3); + *(vuip) ((addr << 5) + CIA_IO + 0x08) = w; + wmb(); +} + +__EXTERN_INLINE unsigned int cia_inl(unsigned long addr) +{ + return *(vuip) ((addr << 5) + CIA_IO + 0x18); +} + +__EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr) +{ + *(vuip) ((addr << 5) + CIA_IO + 0x18) = b; + wmb(); +} + + +/* + * Memory functions. 64-bit and 32-bit accesses are done through + * dense memory space, everything else through sparse space. + * + * For reading and writing 8 and 16 bit quantities we need to + * go through one of the three sparse address mapping regions + * and use the HAE_MEM CSR to provide some bits of the address. + * The following few routines use only sparse address region 1 + * which gives 1Gbyte of accessible space which relates exactly + * to the amount of PCI memory mapping *into* system address space. + * See p 6-17 of the specification but it looks something like this: + * + * 21164 Address: + * + * 3 2 1 + * 9876543210987654321098765432109876543210 + * 1ZZZZ0.PCI.QW.Address............BBLL + * + * ZZ = SBZ + * BB = Byte offset + * LL = Transfer length + * + * PCI Address: + * + * 3 2 1 + * 10987654321098765432109876543210 + * HHH....PCI.QW.Address........ 00 + * + * HHH = 31:29 HAE_MEM CSR + * + */ + +__EXTERN_INLINE unsigned long cia_srm_base(unsigned long addr) +{ + unsigned long mask, base; + + if (addr >= alpha_mv.sm_base_r1 + && addr <= alpha_mv.sm_base_r1 + CIA_MEM_R1_MASK) { + mask = CIA_MEM_R1_MASK; + base = CIA_SPARSE_MEM; + } + else if (addr >= alpha_mv.sm_base_r2 + && addr <= alpha_mv.sm_base_r2 + CIA_MEM_R2_MASK) { + mask = CIA_MEM_R2_MASK; + base = CIA_SPARSE_MEM_R2; + } + else if (addr >= alpha_mv.sm_base_r3 + && addr <= alpha_mv.sm_base_r3 + CIA_MEM_R3_MASK) { + mask = CIA_MEM_R3_MASK; + base = CIA_SPARSE_MEM_R3; + } + else + { +#if 0 + printk("cia: address 0x%lx not covered by HAE\n", addr); +#endif + return 0; + } + + return ((addr & mask) << 5) + base; +} + +__EXTERN_INLINE unsigned long cia_srm_readb(unsigned long addr) +{ + unsigned long result, work; + + if ((work = cia_srm_base(addr)) == 0) + return 0xff; + work += 0x00; /* add transfer length */ + + result = *(vip) work; + return __kernel_extbl(result, addr & 3); +} + +__EXTERN_INLINE unsigned long cia_srm_readw(unsigned long addr) +{ + unsigned long result, work; + + if ((work = cia_srm_base(addr)) == 0) + return 0xffff; + work += 0x08; /* add transfer length */ + + result = *(vip) work; + return __kernel_extwl(result, addr & 3); +} + +__EXTERN_INLINE void cia_srm_writeb(unsigned char b, unsigned long addr) +{ + unsigned long work = cia_srm_base(addr), w; + if (work) { + work += 0x00; /* add transfer length */ + w = __kernel_insbl(b, addr & 3); + *(vuip) work = w; + } +} + +__EXTERN_INLINE void cia_srm_writew(unsigned short b, unsigned long addr) +{ + unsigned long work = cia_srm_base(addr), w; + if (work) { + work += 0x08; /* add transfer length */ + w = __kernel_inswl(b, addr & 3); + *(vuip) work = w; + } +} + +__EXTERN_INLINE unsigned long cia_readb(unsigned long addr) +{ + unsigned long result, msb; + + msb = addr & 0xE0000000; + addr &= CIA_MEM_R1_MASK; + set_hae(msb); + + result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00); + return __kernel_extbl(result, addr & 3); +} + +__EXTERN_INLINE unsigned long cia_readw(unsigned long addr) +{ + unsigned long result, msb; + + msb = addr & 0xE0000000; + addr &= CIA_MEM_R1_MASK; + set_hae(msb); + + result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08); + return __kernel_extwl(result, addr & 3); +} + +__EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr) +{ + unsigned long msb, w; + + msb = addr & 0xE0000000; + addr &= CIA_MEM_R1_MASK; + set_hae(msb); + + w = __kernel_insbl(b, addr & 3); + *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w; +} + +__EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr) +{ + unsigned long msb, w; + + msb = addr & 0xE0000000; + addr &= CIA_MEM_R1_MASK; + set_hae(msb); + + w = __kernel_inswl(b, addr & 3); + *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w; +} + +__EXTERN_INLINE unsigned long cia_readl(unsigned long addr) +{ + return *(vuip) (addr + CIA_DENSE_MEM); +} + +__EXTERN_INLINE unsigned long cia_readq(unsigned long addr) +{ + return *(vulp) (addr + CIA_DENSE_MEM); +} + +__EXTERN_INLINE void cia_writel(unsigned int b, unsigned long addr) +{ + *(vuip) (addr + CIA_DENSE_MEM) = b; +} + +__EXTERN_INLINE void cia_writeq(unsigned long b, unsigned long addr) +{ + *(vulp) (addr + CIA_DENSE_MEM) = b; +} + +/* Find the DENSE memory area for a given bus address. */ + +__EXTERN_INLINE unsigned long cia_dense_mem(unsigned long addr) +{ + return CIA_DENSE_MEM; +} + +#undef vip +#undef vuip +#undef vulp + +#ifdef __WANT_IO_DEF + +#define virt_to_bus cia_virt_to_bus +#define bus_to_virt cia_bus_to_virt +#define __inb cia_inb +#define __inw cia_inw +#define __inl cia_inl +#define __outb cia_outb +#define __outw cia_outw +#define __outl cia_outl + +#ifdef CONFIG_ALPHA_SRM_SETUP +#define __readb cia_srm_readb +#define __readw cia_srm_readw +#define __writeb cia_srm_writeb +#define __writew cia_srm_writew +#else +#define __readb cia_readb +#define __readw cia_readw +#define __writeb cia_writeb +#define __writew cia_writew +#endif + +#define __readl cia_readl +#define __readq cia_readq +#define __writel cia_writel +#define __writeq cia_writeq +#define dense_mem cia_dense_mem + +#define inb(port) \ +(__builtin_constant_p((port))?__inb(port):_inb(port)) +#define outb(x, port) \ +(__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port))) + +#define inw(port) \ +(__builtin_constant_p((port))?__inw(port):_inw(port)) +#define outw(x, port) \ +(__builtin_constant_p((port))?__outw((x),(port)):_outw((x),(port))) + +#define inl(port) __inl(port) +#define outl(x,port) __outl((x),(port)) + +#define readl(a) __readl((unsigned long)(a)) +#define readq(a) __readq((unsigned long)(a)) +#define writel(v,a) __writel((v),(unsigned long)(a)) +#define writeq(v,a) __writeq((v),(unsigned long)(a)) + +#endif /* __WANT_IO_DEF */ + +#ifdef __IO_EXTERN_INLINE +#undef __EXTERN_INLINE +#undef __IO_EXTERN_INLINE +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ALPHA_CIA__H__ */ -- cgit v1.2.3