From 32d720e84fb594066b2c3b0e8727a5341e03ebea Mon Sep 17 00:00:00 2001
From: Kanoj Sarcar <kanoj@engr.sgi.com>
Date: Fri, 16 Feb 2001 03:26:34 +0000
Subject: Add in support to specify the proper L2 cache line size to eliminate
 false sharing.

---
 include/asm-mips64/cache.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/asm-mips64/cache.h b/include/asm-mips64/cache.h
index c05688a72..9c50dff97 100644
--- a/include/asm-mips64/cache.h
+++ b/include/asm-mips64/cache.h
@@ -10,8 +10,9 @@
 #ifndef _ASM_CACHE_H
 #define _ASM_CACHE_H
 
+#include <linux/config.h>
+
 /* bytes per L1 cache line */
-#define L1_CACHE_BYTES		32	/* A guess */
-#define SMP_CACHE_BYTES		L1_CACHE_BYTES
+#define L1_CACHE_BYTES		(1 << CONFIG_L1_CACHE_SHIFT)
 
 #endif /* _ASM_CACHE_H */
-- 
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