Name change: the generic call flush_cache_all() does not do anything

anymore. All the flush_cache_all() calls in MIPS code is changed to
call flush_cache_l1(), and ends up flushing the L1 i/d caches.

8 files changed, 28 insertions, 27 deletions

diff --git a/arch/mips64/kernel/mips64_ksyms.c b/arch/mips64/kernel/mips64_ksyms.c
index 284e831b4..b384db2af 100644
--- a/arch/mips64/kernel/mips64_ksyms.c
+++ b/arch/mips64/kernel/mips64_ksyms.c
@@ -81,7 +81,7 @@ EXPORT_SYMBOL(csum_partial_copy);
  * Functions to control caches.
  */
 EXPORT_SYMBOL(_flush_page_to_ram);
-EXPORT_SYMBOL(_flush_cache_all);
+EXPORT_SYMBOL(_flush_cache_l1);
 #ifndef CONFIG_COHERENT_IO
 EXPORT_SYMBOL(_dma_cache_wback_inv);
 EXPORT_SYMBOL(_dma_cache_inv);
diff --git a/arch/mips64/kernel/syscall.c b/arch/mips64/kernel/syscall.c
index 55685248a..1588b95a7 100644
--- a/arch/mips64/kernel/syscall.c
+++ b/arch/mips64/kernel/syscall.c
@@ -217,7 +217,7 @@ sys_sysmips(int cmd, long arg1, int arg2, int arg3)
 		return 0;
 
 	case FLUSH_CACHE:
-		flush_cache_all();
+		flush_cache_l1();
 		return 0;
 
 	case MIPS_RDNVRAM:
diff --git a/arch/mips64/mm/andes.c b/arch/mips64/mm/andes.c
index fa140bf94..bcff62ad9 100644
--- a/arch/mips64/mm/andes.c
+++ b/arch/mips64/mm/andes.c
@@ -84,7 +84,7 @@ static void andes_copy_page(void * to, void * from)
 /* Cache operations.  These are only used with the virtual memory system,
    not for non-coherent I/O so it's ok to ignore the secondary caches.  */
 static void
-andes_flush_cache_all(void)
+andes_flush_cache_l1(void)
 {
 	blast_dcache32(); blast_icache64();
 }
@@ -116,7 +116,7 @@ andes_flush_cache_mm(struct mm_struct *mm)
 #ifdef DEBUG_CACHE
 		printk("cmm[%d]", (int)mm->context);
 #endif
-		andes_flush_cache_all();
+		andes_flush_cache_l1();
 	}
 }
 
@@ -461,7 +461,7 @@ void __init ld_mmu_andes(void)
 	_clear_page = andes_clear_page;
 	_copy_page = andes_copy_page;
 
-	_flush_cache_all = andes_flush_cache_all;
+	_flush_cache_l1 = andes_flush_cache_l1;
 	_flush_cache_l2 = andes_flush_cache_l2;
 	_flush_cache_mm = andes_flush_cache_mm;
 	_flush_cache_range = andes_flush_cache_range;
@@ -479,7 +479,7 @@ void __init ld_mmu_andes(void)
 	_show_regs = andes_show_regs;
 	_user_mode = andes_user_mode;
 
-        flush_cache_all();
+        flush_cache_l1();
 
 	/*
 	 * You should never change this register:
diff --git a/arch/mips64/mm/init.c b/arch/mips64/mm/init.c
index c518f96b4..223ca3e5e 100644
--- a/arch/mips64/mm/init.c
+++ b/arch/mips64/mm/init.c
@@ -200,7 +200,7 @@ int do_check_pgt_cache(int low, int high)
 asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
 {
 	/* XXX Just get it working for now... */
-	flush_cache_all();
+	flush_cache_l1();
 	return 0;
 }
 
diff --git a/arch/mips64/mm/loadmmu.c b/arch/mips64/mm/loadmmu.c
index b8d04273d..ce7525545 100644
--- a/arch/mips64/mm/loadmmu.c
+++ b/arch/mips64/mm/loadmmu.c
@@ -25,7 +25,6 @@ void (*_clear_page)(void * page);
 void (*_copy_page)(void * to, void * from);
 
 /* Cache operations. */
-void (*_flush_cache_all)(void);
 void (*_flush_cache_mm)(struct mm_struct *mm);
 void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
                            unsigned long end);
@@ -35,6 +34,7 @@ void (*_flush_page_to_ram)(struct page * page);
 /* MIPS specific cache operations */
 void (*_flush_cache_sigtramp)(unsigned long addr);
 void (*_flush_cache_l2)(void);
+void (*_flush_cache_l1)(void);
 
 
 /* DMA cache operations. */
diff --git a/arch/mips64/mm/r4xx0.c b/arch/mips64/mm/r4xx0.c
index 84078b824..5fa267d6d 100644
--- a/arch/mips64/mm/r4xx0.c
+++ b/arch/mips64/mm/r4xx0.c
@@ -1882,7 +1882,7 @@ r4k_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size)
 	unsigned int flags;
 
 	if (size >= dcache_size) {
-		flush_cache_all();
+		flush_cache_l1();
 	} else {
 		/* Workaround for R4600 bug.  See comment above. */
 		__save_and_cli(flags);
@@ -1906,7 +1906,7 @@ r4k_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size)
 	unsigned long end, a;
 
 	if (size >= scache_size) {
-		flush_cache_all();
+		flush_cache_l1();
 		return;
 	}
 
@@ -1926,7 +1926,7 @@ r4k_dma_cache_inv_pc(unsigned long addr, unsigned long size)
 	unsigned int flags;
 
 	if (size >= dcache_size) {
-		flush_cache_all();
+		flush_cache_l1();
 	} else {
 		/* Workaround for R4600 bug.  See comment above. */
 		__save_and_cli(flags);
@@ -1951,7 +1951,7 @@ r4k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
 	unsigned long end, a;
 
 	if (size >= scache_size) {
-		flush_cache_all();
+		flush_cache_l1();
 		return;
 	}
 
@@ -2376,7 +2376,7 @@ static void __init setup_noscache_funcs(void)
 	case 16:
 		_clear_page = r4k_clear_page_d16;
 		_copy_page = r4k_copy_page_d16;
-		_flush_cache_all = r4k_flush_cache_all_d16i16;
+		_flush_cache_l1 = r4k_flush_cache_all_d16i16;
 		_flush_cache_mm = r4k_flush_cache_mm_d16i16;
 		_flush_cache_range = r4k_flush_cache_range_d16i16;
 		_flush_cache_page = r4k_flush_cache_page_d16i16;
@@ -2394,7 +2394,7 @@ static void __init setup_noscache_funcs(void)
 			_clear_page = r4k_clear_page_d32;
 			_copy_page = r4k_copy_page_d32;
 		}
-		_flush_cache_all = r4k_flush_cache_all_d32i32;
+		_flush_cache_l1 = r4k_flush_cache_all_d32i32;
 		_flush_cache_mm = r4k_flush_cache_mm_d32i32;
 		_flush_cache_range = r4k_flush_cache_range_d32i32;
 		_flush_cache_page = r4k_flush_cache_page_d32i32;
@@ -2412,7 +2412,7 @@ static void __init setup_scache_funcs(void)
 	case 16:
 		switch(dc_lsize) {
 		case 16:
-			_flush_cache_all = r4k_flush_cache_all_s16d16i16;
+			_flush_cache_l1 = r4k_flush_cache_all_s16d16i16;
 			_flush_cache_mm = r4k_flush_cache_mm_s16d16i16;
 			_flush_cache_range = r4k_flush_cache_range_s16d16i16;
 			_flush_cache_page = r4k_flush_cache_page_s16d16i16;
@@ -2427,14 +2427,14 @@ static void __init setup_scache_funcs(void)
 	case 32:
 		switch(dc_lsize) {
 		case 16:
-			_flush_cache_all = r4k_flush_cache_all_s32d16i16;
+			_flush_cache_l1 = r4k_flush_cache_all_s32d16i16;
 			_flush_cache_mm = r4k_flush_cache_mm_s32d16i16;
 			_flush_cache_range = r4k_flush_cache_range_s32d16i16;
 			_flush_cache_page = r4k_flush_cache_page_s32d16i16;
 			_flush_page_to_ram = r4k_flush_page_to_ram_s32d16i16;
 			break;
 		case 32:
-			_flush_cache_all = r4k_flush_cache_all_s32d32i32;
+			_flush_cache_l1 = r4k_flush_cache_all_s32d32i32;
 			_flush_cache_mm = r4k_flush_cache_mm_s32d32i32;
 			_flush_cache_range = r4k_flush_cache_range_s32d32i32;
 			_flush_cache_page = r4k_flush_cache_page_s32d32i32;
@@ -2447,14 +2447,14 @@ static void __init setup_scache_funcs(void)
 	case 64:
 		switch(dc_lsize) {
 		case 16:
-			_flush_cache_all = r4k_flush_cache_all_s64d16i16;
+			_flush_cache_l1 = r4k_flush_cache_all_s64d16i16;
 			_flush_cache_mm = r4k_flush_cache_mm_s64d16i16;
 			_flush_cache_range = r4k_flush_cache_range_s64d16i16;
 			_flush_cache_page = r4k_flush_cache_page_s64d16i16;
 			_flush_page_to_ram = r4k_flush_page_to_ram_s64d16i16;
 			break;
 		case 32:
-			_flush_cache_all = r4k_flush_cache_all_s64d32i32;
+			_flush_cache_l1 = r4k_flush_cache_all_s64d32i32;
 			_flush_cache_mm = r4k_flush_cache_mm_s64d32i32;
 			_flush_cache_range = r4k_flush_cache_range_s64d32i32;
 			_flush_cache_page = r4k_flush_cache_page_s64d32i32;
@@ -2467,14 +2467,14 @@ static void __init setup_scache_funcs(void)
 	case 128:
 		switch(dc_lsize) {
 		case 16:
-			_flush_cache_all = r4k_flush_cache_all_s128d16i16;
+			_flush_cache_l1 = r4k_flush_cache_all_s128d16i16;
 			_flush_cache_mm = r4k_flush_cache_mm_s128d16i16;
 			_flush_cache_range = r4k_flush_cache_range_s128d16i16;
 			_flush_cache_page = r4k_flush_cache_page_s128d16i16;
 			_flush_page_to_ram = r4k_flush_page_to_ram_s128d16i16;
 			break;
 		case 32:
-			_flush_cache_all = r4k_flush_cache_all_s128d32i32;
+			_flush_cache_l1 = r4k_flush_cache_all_s128d32i32;
 			_flush_cache_mm = r4k_flush_cache_mm_s128d32i32;
 			_flush_cache_range = r4k_flush_cache_range_s128d32i32;
 			_flush_cache_page = r4k_flush_cache_page_s128d32i32;
@@ -2550,7 +2550,7 @@ void __init ld_mmu_r4xx0(void)
 	_show_regs = r4k_show_regs;
 	_user_mode = r4k_user_mode;
 
-	flush_cache_all();
+	flush_cache_l1();
 
 	/*
 	 * You should never change this register:
diff --git a/arch/mips64/sgi-ip27/ip27-init.c b/arch/mips64/sgi-ip27/ip27-init.c
index f18b124a1..f6b94445b 100644
--- a/arch/mips64/sgi-ip27/ip27-init.c
+++ b/arch/mips64/sgi-ip27/ip27-init.c
@@ -301,7 +301,7 @@ void per_hub_init(cnodeid_t cnode)
 			memcpy((void *)(KSEG0 + 0x100), (void *) KSEG0, 0x80);
 			memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
 								0x100);
-			flush_cache_all();
+			flush_cache_l1();
 			flush_cache_l2();
 		}
 #endif
@@ -419,7 +419,7 @@ void cboot(void)
 	init_mfhi_war();
 #endif
 	_flush_tlb_all();
-	flush_cache_all();
+	flush_cache_l1();
 	flush_cache_l2();
 	start_secondary();
 }
diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h
index 867e78041..a5b5b977d 100644
--- a/include/asm-mips64/pgtable.h
+++ b/include/asm-mips64/pgtable.h
@@ -27,20 +27,19 @@
  *  - flush_cache_range(mm, start, end) flushes a range of pages
  *  - flush_page_to_ram(page) write back kernel page to ram
  */
-extern void (*_flush_cache_all)(void);
 extern void (*_flush_cache_mm)(struct mm_struct *mm);
 extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
                                  unsigned long end);
 extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
 extern void (*_flush_page_to_ram)(struct page * page);
 
-#define flush_cache_all()		_flush_cache_all()
+#define flush_cache_all()		do { } while(0)
 #define flush_cache_mm(mm)		_flush_cache_mm(mm)
 #define flush_cache_range(mm,start,end)	_flush_cache_range(mm,start,end)
 #define flush_cache_page(vma,page)	_flush_cache_page(vma, page)
 #define flush_page_to_ram(page)		_flush_page_to_ram(page)
 
-#define flush_icache_range(start, end)	flush_cache_all()
+#define flush_icache_range(start, end)	_flush_cache_l1()
 
 #define flush_icache_page(vma, page)					\
 do {									\
@@ -55,9 +54,11 @@ do {									\
  */
 extern void (*_flush_cache_sigtramp)(unsigned long addr);
 extern void (*_flush_cache_l2)(void);
+extern void (*_flush_cache_l1)(void);
 
 #define flush_cache_sigtramp(addr)	_flush_cache_sigtramp(addr)
 #define flush_cache_l2()		_flush_cache_l2()
+#define flush_cache_l1()		_flush_cache_l1()
 
 /*
  * Each address space has 2 4K pages as its page directory, giving 1024