virt_to_bus and bus_to_virt are gone! Implement true pci-dma api that

routes all dma's via the containing xbow's master hub.

4 files changed, 21 insertions, 26 deletions

diff --git a/arch/mips64/sgi-ip27/ip27-pci-dma.c b/arch/mips64/sgi-ip27/ip27-pci-dma.c
index 81e3e5c6f..b8d5f8776 100644
--- a/arch/mips64/sgi-ip27/ip27-pci-dma.c
+++ b/arch/mips64/sgi-ip27/ip27-pci-dma.c
@@ -42,7 +42,7 @@ void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
 
 	if (ret != NULL) {
 		memset(ret, 0, size);
-		*dma_handle = virt_to_bus(ret);
+		*dma_handle = (bus_to_baddr[hwdev->bus->number] | __pa(ret));
 	}
 
 	return ret;
diff --git a/arch/mips64/sgi-ip27/ip27-setup.c b/arch/mips64/sgi-ip27/ip27-setup.c
index f1f835939..141f29c2e 100644
--- a/arch/mips64/sgi-ip27/ip27-setup.c
+++ b/arch/mips64/sgi-ip27/ip27-setup.c
@@ -104,10 +104,12 @@ static void __init verify_mode(void)
 #define BASE_XBOW_PORT  	8     /* Lowest external port */
 
 unsigned int bus_to_cpu[256];
+unsigned long bus_to_baddr[256];
 
 void __init pcibr_setup(cnodeid_t nid)
 {
-	int 			i, start, num, masterwid;
+	int 			i, start, num;
+	unsigned long		masterwid;
 	bridge_t 		*bridge; 
 	volatile u64 		hubreg;
 	nasid_t	 		nasid, masternasid;
@@ -149,6 +151,7 @@ void __init pcibr_setup(cnodeid_t nid)
         		bus_to_wid[0] = 0x8;
 			bus_to_nid[0] = 0;
 			masterwid = 0xa;
+			bus_to_baddr[0] = 0xa100000000000000UL;
 		} else if (partnum == XBOW_WIDGET_PART_NUM) {
 			lboard_t *brd;
 			klxbow_t *xbow_p;
@@ -200,6 +203,7 @@ void __init pcibr_setup(cnodeid_t nid)
 					printk("widget 0x%x is a bridge\n", i);
 					bus_to_wid[num_bridges] = i;
 					bus_to_nid[num_bridges] = nasid;
+					bus_to_baddr[num_bridges] = ((masterwid << 60) | (1UL << 56));	/* Barrier set */
 					num_bridges++;
 				   }
 				}
@@ -218,6 +222,9 @@ void __init pcibr_setup(cnodeid_t nid)
         		bus_to_nid[1] = 0;
         		bus_to_nid[2] = 0;
 
+			bus_to_baddr[0] = 0xa100000000000000UL;
+			bus_to_baddr[1] = 0xa100000000000000UL;
+			bus_to_baddr[2] = 0xa100000000000000UL;
 			masterwid = 0xa;
 			num_bridges = 3;
 		}
diff --git a/include/asm-mips64/io.h b/include/asm-mips64/io.h
index dcedea9df..753adeb6a 100644
--- a/include/asm-mips64/io.h
+++ b/include/asm-mips64/io.h
@@ -23,6 +23,8 @@
 #include <asm/sn/io.h>
 #endif
 
+extern unsigned long bus_to_baddr[256];
+
 /*
  * Slowdown I/O port space accesses for antique hardware.
  */
@@ -111,22 +113,6 @@ extern inline void * phys_to_virt(unsigned long address)
 	return (void *)(address + PAGE_OFFSET);
 }
 
-#define	BRIDGE_DIRECT_MAPPED_BASE	0xa180000000000000ull
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- * This simplistic model doesn't hold for the Origin.
- */
-extern inline unsigned long virt_to_bus(volatile void * address)
-{
-	return (((unsigned long)address - PAGE_OFFSET)|BRIDGE_DIRECT_MAPPED_BASE);
-}
-
-extern inline void * bus_to_virt(unsigned long address)
-{
-	return (void *)((address & ~BRIDGE_DIRECT_MAPPED_BASE) + PAGE_OFFSET);
-}
-
 /*
  * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
  * for the processor.  This implies the assumption that there is only
diff --git a/include/asm-mips64/pci.h b/include/asm-mips64/pci.h
index b530f89a2..0112244e3 100644
--- a/include/asm-mips64/pci.h
+++ b/include/asm-mips64/pci.h
@@ -78,9 +78,10 @@ extern inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
+#ifndef CONFIG_COHERENT_IO
 	dma_cache_wback_inv((unsigned long)ptr, size);
-
-	return virt_to_bus(ptr);
+#endif
+	return (bus_to_baddr[hwdev->bus->number] | __pa(ptr));
 }
 
 /*
@@ -119,18 +120,18 @@ extern inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
 extern inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 			     int nents, int direction)
 {
-#ifndef CONFIG_COHERENT_IO
 	int i;
-#endif
 
 	if (direction == PCI_DMA_NONE)
 		BUG();
 
 	/* Make sure that gcc doesn't leave the empty loop body.  */
+	for (i = 0; i < nents; i++, sg++) {
 #ifndef CONFIG_COHERENT_IO
-	for (i = 0; i < nents; i++, sg++)
 		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
 #endif
+		sg->address = (char *)(bus_to_baddr[hwdev->bus->number] | __pa(sg->address));
+	}
 
 	return nents;
 }
@@ -165,8 +166,9 @@ extern inline void pci_dma_sync_single(struct pci_dev *hwdev,
 {
 	if (direction == PCI_DMA_NONE)
 		BUG();
-
-	dma_cache_wback_inv((unsigned long)bus_to_virt(dma_handle), size);
+#ifndef CONFIG_COHERENT_IO
+	dma_cache_wback_inv((unsigned long)__va(dma_handle - bus_to_baddr[hwdev->bus->number]), size);
+#endif
 }
 
 /*
@@ -201,7 +203,7 @@ extern inline void pci_dma_sync_sg(struct pci_dev *hwdev,
  * returns, or alternatively stop on the first sg_dma_len(sg) which
  * is 0.
  */
-#define sg_dma_address(sg)	(virt_to_bus((sg)->address))
+#define sg_dma_address(sg)	((unsigned long)((sg)->address))
 #define sg_dma_len(sg)		((sg)->length)
 
 #endif /* __KERNEL__ */