DECstation updates

15 files changed, 282 insertions, 179 deletions

diff --git a/arch/mips/dec/irq.c b/arch/mips/dec/irq.c
index 1090470a0..d5d6303ed 100644
--- a/arch/mips/dec/irq.c
+++ b/arch/mips/dec/irq.c
@@ -4,7 +4,7 @@
  * Copyright (C) 1992 Linus Torvalds
  * Copyright (C) 1994, 1995, 1996, 1997 Ralf Baechle
  *
- * $Id: irq.c,v 1.1.2.1 1998/03/18 20:51:19 harald Exp $
+ * $Id: irq.c,v 1.2 1999/01/17 03:49:41 ralf Exp $
  */
 #include <linux/errno.h>
 #include <linux/init.h>
@@ -24,7 +24,6 @@
 #include <asm/irq.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
-#include <asm/wbflush.h>
 
 #include <asm/dec/interrupts.h>
 
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index 5fa828384..de80c34e8 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -93,3 +93,12 @@ __initfunc(void prom_meminit(unsigned int magic))
 	prom_printf("mips_memory_upper: 0x%08x\n", mips_memory_upper);
 #endif
 }
+
+/* Called from mem_init() to fixup the mem_map page settings. */
+__initfunc(void prom_fixup_mem_map(unsigned long start, unsigned long end))
+{
+}
+
+void prom_free_prom_memory (void)
+{
+}
diff --git a/arch/mips/dec/reset.c b/arch/mips/dec/reset.c
index 644935747..e4d07608f 100644
--- a/arch/mips/dec/reset.c
+++ b/arch/mips/dec/reset.c
@@ -1,22 +1,25 @@
-
-
 /*
- *  linux/arch/mips/dec/reset.c
+ *  $Id: $
  *
  *  Reset a DECstation machine.
  *
- *  $Id: reset.c,v 1.3 1998/03/04 08:29:10 ralf Exp $
  */
 
+void (*back_to_prom)(void) = (void (*)(void))0xBFC00000;
+
 void dec_machine_restart(char *command)
 {
+	back_to_prom();
 }
 
 void dec_machine_halt(void)
 {
+	back_to_prom();
 }
 
 void dec_machine_power_off(void)
 {
     /* DECstations don't have a software power switch */
+	back_to_prom();
 }
+
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 9999de881..d7fbc4a13 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -101,9 +101,13 @@ __initfunc(static void dec_time_init(struct irqaction *irq))
 {
     /*
      * Here we go, enable periodic rtc interrupts.
-     * Frequency is 128 Hz.
      */
-    CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x9, RTC_REG_A);
+
+#ifndef LOG_2_HZ
+#  define LOG_2_HZ 7
+#endif
+
+    CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
     CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
     setup_dec_irq(CLOCK, irq);
 }
@@ -291,25 +295,30 @@ __initfunc(void dec_init_kn02ba(void))
     asic_mask_tbl[0] = KMIN_CLOCK;
     asic_irq_nr[0] = CLOCK;
 
+    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
+    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
+    asic_mask_tbl[1] = SCSI_DMA_INTS;
+    asic_irq_nr[1] = SCSI_DMA_INT;
+
     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_INT].iemask = KMIN_SCSI_INTS;
-    asic_mask_tbl[1] = KMIN_SCSI_INTS;
-    asic_irq_nr[1] = SCSI_INT;
+    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
+    asic_mask_tbl[2] = SCSI_CHIP;
+    asic_irq_nr[2] = SCSI_INT;
 
     dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
     dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[2] = LANCE_INTS;
-    asic_irq_nr[2] = ETHER;
+    asic_mask_tbl[3] = LANCE_INTS;
+    asic_irq_nr[3] = ETHER;
 
     dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
     dec_interrupt[SERIAL].iemask = SERIAL_INTS;
-    asic_mask_tbl[3] = SERIAL_INTS;
-    asic_irq_nr[3] = SERIAL;
+    asic_mask_tbl[4] = SERIAL_INTS;
+    asic_irq_nr[4] = SERIAL;
 
     dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
     dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT;
-    asic_mask_tbl[4] = KMIN_TIMEOUT;
-    asic_irq_nr[4] = MEMORY;
+    asic_mask_tbl[5] = KMIN_TIMEOUT;
+    asic_irq_nr[5] = MEMORY;
 
     dec_interrupt[TC0].cpu_mask = IE_IRQ0;
     dec_interrupt[TC0].iemask = 0;
@@ -366,30 +375,35 @@ __initfunc(void dec_init_kn02ca(void))
     cpu_mask_tbl[0] = IE_IRQ1;
     cpu_irq_nr[0] = CLOCK;
 
+    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
+    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
+    asic_mask_tbl[0] = SCSI_DMA_INTS;
+    asic_irq_nr[0] = SCSI_DMA_INT;
+
     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
-    dec_interrupt[SCSI_INT].iemask = SCSI_INTS;
-    asic_mask_tbl[0] = SCSI_INTS;
-    asic_irq_nr[0] = SCSI_INT;
+    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
+    asic_mask_tbl[1] = SCSI_CHIP;
+    asic_irq_nr[1] = SCSI_INT;
 
     dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
     dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[1] = LANCE_INTS;
-    asic_irq_nr[1] = ETHER;
+    asic_mask_tbl[2] = LANCE_INTS;
+    asic_irq_nr[2] = ETHER;
 
     dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
     dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS;
-    asic_mask_tbl[2] = XINE_SERIAL_INTS;
-    asic_irq_nr[2] = SERIAL;
+    asic_mask_tbl[3] = XINE_SERIAL_INTS;
+    asic_irq_nr[3] = SERIAL;
 
     dec_interrupt[TC0].cpu_mask = IE_IRQ3;
     dec_interrupt[TC0].iemask = MAXINE_TC0;
-    asic_mask_tbl[3] = MAXINE_TC0;
-    asic_irq_nr[3] = TC0;
+    asic_mask_tbl[4] = MAXINE_TC0;
+    asic_irq_nr[4] = TC0;
 
     dec_interrupt[TC1].cpu_mask = IE_IRQ3;
     dec_interrupt[TC1].iemask = MAXINE_TC1;
-    asic_mask_tbl[4] = MAXINE_TC1;
-    asic_irq_nr[4] = TC1;
+    asic_mask_tbl[5] = MAXINE_TC1;
+    asic_irq_nr[5] = TC1;
 
     dec_interrupt[MEMORY].cpu_mask = IE_IRQ2;
     dec_interrupt[MEMORY].iemask = 0;
@@ -436,35 +450,40 @@ __initfunc(void dec_init_kn03(void))
     cpu_mask_tbl[0] = IE_IRQ1;
     cpu_irq_nr[0] = CLOCK;
 
+    dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0;
+    dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
+    asic_mask_tbl[0] = SCSI_DMA_INTS;
+    asic_irq_nr[0] = SCSI_DMA_INT;
+
     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
-    dec_interrupt[SCSI_INT].iemask = SCSI_INTS;
-    asic_mask_tbl[0] = SCSI_INTS;
-    asic_irq_nr[0] = SCSI_INT;
+    dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
+    asic_mask_tbl[1] = SCSI_CHIP;
+    asic_irq_nr[1] = SCSI_INT;
 
     dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
     dec_interrupt[ETHER].iemask = LANCE_INTS;
-    asic_mask_tbl[1] = LANCE_INTS;
-    asic_irq_nr[1] = ETHER;
+    asic_mask_tbl[2] = LANCE_INTS;
+    asic_irq_nr[2] = ETHER;
 
     dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
     dec_interrupt[SERIAL].iemask = SERIAL_INTS;
-    asic_mask_tbl[2] = SERIAL_INTS;
-    asic_irq_nr[2] = SERIAL;
+    asic_mask_tbl[3] = SERIAL_INTS;
+    asic_irq_nr[3] = SERIAL;
 
     dec_interrupt[TC0].cpu_mask = IE_IRQ0;
     dec_interrupt[TC0].iemask = KN03_TC0;
-    asic_mask_tbl[3] = KN03_TC0;
-    asic_irq_nr[3] = TC0;
+    asic_mask_tbl[4] = KN03_TC0;
+    asic_irq_nr[4] = TC0;
 
     dec_interrupt[TC1].cpu_mask = IE_IRQ0;
     dec_interrupt[TC1].iemask = KN03_TC1;
-    asic_mask_tbl[4] = KN03_TC1;
-    asic_irq_nr[4] = TC1;
+    asic_mask_tbl[5] = KN03_TC1;
+    asic_irq_nr[5] = TC1;
 
     dec_interrupt[TC2].cpu_mask = IE_IRQ0;
     dec_interrupt[TC2].iemask = KN03_TC2;
-    asic_mask_tbl[5] = KN03_TC2;
-    asic_irq_nr[5] = TC2;
+    asic_mask_tbl[6] = KN03_TC2;
+    asic_irq_nr[6] = TC2;
 
     dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
     dec_interrupt[MEMORY].iemask = 0;
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 649df1b9c..dd4951691 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -423,7 +423,7 @@ __initfunc(void time_init(void))
      * The PROM will reset the year to either '70, '71 or '72.
      * This hack will only work until Dec 31 2001.
      */
-    year += 1925;
+    year += 1927;
 
     xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
     xtime.tv_usec = 0;
diff --git a/arch/mips/dec/wbflush.c b/arch/mips/dec/wbflush.c
index 3c7338c92..6b183634b 100644
--- a/arch/mips/dec/wbflush.c
+++ b/arch/mips/dec/wbflush.c
@@ -101,11 +101,4 @@ static void wbflush_kn02ba(void)
  */
 static void wbflush_kn03(void)
 {
-    asm(".set\tpush\n\t"
-	".set\tnoreorder\n\t"
-	"lui\t$2,0xbf84\n\t"
-	"lw\t$3,0x120($2)\n\t"
-	"lw\t$3,0x120($2)\n\t"
-	".set\tpop"
-  : : :"$2", "$3");
 }
diff --git a/drivers/net/declance.c b/drivers/net/declance.c
index b5c5b4f42..b0183061c 100644
--- a/drivers/net/declance.c
+++ b/drivers/net/declance.c
@@ -60,7 +60,6 @@ static char *lancestr = "LANCE";
 #include <asm/dec/machtype.h>
 #include <asm/dec/tc.h>
 #include <asm/dec/kn01.h>
-#include <asm/wbflush.h>
 #include <asm/addrspace.h>
 
 #include <linux/config.h>
@@ -302,7 +301,6 @@ int dec_lance_debug = 2;
 static inline void writereg(volatile unsigned short *regptr, short value)
 {
 	*regptr = value;
-	wbflush();
 }
 
 /* Load the CSR registers */
@@ -382,7 +380,6 @@ void cp_to_buf(void *to, const void *from, __kernel_size_t len)
 		}
 	}
 
-	wbflush();
 }
 
 void cp_from_buf(void *to, unsigned char *from, int len)
@@ -518,7 +515,6 @@ static void lance_init_ring(struct device *dev)
 		if (i < 3 && ZERO)
 			printk("%d: 0x%8.8x(0x%8.8x)\n", i, leptr, (int) lp->rx_buf_ptr_cpu[i]);
 	}
-	wbflush();
 }
 
 static int init_restart_lance(struct lance_private *lp)
@@ -756,7 +752,6 @@ static void lance_interrupt(const int irq, void *dev_id, struct pt_regs *regs)
 			 * re-enable LANCE DMA
 			 */
 			*(unsigned long *) (system_base + IOCTL + SSR) |= (1 << 16);
-			wbflush();
 		}
 		writereg(&ll->rdp, LE_C0_STOP);
 
@@ -1076,7 +1071,6 @@ __initfunc(static int dec_lance_init(struct device *dev, const int type))
 		lp->dma_ptr_reg = (unsigned long *) (system_base + IOCTL + LANCE_DMA_P);
 		*(lp->dma_ptr_reg) = PHYSADDR(dev->mem_start) << 3;
 		*(unsigned long *) (system_base + IOCTL + SSR) |= (1 << 16);
-		wbflush();
 
 		break;
 	case PMAD_LANCE:
diff --git a/drivers/scsi/dec_esp.c b/drivers/scsi/dec_esp.c
index b1da29c72..f1c56cd16 100644
--- a/drivers/scsi/dec_esp.c
+++ b/drivers/scsi/dec_esp.c
@@ -33,9 +33,12 @@
 #include <asm/dec/tc.h>
 #include <asm/dec/interrupts.h>
 #include <asm/dec/ioasic_addrs.h>
+#include <asm/dec/ioasic_ints.h>
+#include <asm/dec/machtype.h>
 
 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
-static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
+static void dma_drain(struct NCR_ESP *esp);
+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp);
 static void dma_dump_state(struct NCR_ESP *esp);
 static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length);
 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length);
@@ -44,13 +47,9 @@ static void dma_ints_on(struct NCR_ESP *esp);
 static int  dma_irq_p(struct NCR_ESP *esp);
 static int  dma_ports_p(struct NCR_ESP *esp);
 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
-static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp);
-static void dma_advance_sg (Scsi_Cmnd *sp);
-static void dma_led_off(struct NCR_ESP *);
-static void dma_led_on(struct NCR_ESP *);
+static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp);
+static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp);
+static void dma_advance_sg(Scsi_Cmnd * sp);
 
 
 volatile unsigned char cmd_buffer[16];
@@ -59,18 +58,32 @@ volatile unsigned char cmd_buffer[16];
 				 * via PIO.
 				 */
 
+volatile unsigned long *scsi_dma_ptr;
+volatile unsigned long *scsi_next_ptr;
+volatile unsigned long *scsi_scr;
+volatile unsigned long *ioasic_ssr;
+volatile unsigned long *scsi_sdr0;
+volatile unsigned long *scsi_sdr1;
+
+static void scsi_dma_int(int, void *, struct pt_regs *);
+
 /***************************************************************** Detection */
-int dec_esp_detect(Scsi_Host_Template *tpnt)
+int dec_esp_detect(Scsi_Host_Template * tpnt)
 {
     struct NCR_ESP *esp;
     struct ConfigDev *esp_dev;
-    int slot;
 
-    if ((slot = search_tc_card("PMAZ-AA")) >= 0) {
-	claim_tc_card(slot);
+	if (IOASIC) {
 	esp_dev = 0;
 	esp = esp_allocate(tpnt, (void *) esp_dev);
 	
+		scsi_dma_ptr = (unsigned long *) (system_base + IOCTL + SCSI_DMA_P);
+		scsi_next_ptr = (unsigned long *) (system_base + IOCTL + SCSI_DMA_BP);
+		scsi_scr = (unsigned long *) (system_base + IOCTL + SCSI_SCR);
+		ioasic_ssr = (unsigned long *) (system_base + IOCTL + SSR);
+		scsi_sdr0 = (unsigned long *) (system_base + IOCTL + SCSI_SDR0);
+		scsi_sdr1 = (unsigned long *) (system_base + IOCTL + SCSI_SDR1);
+
 	/* Do command transfer with programmed I/O */
 	esp->do_pio_cmds = 1;
 	
@@ -88,7 +101,7 @@ int dec_esp_detect(Scsi_Host_Template *tpnt)
 
 	/* Optional functions */
 	esp->dma_barrier = 0;
-	esp->dma_drain = 0;
+		esp->dma_drain = &dma_drain;
 	esp->dma_invalidate = 0;
 	esp->dma_irq_entry = 0;
 	esp->dma_irq_exit = 0;
@@ -100,13 +113,13 @@ int dec_esp_detect(Scsi_Host_Template *tpnt)
 	/* virtual DMA functions */
 	esp->dma_mmu_get_scsi_one = &dma_mmu_get_scsi_one;
 	esp->dma_mmu_get_scsi_sgl = &dma_mmu_get_scsi_sgl;
-	esp->dma_mmu_release_scsi_one = &dma_mmu_release_scsi_one;
-	esp->dma_mmu_release_scsi_sgl = &dma_mmu_release_scsi_sgl;
+		esp->dma_mmu_release_scsi_one = 0;
+		esp->dma_mmu_release_scsi_sgl = 0;
 	esp->dma_advance_sg = &dma_advance_sg;
 
 
 	/* SCSI chip speed */
-	esp->cfreq = get_tc_speed();
+		esp->cfreq = 25000000;
 
 	/* 
 	 * we don't give the address of DMA channel, but the number
@@ -116,17 +129,19 @@ int dec_esp_detect(Scsi_Host_Template *tpnt)
 	esp->dregs = JAZZ_SCSI_DMA;
 	
 	/* ESP register base */
-	esp->eregs = (struct ESP_regs *)get_tc_base_addr(slot);
+		esp->eregs = (struct ESP_regs *) (system_base + SCSI);
 	
 	/* Set the command buffer */
-	esp->esp_command = (volatile unsigned char *)cmd_buffer;
+		esp->esp_command = (volatile unsigned char *) cmd_buffer;
 	
 	/* get virtual dma address for command buffer */
-	esp->esp_command_dvma = (volatile unsigned char *)cmd_buffer; /* vdma_alloc(PHYSADDR(cmd_buffer), sizeof (cmd_buffer)); */
+		esp->esp_command_dvma = KSEG1ADDR((volatile unsigned char *) cmd_buffer);
 	
-	esp->irq = get_tc_irq_nr(slot);
+		esp->irq = SCSI_INT;
 	request_irq(esp->irq, esp_intr, SA_INTERRUPT, "NCR 53C94 SCSI",
 	            NULL);
+		request_irq(SCSI_DMA_INT, scsi_dma_int, SA_INTERRUPT, "JUNKIO SCSI DMA",
+			    NULL);
 
 	/*
 	 * FIXME, look if the scsi id is availabe from NVRAM
@@ -139,7 +154,7 @@ int dec_esp_detect(Scsi_Host_Template *tpnt)
 
 	esp_initialize(esp);
 	
-	printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps,esps_in_use);
+		printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 	esps_running = esps_in_use;
 	return esps_in_use;
     }
@@ -147,61 +162,140 @@ int dec_esp_detect(Scsi_Host_Template *tpnt)
 }
 
 /************************************************************* DMA Functions */
+static void scsi_dma_int(int irq, void *dev_id, struct pt_regs *regs)
+{
+	extern volatile unsigned int *isr;
+	unsigned int dummy;
+
+	if (*isr & SCSI_PTR_LOADED) {
+		/* next page */
+		*scsi_next_ptr = ((*scsi_dma_ptr + PAGE_SIZE) & PAGE_MASK) << 3;
+		*isr &= ~SCSI_PTR_LOADED;
+	} else {
+		printk("Got unexpected SCSI DMA Interrupt! < ");
+		if (*isr & SCSI_PAGOVRRUN)
+			printk("SCSI_PAGOVRRUN ");
+		if (*isr & SCSI_DMA_MEMRDERR)
+			printk("SCSI_DMA_MEMRDERR ");
+		printk(">\n");
+//		panic("stop");
+		*isr &= ~(SCSI_PAGOVRRUN || SCSI_DMA_MEMRDERR);
+	}
+
+	/*
+	 * This driver will only work on IOASIC machines
+	 * so we can avoid an indirect function call here
+	 * and flush the writeback buffer the fast way
+	 */
+	dummy = *isr;
+	dummy = *isr;
+}
+
 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 {
     return fifo_count;
 }
 
-static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
+static void dma_drain(struct NCR_ESP *esp)
 {
+	unsigned long nw;
+	unsigned short *p = KSEG1ADDR((unsigned short *) ((*scsi_dma_ptr) >> 3));
+
     /*
-     * maximum DMA size is 1MB
+	 * Is there something in the dma buffers left?
      */
-    unsigned long sz = sp->SCp.this_residual;
-    if(sz > 0x100000)
-	sz = 0x100000;
-    return sz;
+	if (nw = *scsi_scr) {
+		switch (nw) {
+		case 1:
+			*p = (unsigned short) *scsi_sdr0;
+			break;
+		case 2:
+			*p++ = (unsigned short) (*scsi_sdr0);
+			*p = (unsigned short) ((*scsi_sdr0) >> 16);
+			break;
+		case 3:
+			*p++ = (unsigned short) (*scsi_sdr0);
+			*p++ = (unsigned short) ((*scsi_sdr0) >> 16);
+			*p = (unsigned short) (*scsi_sdr1);
+			break;
+		default:
+			printk("Strange: %d words in dma buffer left\n", (int) nw);
+			break;
+		}
+	}
 }
 
-static void dma_dump_state(struct NCR_ESP *esp)
+static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd * sp)
 {
+	return sp->SCp.this_residual;;
+}
     
+static void dma_dump_state(struct NCR_ESP *esp)
+{
+/*    
     ESPLOG(("esp%d: dma -- enable <%08x> residue <%08x\n",
 	    esp->esp_id, vdma_get_enable((int)esp->dregs), vdma_get_resdiue((int)esp->dregs)));
+ */
 }
 
 static void dma_init_read(struct NCR_ESP *esp, __u32 vaddress, int length)
 {
-/*
-    dma_cache_wback_inv ((unsigned long)phys_to_virt(vdma_log2phys(vaddress)), length);
-    vdma_disable ((int)esp->dregs);
-    vdma_set_mode ((int)esp->dregs, DMA_MODE_READ);
-    vdma_set_addr ((int)esp->dregs, vaddress);
-    vdma_set_count ((int)esp->dregs, length);
-    vdma_enable ((int)esp->dregs);
-*/
+	extern volatile unsigned int *isr;
+	unsigned int dummy;
+
+	if (vaddress & 3)
+		panic("dec_efs.c: unable to handle partial word transfers, yet...");
+
+	dma_cache_wback_inv((unsigned long) phys_to_virt(vaddress), length);
+
+	*ioasic_ssr &= ~SCSI_DMA_EN;
+	*scsi_scr = 0;
+	*scsi_dma_ptr = vaddress << 3;
+
+	/* prepare for next page */
+	*scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3;
+	*ioasic_ssr |= (SCSI_DMA_DIR | SCSI_DMA_EN);
+
+	/*
+	 * see above
+	 */
+	dummy = *isr;
+	dummy = *isr;
 }
 
 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddress, int length)
 {
-/*
-    dma_cache_wback_inv ((unsigned long)phys_to_virt(vdma_log2phys(vaddress)), length);    
-    vdma_disable ((int)esp->dregs);    
-    vdma_set_mode ((int)esp->dregs, DMA_MODE_WRITE);
-    vdma_set_addr ((int)esp->dregs, vaddress);
-    vdma_set_count ((int)esp->dregs, length);
-    vdma_enable ((int)esp->dregs);    
-*/
+	extern volatile unsigned int *isr;
+	unsigned int dummy;
+
+	if (vaddress & 3)
+		panic("dec_efs.c: unable to handle partial word transfers, yet...");
+
+	dma_cache_wback_inv((unsigned long) phys_to_virt(vaddress), length);
+
+	*ioasic_ssr &= ~(SCSI_DMA_DIR | SCSI_DMA_EN);
+	*scsi_scr = 0;
+	*scsi_dma_ptr = vaddress << 3;
+
+	/* prepare for next page */
+	*scsi_next_ptr = ((vaddress + PAGE_SIZE) & PAGE_MASK) << 3;
+	*ioasic_ssr |= SCSI_DMA_EN;
+
+	/*
+	 * see above
+	 */
+	dummy = *isr;
+	dummy = *isr;
 }
 
 static void dma_ints_off(struct NCR_ESP *esp)
 {
-    disable_irq(esp->irq);
+	disable_irq(SCSI_DMA_INT);
 }
 
 static void dma_ints_on(struct NCR_ESP *esp)
 {
-    enable_irq(esp->irq);
+	enable_irq(SCSI_DMA_INT);
 }
 
 static int dma_irq_p(struct NCR_ESP *esp)
@@ -212,10 +306,9 @@ static int dma_irq_p(struct NCR_ESP *esp)
 static int dma_ports_p(struct NCR_ESP *esp)
 {
 /*
-    int enable = vdma_get_enable((int)esp->dregs);
-    
-    return (enable & R4030_CHNL_ENABLE);
-*/
+ * FIXME: what's this good for?
+ */
+	return 1;
 }
 
 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
@@ -224,76 +317,35 @@ static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
      * On the Sparc, DMA_ST_WRITE means "move data from device to memory"
      * so when (write) is true, it actually means READ!
      */
-/*
-    if(write){
+	if (write) {
 	dma_init_read(esp, addr, count);
     } else {
 	dma_init_write(esp, addr, count);
     }
-*/
 }
 
-static void dma_mmu_get_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
-{
 /*
-    sp->SCp.have_data_in = vdma_alloc(PHYSADDR(sp->SCp.buffer), sp->SCp.this_residual);
-    sp->SCp.ptr = (char *)((unsigned long)sp->SCp.have_data_in);
-*/
+ * These aren't used yet
+ */
+static void dma_mmu_get_scsi_one(struct NCR_ESP *esp, Scsi_Cmnd * sp)
+{
+	sp->SCp.have_data_in = PHYSADDR(sp->SCp.buffer);
+	sp->SCp.ptr = (char *) ((unsigned long) sp->SCp.have_data_in);
 }
 
-static void dma_mmu_get_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
+static void dma_mmu_get_scsi_sgl(struct NCR_ESP *esp, Scsi_Cmnd * sp)
 {
-/*
     int sz = sp->SCp.buffers_residual;
     struct mmu_sglist *sg = (struct mmu_sglist *) sp->SCp.buffer;
     
     while (sz >= 0) {
-	sg[sz].dvma_addr = vdma_alloc(PHYSADDR(sg[sz].addr), sg[sz].len);
+		sg[sz].dvma_addr = PHYSADDR(sg[sz].addr);
 	sz--;
     }
-    sp->SCp.ptr=(char *)((unsigned long)sp->SCp.buffer->dvma_address);
-*/
-}    
-
-static void dma_mmu_release_scsi_one (struct NCR_ESP *esp, Scsi_Cmnd *sp)
-{
-/*
-    vdma_free(sp->SCp.have_data_in);
-*/
-}
-
-static void dma_mmu_release_scsi_sgl (struct NCR_ESP *esp, Scsi_Cmnd *sp)
-{
-/*
-    int sz = sp->use_sg - 1;
-    struct mmu_sglist *sg = (struct mmu_sglist *)sp->buffer;
-			
-    while(sz >= 0) {
-	vdma_free(sg[sz].dvma_addr);
-	sz--;
-    }
-*/
-}
-
-static void dma_advance_sg (Scsi_Cmnd *sp)
-{
-/*
-    sp->SCp.ptr = (char *)((unsigned long)sp->SCp.buffer->dvma_address);
-*/
-}
-
-#define JAZZ_HDC_LED   0xe000d100 /* FIXME, find correct address */
-
-static void dma_led_off(struct NCR_ESP *esp)
-{
-#if 0    
-    *(unsigned char *)JAZZ_HDC_LED = 0;
-#endif    
+	sp->SCp.ptr = (char *) ((unsigned long) sp->SCp.buffer->dvma_address);
 }
 
-static void dma_led_on(struct NCR_ESP *esp)
+static void dma_advance_sg(Scsi_Cmnd * sp)
 {    
-#if 0    
-    *(unsigned char *)JAZZ_HDC_LED = 1;
-#endif    
+	sp->SCp.ptr = (char *) ((unsigned long) sp->SCp.buffer->dvma_address);
 }
diff --git a/drivers/scsi/dec_esp.h b/drivers/scsi/dec_esp.h
index 738b90356..15a7bc14b 100644
--- a/drivers/scsi/dec_esp.h
+++ b/drivers/scsi/dec_esp.h
@@ -1,6 +1,6 @@
 /* dec_esp.h: Defines and structures for the JAZZ SCSI driver.
  *
- * Copyright (C) 1998 Harald Koerfgen
+ * DECstation changes Copyright (C) 1998 Harald Koerfgen
  *
  * based on jazz_esp.h:
  * Copyright (C) 1997 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
@@ -39,4 +39,4 @@ extern int esp_proc_info(char *buffer, char **start, off_t offset, int length,
 		cmd_per_lun:    1,				\
 		use_clustering: DISABLE_CLUSTERING, }
 
-#endif /* JAZZ_DEC_H */
+#endif /* DEC_ESP_H */
diff --git a/drivers/tc/Makefile b/drivers/tc/Makefile
index b1f4c4644..701214ea5 100644
--- a/drivers/tc/Makefile
+++ b/drivers/tc/Makefile
@@ -14,8 +14,20 @@ ALL_SUB_DIRS :=
 L_TARGET := tc.a
 L_OBJS   := tc.o
 
+# Nasty trick as nobody references tcsyms.o, but we still want it linked.
+# Stolen from pci Makefile
+ifeq ($(CONFIG_MODULES),y)
+O_TARGET = tc_syms.o
+OX_OBJS  = tcsyms.o
+O_OBJS   = tc.o
+L_OBJS   := tc_syms.o
+else
+L_OBJS   := tc.o
+endif
+
 ifdef CONFIG_ZS
 L_OBJS   += zs.o
 endif
 
 include $(TOPDIR)/Rules.make
+
diff --git a/drivers/tc/tc.c b/drivers/tc/tc.c
index 36183ff9c..c5e3d4c6b 100644
--- a/drivers/tc/tc.c
+++ b/drivers/tc/tc.c
@@ -135,19 +135,25 @@ __initfunc(static void tc_probe(unsigned long startaddr, unsigned long size, int
 			switch (slot) {
 			case 0:
 				tc_bus[slot].interrupt = TC0;
+				break;
 			case 1:
 				tc_bus[slot].interrupt = TC1;
+				break;
 			case 2:
 				tc_bus[slot].interrupt = TC2;
+				break;
 			/*
 			 * Yuck! DS5000/200 onboard devices
 			 */
 			case 5:
 				tc_bus[slot].interrupt = SCSI_INT;
+				break;
 			case 6:
 				tc_bus[slot].interrupt = ETHER;
+				break;
 			default:
 				tc_bus[slot].interrupt = -1;
+				break;
 			}	
 		}
 	}
diff --git a/drivers/tc/zs.c b/drivers/tc/zs.c
index 3dbb837a2..887fea87f 100644
--- a/drivers/tc/zs.c
+++ b/drivers/tc/zs.c
@@ -42,7 +42,6 @@
 #include <asm/segment.h>
 #include <asm/bitops.h>
 #include <asm/uaccess.h>
-#include <asm/wbflush.h>
 #include <asm/dec/interrupts.h>
 #include <asm/dec/machtype.h>
 #include <asm/dec/tc.h>
@@ -196,7 +195,7 @@ static inline unsigned char read_zsreg(struct dec_zschannel *channel,
 
 	if (reg != 0) {
 		*channel->control = reg & 0xf;
-		wbflush(); RECOVERY_DELAY;
+		RECOVERY_DELAY;
 	}
 	retval = *channel->control;
 	RECOVERY_DELAY;
@@ -208,10 +207,10 @@ static inline void write_zsreg(struct dec_zschannel *channel,
 {
 	if (reg != 0) {
 		*channel->control = reg & 0xf;
-		wbflush(); RECOVERY_DELAY;
+		RECOVERY_DELAY;
 	}
 	*channel->control = value;
-	wbflush(); RECOVERY_DELAY;
+	RECOVERY_DELAY;
 	return;
 }
 
@@ -228,7 +227,7 @@ static inline void write_zsdata(struct dec_zschannel *channel,
 				unsigned char value)
 {
 	*channel->data = value;
-	wbflush(); RECOVERY_DELAY;
+	RECOVERY_DELAY;
 	return;
 }
 
@@ -1830,7 +1829,7 @@ zs_console_putchar(struct dec_serial *info, char ch)
 	while (!(*(info->zs_channel->control) & Tx_BUF_EMP) && --loops)
 		RECOVERY_DELAY;
 	*(info->zs_channel->data) = ch;
-	wbflush(); RECOVERY_DELAY;
+	RECOVERY_DELAY;
 
 	restore_flags(flags);
 }
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h
index 5f99727cc..524e94b68 100644
--- a/include/asm-mips/dec/interrupts.h
+++ b/include/asm-mips/dec/interrupts.h
@@ -23,17 +23,18 @@
  * Interrupts before the TC Interrupts.
  */
 #define CLOCK 	0
-#define SCSI_INT	1
-#define ETHER	2
-#define SERIAL	3
-#define TC0	4
-#define TC1	5
-#define TC2	6
-#define MEMORY	7
-#define FPU	8
-#define HALT	9
+#define SCSI_DMA_INT 	1
+#define SCSI_INT	2
+#define ETHER		3
+#define SERIAL		4
+#define TC0		5
+#define TC1		6
+#define TC2		7
+#define MEMORY		8
+#define FPU		9
+#define HALT		10
 
-#define NR_INTS	10
+#define NR_INTS	11
 
 #ifndef _LANGUAGE_ASSEMBLY
 /*
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
index a2044782e..6c0b42b3e 100644
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ b/include/asm-mips/dec/ioasic_addrs.h
@@ -58,10 +58,25 @@
 #define SIMR		0x120			/* System Interrupt Mask Register */
 
 /*
- * These come from mach, meaning unkown	yet
+ * Handle partial word SCSI DMA transfers
  */
 #define	SCSI_SCR	0x1b0
 #define	SCSI_SDR0	0x1c0
 #define	SCSI_SDR1	0x1d0
 
+/*
+ * DMA defines for the System Support Register
+ */
+#define LANCE_DMA_EN	(1UL<<16)			/* LANCE DMA enable */
+#define SCSI_DMA_EN	(1UL<<17)			/* SCSI DMA enable */
+#define SCSI_DMA_DIR	(1UL<<18)			/* SCSI DMA direction */
+#define ISDN_REC_DMA_EN (1UL<<19)			/* ISDN receive DMA enable */
+#define ISDN_TRN_DMA_EN (1UL<<20)			/* ISDN transmit DMA enable */
+#define FLOPPY_DMA_EN	(1UL<<21)			/* Floppy DMA enable */
+#define FLOPPY_DMA_DIR	(1UL<<22)			/* Floppy DMA direction */
+#define SCC1A_DMA_EN	(1UL<<28)			/* SCC1 Channel A DMA enable */
+#define SCC1B_DMA_EN	(1UL<<29)			/* SCC1 Channel B DMA enable */
+#define SCC0A_DMA_EN	(1UL<<30)			/* SCC0 Channel A DMA enable */
+#define SCC0B_DMA_EN	(1UL<<31)			/* Scc0 Channel B DMA enable */
+
 #endif
diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h
index e1f61f1cb..e28e334b2 100644
--- a/include/asm-mips/dec/ioasic_ints.h
+++ b/include/asm-mips/dec/ioasic_ints.h
@@ -86,8 +86,8 @@
 			SCC0_RECV_HALFPAGE | SCC0_RECV_PAGOVRRUN | \
 			SCC0_CHIP)
 
-#define SCSI_INTS	(SCSI_PTR_LOADED | SCSI_PAGOVRRUN | \
-			SCSI_DMA_MEMRDERR | SCSI_CHIP)
+#define SCSI_DMA_INTS	(/* SCSI_PTR_LOADED | */ SCSI_PAGOVRRUN | \
+			SCSI_DMA_MEMRDERR)
 
 #define KMIN_SCSI_INTS	(SCSI_PTR_LOADED | SCSI_PAGOVRRUN | \
 			SCSI_DMA_MEMRDERR | SCSI_CHIP | KMIN_SCSI_FIFO)
@@ -106,3 +106,4 @@
 #define XINE_DTOP_INTS	(MAXINE_DTOP_TRANS | DTOP_RECV | \
 			ISDN_TRANS_PTR_LOADED | ISDN_RECV_PTR_LOADED | \
 			ISDN_DMA_MEMRDERR)
+