Bunch more patches from MIPS.

27 files changed, 692 insertions, 513 deletions

diff --git a/arch/mips/config.in b/arch/mips/config.in
index c2367d8c4..374cbb5de 100644
--- a/arch/mips/config.in
+++ b/arch/mips/config.in
@@ -89,12 +89,13 @@ if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
 fi
 if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
    define_bool CONFIG_PCI y
-   define_bool CONFIG_ISA n
+   define_bool CONFIG_SWAP_IO_SPACE y
 fi
 if [ "$CONFIG_MIPS_MALTA" = "y" ]; then
    define_bool CONFIG_I8259 y
    define_bool CONFIG_PCI y
-   define_bool CONFIG_ISA n
+   define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
+   define_bool CONFIG_SWAP_IO_SPACE y
 fi
 if [ "$CONFIG_PMC_CP7000" = "y" ]; then
    define_bool CONFIG_PCI y
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 31f906ef2..368300cf1 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -237,6 +237,8 @@ static inline void cpu_probe(void)
 		mips_cpu.options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 
 		                   MIPS_CPU_DIVEC;
 		mips_cpu.tlbsize = 48;
+		mips_cpu.icache.ways = 2;
+		mips_cpu.dcache.ways = 2;
 		break;
 	case PRID_IMP_R6000:
 		mips_cpu.cputype = CPU_R6000;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 7b953e94f..b6e1f7a6c 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -5,6 +5,14 @@
  * This file contains the time handling details for PC-style clocks as
  * found in some MIPS systems.
  */
+/**************************************************************************
+ *  9 Nov, 2000.
+ *  Changed init_cycle_counter() routine, use the mips_cpu structure.
+ *
+ *  Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips
+ *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *************************************************************************/
+
 #include <linux/config.h>
 #include <linux/errno.h>
 #include <linux/init.h>
@@ -449,42 +457,8 @@ char cyclecounter_available;
 
 static inline void init_cycle_counter(void)
 {
-	switch(mips_cpu.cputype) {
-	case CPU_UNKNOWN:
-	case CPU_R2000:
-	case CPU_R3000:
-	case CPU_R3000A:
-	case CPU_R3041:
-	case CPU_R3051:
-	case CPU_R3052:
-	case CPU_R3081:
-	case CPU_R3081E:
-	case CPU_R6000:
-	case CPU_R6000A:
-	case CPU_R8000:		/* Not shure about that one, play safe */
-		cyclecounter_available = 0;
-		break;
-	case CPU_R4000PC:
-	case CPU_R4000SC:
-	case CPU_R4000MC:
-	case CPU_R4200:
-	case CPU_R4400PC:
-	case CPU_R4400SC:
-	case CPU_R4400MC:
-	case CPU_R4600:
-	case CPU_R10000:
-	case CPU_R4300:
-	case CPU_R4650:
-	case CPU_R4700:
-	case CPU_R5000:
-	case CPU_R5432:
-	case CPU_R5000A:
-	case CPU_R4640:
-	case CPU_NEVADA:
-	case CPU_RM7000:
-		cyclecounter_available = 1;
-		break;
-	}
+	if(mips_cpu.options & MIPS_CPU_COUNTER) cyclecounter_available = 1;
+	else cyclecounter_available = 0;
 }
 
 struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0,
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d55619720..d3ea588f0 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -790,6 +790,7 @@ void __init trap_init(void)
 	extern char except_vec0_r4600, except_vec0_r2300;
 	extern char except_vec1_generic, except_vec2_generic;
 	extern char except_vec3_generic, except_vec3_r4000;
+	extern char except_vec_ejtag_debug;
 	unsigned long i;
 
 	if(mips_machtype == MACH_MIPS_MAGNUM_4000 ||
@@ -810,6 +811,12 @@ void __init trap_init(void)
 	for(i = 0; i <= 31; i++)
 		(void)set_except_vector(i, handle_reserved);
 
+	/* 
+	 * Copy the EJTAG debug exception vector handler code to it's final 
+	 * destination.
+	 */
+	memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80);
+
 	/*
 	 * Only some CPUs have the watch exceptions or a dedicated
 	 * interrupt vector.
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 80d5ef652..8ff004b55 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -33,6 +33,7 @@
 #include <asm/irq.h>
 #include <asm/mips-boards/atlas.h>
 #include <asm/mips-boards/atlasint.h>
+#include <asm/gdb-stub.h>
 
 
 struct atlas_ictrl_regs *atlas_hw0_icregs
@@ -41,6 +42,15 @@ struct atlas_ictrl_regs *atlas_hw0_icregs
 extern asmlinkage void mipsIRQ(void);
 extern void do_IRQ(int irq, struct pt_regs *regs);
 
+unsigned long spurious_count = 0;
+irq_desc_t irq_desc[NR_IRQS];
+
+#if 0
+#define DEBUG_INT(x...) printk(x)
+#else
+#define DEBUG_INT(x...)
+#endif
+
 void disable_atlas_irq(unsigned int irq_nr)
 {
 	atlas_hw0_icregs->intrsten = (1 << irq_nr);
@@ -78,9 +88,79 @@ static struct hw_interrupt_type atlas_irq_type = {
 	NULL
 };
 
+int get_irq_list(char *buf)
+{
+	int i, len = 0;
+	int num = 0;
+	struct irqaction *action;
+
+	for (i = 0; i < ATLASINT_END; i++, num++) {
+		action = irq_desc[i].action;
+		if (!action) 
+			continue;
+		len += sprintf(buf+len, "%2d: %8d %c %s",
+			num, kstat.irqs[0][num],
+			(action->flags & SA_INTERRUPT) ? '+' : ' ',
+			action->name);
+		for (action=action->next; action; action = action->next) {
+			len += sprintf(buf+len, ",%s %s",
+				(action->flags & SA_INTERRUPT) ? " +" : "",
+				action->name);
+		}
+		len += sprintf(buf+len, " [hw0]\n");
+	}
+	return len;
+}
+
+int request_irq(unsigned int irq, 
+		void (*handler)(int, void *, struct pt_regs *),
+		unsigned long irqflags, 
+		const char * devname,
+		void *dev_id)
+{  
+        struct irqaction *action;
+
+	DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname);
+
+	if (irq >= ATLASINT_END)
+		return -EINVAL;
+	if (!handler)
+		return -EINVAL;
+
+	action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
+	if(!action)
+		return -ENOMEM;
+
+	action->handler = handler;
+	action->flags = irqflags;
+	action->mask = 0;
+	action->name = devname;
+	action->dev_id = dev_id;
+	action->next = 0;
+	irq_desc[irq].action = action;
+	enable_atlas_irq(irq);
+
+	return 0;
+}
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+	struct irqaction *action;
+
+	if (irq >= ATLASINT_END) {
+		printk("Trying to free IRQ%d\n",irq);
+		return;
+	}
+
+	action = irq_desc[irq].action;
+	irq_desc[irq].action = NULL;
+	disable_atlas_irq(irq);
+	kfree(action);
+}
+
 static inline int ls1bit32(unsigned int x)
 {
-	int b = 32, s;
+	int b = 31, s;
 
 	s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
 	s =  8; if (x <<  8 == 0) s = 0; b -= s; x <<= s;
@@ -93,8 +173,9 @@ static inline int ls1bit32(unsigned int x)
 
 void atlas_hw0_irqdispatch(struct pt_regs *regs)
 {
+	struct irqaction *action;
 	unsigned long int_status;
-	int irq;
+	int irq, cpu = smp_processor_id();
 
 	int_status = atlas_hw0_icregs->intstatus; 
 
@@ -103,15 +184,45 @@ void atlas_hw0_irqdispatch(struct pt_regs *regs)
 		return;
 
 	irq = ls1bit32(int_status);
-	do_IRQ(irq, regs);
+	action = irq_desc[irq].action;
+
+	DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
+
+	/* if action == NULL, then we don't have a handler for the irq */
+	if ( action == NULL ) {
+		printk("No handler for hw0 irq: %i\n", irq);
+		spurious_count++;
+		return;
+	}
+
+	irq_enter(cpu, irq);
+	kstat.irqs[0][irq]++;
+	action->handler(irq, action->dev_id, regs);
+	irq_exit(cpu, irq);
+
+	return;		
+}
+
+unsigned long probe_irq_on (void)
+{
+	return 0;
 }
 
+
+int probe_irq_off (unsigned long irqs)
+{
+	return 0;
+}
+
+#ifdef CONFIG_REMOTE_DEBUG
+extern void breakpoint(void);
+extern int remote_debug;
+#endif
+
 void __init init_IRQ(void)
 {
 	int i;
 
-	init_generic_irq();
-
 	/* 
 	 * Mask out all interrupt by writing "1" to all bit position in 
 	 * the interrupt reset reg. 
@@ -129,9 +240,7 @@ void __init init_IRQ(void)
 	}
 
 #ifdef CONFIG_REMOTE_DEBUG
-	/* If local serial I/O used for debug port, enter kgdb at once */
-	/* Otherwise, this will be done after the SAA9730 is up*/
-	if (remote_debug && !kgdb_on_pci) {
+	if (remote_debug) {
 		set_debug_traps();
 		breakpoint();
 	}
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index d11a4d8ac..42546a93d 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -40,8 +40,7 @@ char serial_console[20];
 extern void rs_kgdb_hook(int);
 extern void saa9730_kgdb_hook(void);
 extern void breakpoint(void);
-static int remote_debug = 0;
-static int kgdb_on_pci = 0;
+int remote_debug = 0;
 #endif
 
 extern struct rtc_ops atlas_rtc_ops;
@@ -60,7 +59,6 @@ void __init atlas_setup(void)
 #endif
 	char *argptr;
 
-	mips_io_port_base = KSEG1;
 	ioport_resource.end = 0x7fffffff;
 
 #ifdef CONFIG_SERIAL_CONSOLE
@@ -97,7 +95,6 @@ void __init atlas_setup(void)
 			saa9730_kgdb_hook();
 			putDebugChar = saa9730_putDebugChar;
 			getDebugChar = saa9730_getDebugChar;
-			kgdb_on_pci = 1;
 		}
 
 		prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
@@ -109,19 +106,10 @@ void __init atlas_setup(void)
 #endif
 	argptr = prom_getcmdline();
 
+	if ((argptr = strstr(argptr, "nofpu")) != NULL)
+		mips_cpu.options &= ~MIPS_CPU_FPU;
+
 	rtc_ops = &atlas_rtc_ops;
 
 	mips_reboot_setup();
-
-	/*
-	 * Setup the North bridge to do Master byte-lane swapping when
-	 * running in bigendian.
-	 * Be careful to use prom_printf after this.
-	 */
-#if defined(__MIPSEL__)
-	GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
-	         GT_PCI0_CMD_SBYTESWAP_BIT);
-#else
-	GT_WRITE(GT_PCI0_CMD_OFS, 0);
-#endif
 }
diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile
index c76f6fd46..8a2f0e6d8 100644
--- a/arch/mips/mips-boards/generic/Makefile
+++ b/arch/mips/mips-boards/generic/Makefile
@@ -39,4 +39,8 @@ O_TARGET := mipsboards.o
 O_OBJS := mipsIRQ.o pci.o reset.o display.o init.o memory.o printf.o \
 	  cmdline.o time.o
 
+ifdef CONFIG_REMOTE_DEBUG
+O_OBJS += gdb_hook.o
+endif
+
 include $(TOPDIR)/Rules.make
diff --git a/arch/mips/mips-boards/generic/gdb_hook.c b/arch/mips/mips-boards/generic/gdb_hook.c
new file mode 100644
index 000000000..bb14774d9
--- /dev/null
+++ b/arch/mips/mips-boards/generic/gdb_hook.c
@@ -0,0 +1,202 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * This is the interface to the remote debugger stub.
+ *
+ */
+
+#include <linux/serialP.h>
+#include <linux/serial_reg.h>
+
+#include <asm/serial.h>
+#include <asm/io.h>
+
+static struct serial_state rs_table[RS_TABLE_SIZE] = {
+	SERIAL_PORT_DFNS	/* Defined in serial.h */
+};
+
+static struct async_struct kdb_port_info = {0};
+
+
+static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
+{
+	return inb(info->port + offset);
+}
+
+static __inline__ void serial_out(struct async_struct *info, int offset,
+				int value)
+{
+	outb(value, info->port+offset);
+}
+
+void rs_kgdb_hook(int tty_no) {
+	int t;
+	struct serial_state *ser = &rs_table[tty_no];
+
+	kdb_port_info.state = ser;
+	kdb_port_info.magic = SERIAL_MAGIC;
+	kdb_port_info.port = ser->port;
+	kdb_port_info.flags = ser->flags;
+
+	/*
+	 * Clear all interrupts
+	 */
+	serial_in(&kdb_port_info, UART_LSR);
+	serial_in(&kdb_port_info, UART_RX);
+	serial_in(&kdb_port_info, UART_IIR);
+	serial_in(&kdb_port_info, UART_MSR);
+
+	/*
+	 * Now, initialize the UART 
+	 */
+	serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);	/* reset DLAB */
+	if (kdb_port_info.flags & ASYNC_FOURPORT) {
+		kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
+		t = UART_MCR_DTR | UART_MCR_OUT1;
+	} else {
+		kdb_port_info.MCR 
+			= UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
+		t = UART_MCR_DTR | UART_MCR_RTS;
+	}
+
+	kdb_port_info.MCR = t;		/* no interrupts, please */
+	serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
+	
+	/*
+	 * and set the speed of the serial port
+	 * (currently hardwired to 9600 8N1
+	 */
+
+	/* baud rate is fixed to 9600 (is this sufficient?)*/
+	t = kdb_port_info.state->baud_base / 9600;	
+	/* set DLAB */
+	serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
+	serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
+	serial_out(&kdb_port_info, UART_DLM, t >> 8);  /* MS of divisor */
+	/* reset DLAB */
+	serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
+}
+
+int rs_putDebugChar(char c)
+{
+
+	if (!kdb_port_info.state) { 	/* need to init device first */
+		return 0;
+	}
+
+	while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
+		;
+
+	serial_out(&kdb_port_info, UART_TX, c);
+
+	return 1;
+}
+
+char rs_getDebugChar(void)
+{
+	if (!kdb_port_info.state) { 	/* need to init device first */
+		return 0;
+	}
+
+	while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
+		;
+
+	return(serial_in(&kdb_port_info, UART_RX));
+}
+
+
+#ifdef CONFIG_MIPS_ATLAS
+
+#include <asm/mips-boards/atlas.h>
+#include <asm/mips-boards/saa9730_uart.h>
+
+#define INB(a)     inb((unsigned long)a)
+#define OUTB(x,a)  outb(x,(unsigned long)a)
+
+/*
+ * This is the interface to the remote debugger stub
+ * if the Philips part is used for the debug port,
+ * called from the platform setup code.
+ *
+ * PCI init will not have been done yet, we make a
+ * universal assumption about the way the bootloader (YAMON)
+ * have located and set up the chip.
+ */
+static t_uart_saa9730_regmap *kgdb_uart = (void *)(ATLAS_SAA9730_REG + SAA9730_UART_REGS_ADDR);
+
+static int saa9730_kgdb_active = 0;
+
+void saa9730_kgdb_hook(void) 
+{
+        volatile unsigned char t;
+
+        /*
+         * Clear all interrupts
+         */
+	t = INB(&kgdb_uart->Lsr);
+	t += INB(&kgdb_uart->Msr);
+	t += INB(&kgdb_uart->Thr_Rbr);
+	t += INB(&kgdb_uart->Iir_Fcr);
+
+        /*
+         * Now, initialize the UART
+         */
+	/* 8 data bits, one stop bit, no parity */
+	OUTB(SAA9730_LCR_DATA8, &kgdb_uart->Lcr);
+
+        /* baud rate is fixed to 9600 (is this sufficient?)*/
+	OUTB(0, &kgdb_uart->BaudDivMsb); /* HACK - Assumes standard crystal */
+	OUTB(23, &kgdb_uart->BaudDivLsb); /* HACK - known for MIPS Atlas */
+
+	/* Set RTS/DTR active */
+	OUTB(SAA9730_MCR_DTR | SAA9730_MCR_RTS, &kgdb_uart->Mcr);
+	saa9730_kgdb_active = 1;
+}
+
+int saa9730_putDebugChar(char c)
+{
+
+        if (!saa9730_kgdb_active) {     /* need to init device first */
+                return 0;
+        }
+
+        while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_THRE))
+                ;
+	OUTB(c, &kgdb_uart->Thr_Rbr);
+
+        return 1;
+}
+
+char saa9730_getDebugChar(void)
+{
+	char c;
+
+        if (!saa9730_kgdb_active) {     /* need to init device first */
+                return 0;
+        }
+        while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_DR))
+                ;
+
+	c = INB(&kgdb_uart->Thr_Rbr);
+        return(c);
+}
+
+#endif
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 9f8b4dd27..70b6767b3 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -22,7 +22,11 @@
 #include <linux/string.h>
 #include <linux/kernel.h>
 
+#include <asm/io.h>
 #include <asm/mips-boards/prom.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/gt64120.h>
+#include <asm/mips-boards/malta.h>
 
 /* Environment variable */
 typedef struct
@@ -110,11 +114,25 @@ int __init prom_init(int argc, char **argv, char **envp)
 
 	mips_display_message("LINUX");
 
-	setup_prom_printf();
+	/*
+	 * Setup the North bridge to do Master byte-lane swapping when 
+	 * running in bigendian.
+	 */
+#if defined(__MIPSEL__)
+	GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
+		 GT_PCI0_CMD_SBYTESWAP_BIT);
+#else
+	GT_WRITE(GT_PCI0_CMD_OFS, 0);
+#endif
+
+#if defined(CONFIG_MIPS_MALTA)
+	mips_io_port_base = MALTA_PORT_BASE;
+#else
+	mips_io_port_base = KSEG1;
+#endif
+	setup_prom_printf(0);
 	prom_printf("\nLINUX started...\n");
-
 	prom_init_cmdline();
-
 	prom_meminit();
 
 	return 0;
diff --git a/arch/mips/mips-boards/generic/printf.c b/arch/mips/mips-boards/generic/printf.c
index 3c21ae8bf..4f3f6e845 100644
--- a/arch/mips/mips-boards/generic/printf.c
+++ b/arch/mips/mips-boards/generic/printf.c
@@ -25,31 +25,116 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <asm/addrspace.h>
-#include <asm/mips-boards/generic.h>
+#include <linux/serialP.h>
+#include <linux/serial_reg.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/serial.h>
 
-static char ppbuf[1024];
 
-void (*prom_print_str)(unsigned int out, char *s, int len);
+#ifdef CONFIG_MIPS_ATLAS 
+/* 
+ * Atlas registers are memory mapped on 64-bit aligned boundaries and 
+ * only word access are allowed.
+ * When reading the UART 8 bit registers only the LSB are valid.
+ */
+unsigned int atlas_serial_in(struct async_struct *info, int offset)
+{
+	return (*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) & 0xff);
+}
+
+void atlas_serial_out(struct async_struct *info, int offset, int value)
+{
+	*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) = value;
+}
+
+#define serial_in  atlas_serial_in
+#define serial_out atlas_serial_out
+
+#else
 
+static unsigned int serial_in(struct async_struct *info, int offset)
+{
+	return inb(info->port + offset);
+}
 
-void __init setup_prom_printf(void)
+static void serial_out(struct async_struct *info, int offset,
+				int value)
 {
-        prom_print_str = (void *)*(unsigned int *)YAMON_PROM_PRINT_ADDR;
+	outb(value, info->port + offset);
 }
+#endif
+
+static struct serial_state rs_table[] = {
+	SERIAL_PORT_DFNS	/* Defined in serial.h */
+};
+
+/*
+ * Hooks to fake "prom" console I/O before devices 
+ * are fully initialized. 
+ */
+static struct async_struct prom_port_info = {0};
+
+void __init setup_prom_printf(int tty_no) {
+	struct serial_state *ser = &rs_table[tty_no];
+
+	prom_port_info.state = ser;
+	prom_port_info.magic = SERIAL_MAGIC;
+	prom_port_info.port = ser->port;
+	prom_port_info.flags = ser->flags;
+
+	/* No setup of UART - assume YAMON left in sane state */
+}
+
+int putPromChar(char c)
+{
+        if (!prom_port_info.state) { 	/* need to init device first */
+		return 0;
+	}
+
+	while ((serial_in(&prom_port_info, UART_LSR) & UART_LSR_THRE) == 0)
+		;
+
+	serial_out(&prom_port_info, UART_TX, c);
+
+	return 1;
+}
+
+char getPromChar(void)
+{
+	if (!prom_port_info.state) { 	/* need to init device first */
+		return 0;
+	}
+
+	while (!(serial_in(&prom_port_info, UART_LSR) & 1))
+		;
+
+	return(serial_in(&prom_port_info, UART_RX));
+}
+
+static char buf[1024];
 
 void __init prom_printf(char *fmt, ...)
 {
-        va_list args;
-	int len;
+	va_list args;
+	int l;
+	char *p, *buf_end;
+	long flags;
+
+	int putPromChar(char);
 
-        va_start(args, fmt);
-        vsprintf(ppbuf, fmt, args);
-	len = strlen(ppbuf);
+	/* Low level, brute force, not SMP safe... */
+	save_and_cli(flags);
+	va_start(args, fmt);
+	l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
+	va_end(args);
 
-	prom_print_str(0, ppbuf, len);
+	buf_end = buf + l;
 
-        va_end(args);
-        return;
-        
+	for (p = buf; p < buf_end; p++) {
+		/* Crude cr/nl handling is better than none */
+		if(*p == '\n')putPromChar('\r');
+		putPromChar(*p);
+	}
+	restore_flags(flags);
 }
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 8f90e6413..085fefcdb 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -154,7 +154,7 @@ int get_irq_list(char *buf)
 }
 
 
-static int setup_irq(int irq, struct irqaction * new)
+static int setup_irq(unsigned int irq, struct irqaction * new)
 {
 	int shared = 0;
 	struct irqaction *old, **p;
@@ -316,7 +316,7 @@ void malta_hw0_irqdispatch(struct pt_regs *regs)
 	if ( action == NULL )
 		return;
 
-	irq_enter(cpu);
+	irq_enter(cpu, irq);
 	kstat.irqs[0][irq + 8]++;
 	do {
 	        action->handler(irq, action->dev_id, regs);
@@ -324,7 +324,7 @@ void malta_hw0_irqdispatch(struct pt_regs *regs)
 	} while (action);
 
 	enable_irq(irq);
-	irq_exit(cpu);
+	irq_exit(cpu, irq);
 }
 
 
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index f653ceb9e..944c35e51 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -39,9 +39,6 @@
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
-#ifdef CONFIG_BLK_DEV_IDE
-#include <asm/ide.h>
-#endif
 #ifdef CONFIG_BLK_DEV_FD
 #include <asm/floppy.h>
 #endif
@@ -57,7 +54,6 @@ extern void set_debug_traps(void);
 extern void rs_kgdb_hook(int);
 extern void breakpoint(void);
 static int remote_debug = 0;
-static int kgdb_on_pci = 0;
 #endif
 
 #ifdef CONFIG_BLK_DEV_IDE
@@ -86,7 +82,7 @@ static void __init malta_irq_setup(void)
   	maltaint_init();
 
 #ifdef CONFIG_REMOTE_DEBUG
-	if (remote_debug && !kgdb_on_pci) {
+	if (remote_debug) {
 		set_debug_traps();
 		breakpoint(); 
 	}
@@ -106,7 +102,6 @@ void __init malta_setup(void)
 	int i;
 
 	irq_setup = malta_irq_setup;
-	mips_io_port_base = MALTA_PORT_BASE;
 
 	/* Request I/O space for devices used on the Malta board. */
 	for (i = 0; i < STANDARD_IO_RESOURCES; i++)
@@ -155,6 +150,10 @@ void __init malta_setup(void)
 		/* Breakpoints and stuff are in malta_irq_setup() */
 	}
 #endif
+
+	argptr = prom_getcmdline();
+	if ((argptr = strstr(argptr, "nofpu")) != NULL)
+		mips_cpu.options &= ~MIPS_CPU_FPU;
 		
 	rtc_ops = &malta_rtc_ops;
 #ifdef CONFIG_BLK_DEV_IDE
@@ -164,16 +163,4 @@ void __init malta_setup(void)
         fd_ops = &std_fd_ops;
 #endif
 	mips_reboot_setup();
-
-	/*
-	 * Setup the North bridge to do Master byte-lane swapping when
-	 * running in bigendian.
-	 * Be careful to use prom_printf after this.
-	 */
-#if defined(__MIPSEL__)
-	GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
-	         GT_PCI0_CMD_SBYTESWAP_BIT);
-#else
-	GT_WRITE(GT_PCI0_CMD_OFS, 0);
-#endif
 }
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 7035b1574..cf0775cce 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -6,6 +6,14 @@
  * Copyright (C) 1994 - 2000 by Ralf Baechle
  * Copyright (C) 2000 Silicon Graphics, Inc.
  */
+/**************************************************************************
+ *  9 Nov, 2000.
+ *  Use mips_cpu structure.
+ *
+ *  Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *************************************************************************/
+
 #include <linux/config.h>
 #include <linux/init.h>
 #include <linux/signal.h>
@@ -121,17 +129,9 @@ static inline unsigned long setup_zero_pages(void)
 {
 	unsigned long order, size;
 	struct page *page;
-
-	switch (mips_cpu.cputype) {
-	case CPU_R4000SC:
-	case CPU_R4000MC:
-	case CPU_R4400SC:
-	case CPU_R4400MC:
-		order = 3;
-		break;
-	default:
-		order = 0;
-	}
+	
+	if(mips_cpu.options & MIPS_CPU_VCE) order = 3;
+	else order = 0;
 
 	empty_zero_page = __get_free_pages(GFP_KERNEL, order);
 	if (!empty_zero_page)
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 1136cc0f4..57d52cd88 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -54,6 +54,12 @@ ifeq ($(ARCH),s390)
   SERIAL   =
 endif
 
+ifeq ($(ARCH),mips)
+  ifneq ($(CONFIG_PC_KEYB),y)
+    KEYBD    =
+  endif
+endif
+
 ifeq ($(ARCH),m68k)
    ifdef CONFIG_AMIGA
       KEYBD = amikeyb.o
diff --git a/drivers/char/serial.c b/drivers/char/serial.c
index 85da92470..65912962b 100644
--- a/drivers/char/serial.c
+++ b/drivers/char/serial.c
@@ -86,6 +86,16 @@ static char *serial_revdate = "2000-08-09";
  * 		Check the magic number for the async_structure where
  * 		ever possible.
  */
+/**************************************************************************
+ *  23 Oct, 2000.
+ *  Added suport for MIPS Atlas board.
+ *  
+ *  23 Nov, 2000.
+ *  Hooks for serial kernel debug port support added.
+ *
+ *  Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *************************************************************************/
 
 #include <linux/config.h>
 #include <linux/version.h>
@@ -402,6 +412,22 @@ static inline int serial_paranoia_check(struct async_struct *info,
 	return 0;
 }
 
+#ifdef CONFIG_MIPS_ATLAS 
+extern unsigned int atlas_serial_in(struct async_struct *info, int offset);
+extern void atlas_serial_out(struct async_struct *info, int offset, int value);
+
+static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
+{
+        return (atlas_serial_in(info, offset) & 0xff);   
+}
+
+static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
+{
+        atlas_serial_out(info, offset, value);
+}
+
+#else
+
 static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
 {
 	switch (info->io_type) {
@@ -445,6 +471,8 @@ static _INLINE_ void serial_out(struct async_struct *info, int offset,
 		outb(value, info->port+offset);
 	}
 }
+#endif
+
 
 /*
  * We used to support using pause I/O for certain machines.  We
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 976dd5781..a2c4802c0 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -12,6 +12,14 @@
  *
  *	This driver is for PCnet32 and PCnetPCI based ethercards
  */
+/**************************************************************************
+ *  23 Oct, 2000.
+ *  Fixed a few bugs, related to running the controller in 32bit mode.
+ *
+ *  Carsten Langgaard, carstenl@mips.com
+ *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *************************************************************************/
 
 static const char *version = "pcnet32.c:v1.25kf 26.9.1999 tsbogend@alpha.franken.de\n";
 
@@ -421,7 +429,7 @@ static void pcnet32_dwio_reset (unsigned long addr)
 static int pcnet32_dwio_check (unsigned long addr)
 {
     outl (88, addr+PCNET32_DWIO_RAP);
-    return (inl (addr+PCNET32_DWIO_RAP) == 88);
+    return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
 }
 
 static struct pcnet32_access pcnet32_dwio = {
@@ -528,11 +536,13 @@ pcnet32_probe1(unsigned long ioaddr, unsigned char irq_line, int shared, int car
     pcnet32_dwio_reset(ioaddr);
     pcnet32_wio_reset(ioaddr);
 
-    if (pcnet32_wio_read_csr (ioaddr, 0) == 4 && pcnet32_wio_check (ioaddr)) {
-	a = &pcnet32_wio;
+    /* Important to do the check for dwio mode first. */
+    if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
+        a = &pcnet32_dwio;
     } else {
-	if (pcnet32_dwio_read_csr (ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
-	    a = &pcnet32_dwio;
+        if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && 
+	    pcnet32_wio_check(ioaddr)) {
+	    a = &pcnet32_wio;
 	} else
 	    return -ENODEV;
     }
diff --git a/drivers/net/saa9730.c b/drivers/net/saa9730.c
index 43063a1c1..17d7b6b3d 100644
--- a/drivers/net/saa9730.c
+++ b/drivers/net/saa9730.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include <linux/init.h>
 #include <linux/netdevice.h>
 #include <linux/delay.h>
 #include <linux/etherdevice.h>
@@ -45,8 +46,8 @@ int lan_saa9730_debug;
 /* Non-zero only if the current card is a PCI with BIOS-set IRQ. */
 static unsigned int pci_irq_line = 0;
 
-#define INL(a)     le32_to_cpu(inl((unsigned long)a))
-#define OUTL(x,a)  outl(cpu_to_le32(x),(unsigned long)a)
+#define INL(a)     inl((unsigned long)a)
+#define OUTL(x,a)  outl(x,(unsigned long)a)
 
 static void evm_saa9730_enable_lan_int(struct lan_saa9730_private *lp)
 {
@@ -1003,12 +1004,7 @@ static int lan_saa9730_init(struct net_device *dev, int ioaddr, int irq)
 	/* Set SAA9730 EVM base address. */
 	lp->evm_saa9730_regs = (t_evm_saa9730_regmap *) (ioaddr +
 							 SAA9730_EVM_REGS_ADDR);
-#ifdef CONFIG_REMOTE_DEBUG
-	if (saa9730_kgdb_active)
-		saa9730_kgdb_setup((t_uart_saa9730_regmap *) (ioaddr
-							      +
-							      SAA9730_UART_REGS_ADDR));
-#endif
+
 	/* Allocate LAN RX/TX frame buffer space. */
 	if (lan_saa9730_allocate_buffers(lp))
 		return -1;
diff --git a/drivers/net/saa9730.h b/drivers/net/saa9730.h
index cad254386..f71fadc89 100644
--- a/drivers/net/saa9730.h
+++ b/drivers/net/saa9730.h
@@ -328,46 +328,6 @@ struct evm_saa9730_regmap {
 typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;
 
 
-/* The SAA9730 UART register map, as seen via the PCI bus */
-
-#define SAA9730_UART_REGS_ADDR	0x21800
-
-struct uart_saa9730_regmap {
-	volatile unsigned char Thr_Rbr;
-	volatile unsigned char Ier;
-	volatile unsigned char Iir_Fcr;
-	volatile unsigned char Lcr;
-	volatile unsigned char Mcr;
-	volatile unsigned char Lsr;
-	volatile unsigned char Msr;
-	volatile unsigned char Scr;
-	volatile unsigned char BaudDivLsb;
-	volatile unsigned char BaudDivMsb;
-	volatile unsigned char Junk0;
-	volatile unsigned char Junk1;
-	volatile unsigned int Config;	/* 0x2180c */
-	volatile unsigned int TxStart;	/* 0x21810 */
-	volatile unsigned int TxLength;	/* 0x21814 */
-	volatile unsigned int TxCounter;	/* 0x21818 */
-	volatile unsigned int RxStart;	/* 0x2181c */
-	volatile unsigned int RxLength;	/* 0x21820 */
-	volatile unsigned int RxCounter;	/* 0x21824 */
-};
-typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
-
-/*
- * Only a subset of the UART control bits are defined here,
- * enough to make the serial debug port work.
- */
-
-#define SAA9730_LCR_DATA8	0x03
-
-#define SAA9730_MCR_DTR		0x01
-#define SAA9730_MCR_RTS		0x02
-
-#define SAA9730_LSR_DR		0x01
-#define SAA9730_LSR_THRE	0x20
-
 struct lan_saa9730_private {
 	/* Pointer for the SAA9730 LAN controller register set. */
 	t_lan_saa9730_regmap *lan_saa9730_regs;
diff --git a/drivers/scsi/sym53c8xx_defs.h b/drivers/scsi/sym53c8xx_defs.h
index 0ab0d2745..c2ad1165b 100644
--- a/drivers/scsi/sym53c8xx_defs.h
+++ b/drivers/scsi/sym53c8xx_defs.h
@@ -53,6 +53,13 @@
 **
 *******************************************************************************
 */
+/**************************************************************************
+ *  23 Oct, 2000.
+ *  Added support for MIPS big endian systems.
+ *
+ *  Carsten Langgaard, carstenl@mips.com
+ *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *************************************************************************/
 
 #ifndef SYM53C8XX_DEFS_H
 #define SYM53C8XX_DEFS_H
@@ -399,8 +406,17 @@
 #define	readl_l2b	readl
 #define	writew_b2l	writew
 #define	writel_b2l	writel
+#elif defined(__mips__)
+#define readw_l2b	readw
+#define readl_l2b	readl
+#define writew_b2l	writew
+#define writel_b2l	writel
+#define inw_l2b 	inw
+#define inl_l2b 	inl
+#define outw_b2l	outw
+#define outl_b2l	outl
 #else
-#error	"Support for BIG ENDIAN is only available for PowerPC and SPARC"
+#error	"Support for BIG ENDIAN is only available for PowerPC, SPARC and MIPS"
 #endif
 
 #else	/* little endian */
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
index 1ef59a11d..5d78b6126 100644
--- a/include/asm-mips/gt64120.h
+++ b/include/asm-mips/gt64120.h
@@ -28,23 +28,6 @@
 /*
  * Interrupt Registers
  */
-#define GT_INTRCAUSE_OFS	0xc18
-#define GT_HINTRCAUSE_OFS	0xc98	/* GT64120A only */
-#define GT_INTRMASK_OFS		0xc1c	/* GT64120A only */
-#define GT_HINTRMASK_OFS	0xc9c	/* GT64120A only */
-
-#define GT_PCI0_CFGADDR_OFS	0xcf8
-#define GT_PCI0_CFGDATA_OFS	0xcfc
-#define GT_PCI1_CFGADDR_OFS	0xcf0	/* GT64120A only */
-#define GT_PCI1_CFGDATA_OFS	0xcf4	/* GT64120A only */
-
-#define GT_SDRAM_BM_OFS		0x478
-#define GT_SDRAM_ADDRDECODE_OFS	0x47c
-#define GT_SDRAM_B0_OFS	    	0x44c
-#define GT_SDRAM_B2_OFS		0x454
-#define GT_SDRAM_CFG_OFS	0x448
-#define GT_SDRAM_OPMODE_OFS	0x474
-
 #define GT_SCS10LD_OFS		0x008
 #define GT_SCS10HD_OFS		0x010
 #define GT_SCS32LD_OFS		0x018
@@ -96,14 +79,27 @@
 #define GT_BOOTLD_OFS		0x440
 #define GT_BOOTHD_OFS		0x444
 
+#define GT_SDRAM_B0_OFS	    	0x44c
+#define GT_SDRAM_CFG_OFS	0x448
+#define GT_SDRAM_B2_OFS		0x454
+#define GT_SDRAM_OPMODE_OFS	0x474
+#define GT_SDRAM_BM_OFS		0x478
+#define GT_SDRAM_ADDRDECODE_OFS	0x47c
+
 #define GT_PCI0_CMD_OFS		0xc00	/* GT64120A only */
+#define GT_PCI0_TOR_OFS		0xc04
 #define GT_PCI0_BS_SCS10_OFS    0xc08
 #define GT_PCI0_BS_SCS32_OFS    0xc0c
-#define GT_PCI0_BARE_OFS	0xc3c
-
-#define GT_PCI0_TOR_OFS		0xc04
-
+#define GT_INTRCAUSE_OFS	0xc18
+#define GT_INTRMASK_OFS		0xc1c	/* GT64120A only */
 #define GT_PCI0_IACK_OFS	0xc34
+#define GT_PCI0_BARE_OFS	0xc3c
+#define GT_HINTRCAUSE_OFS	0xc98	/* GT64120A only */
+#define GT_HINTRMASK_OFS	0xc9c	/* GT64120A only */
+#define GT_PCI1_CFGADDR_OFS	0xcf0	/* GT64120A only */
+#define GT_PCI1_CFGDATA_OFS	0xcf4	/* GT64120A only */
+#define GT_PCI0_CFGADDR_OFS	0xcf8
+#define GT_PCI0_CFGDATA_OFS	0xcfc
 
 
 /*
@@ -167,7 +163,9 @@
 /*
  *  Register encodings
  */
-
+#define GT_CPU_ENDIAN_SHF       12
+#define GT_CPU_ENDIAN_MSK       (MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT       GT_CPU_ENDIAN_MSK
 #define GT_CPU_WR_SHF		16
 #define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
 #define GT_CPU_WR_BIT		GT_CPU_WR_MSK
@@ -377,6 +375,18 @@
 #define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
 #define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
 
+#define GT_PCI0_CMD_MBYTESWAP_SHF       0
+#define GT_PCI0_CMD_MBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT       GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF       10
+#define GT_PCI0_CMD_MWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT       GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF       16
+#define GT_PCI0_CMD_SBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT       GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF       11
+#define GT_PCI0_CMD_SWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT       GT_PCI0_CMD_SWORDSWAP_MSK
 
 /*
  *  Misc
diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h
index 9fdf1b75c..3cbfe219c 100644
--- a/include/asm-mips/mips-boards/atlas.h
+++ b/include/asm-mips/mips-boards/atlas.h
@@ -42,7 +42,7 @@
 /*
  * Atlas UART register base.
  */
-#define ATLAS_UART_REGS_BASE    (KSEG1ADDR(0x1f000900))
+#define ATLAS_UART_REGS_BASE    (0x1f000900)
 #define ATLAS_BASE_BAUD ( 3686400 / 16 ) 
 
 /*
@@ -51,5 +51,12 @@
 #define ATLAS_PSUSTBY_REG       (KSEG1ADDR(0x1f000600))
 #define ATLAS_GOSTBY            0x4d
 
+/*
+ * We make a universal assumption about the way the bootloader (YAMON)
+ * have located the Philips SAA9730 chip.
+ * This is not ideal, but is needed for setting up remote debugging as 
+ * soon as possible.
+ */
+#define ATLAS_SAA9730_REG  (KSEG1ADDR(0x08800000))
 
 #endif /* !(_MIPS_ATLAS_H) */
diff --git a/include/asm-mips/mips-boards/gt64120.h b/include/asm-mips/mips-boards/gt64120.h
deleted file mode 100644
index 5b0404cf8..000000000
--- a/include/asm-mips/mips-boards/gt64120.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Register definitions for Galileo 64120 system controller.
- *
- */
-#ifndef GT64120_H
-#define GT64120_H
-
-#define MSK(n)                    ((1 << (n)) - 1)
-
-/************************************************************************
- *  Register offset addresses
- ************************************************************************/
-
-#define GT_CPU_OFS		    0x000
-
-#define GT_INTRCAUSE_OFS	    0xc18
-#define GT_PCI0_CFGADDR_OFS	    0xcf8
-#define GT_PCI0_CFGDATA_OFS	    0xcfc
-#define GT_SDRAM_BM_OFS		    0x478
-#define GT_SDRAM_ADDRDECODE_OFS     0x47c
-#define GT_SDRAM_B0_OFS	    	    0x44c
-#define GT_SDRAM_B2_OFS		    0x454
-#define GT_SDRAM_CFG_OFS	    0x448
-#define GT_SDRAM_OPMODE_OFS	    0x474
-
-#define GT_ISD_OFS		    0x068
-
-#define GT_SCS10LD_OFS		    0x008
-#define GT_SCS10HD_OFS		    0x010
-#define GT_SCS32LD_OFS		    0x018
-#define GT_SCS32HD_OFS		    0x020
-#define GT_CS20LD_OFS		    0x028
-#define GT_CS20HD_OFS		    0x030
-#define GT_CS3BOOTLD_OFS	    0x038
-#define GT_CS3BOOTHD_OFS	    0x040
-#define GT_PCI0IOLD_OFS		    0x048
-#define GT_PCI0IOHD_OFS		    0x050
-#define GT_PCI0M0LD_OFS		    0x058
-#define GT_PCI0M0HD_OFS		    0x060
-#define GT_PCI0M1LD_OFS		    0x080
-#define GT_PCI0M1HD_OFS		    0x088
-#define GT_PCI1IOLD_OFS		    0x090
-#define GT_PCI1IOHD_OFS		    0x098
-#define GT_PCI1M0LD_OFS		    0x0a0
-#define GT_PCI1M0HD_OFS		    0x0a8
-#define GT_PCI1M1LD_OFS		    0x0b0
-#define GT_PCI1M1HD_OFS		    0x0b8
-
-#define GT_SCS0LD_OFS		    0x400	
-#define GT_SCS0HD_OFS		    0x404
-#define GT_SCS1LD_OFS		    0x408
-#define GT_SCS1HD_OFS		    0x40c
-#define GT_SCS2LD_OFS		    0x410
-#define GT_SCS2HD_OFS		    0x414
-#define GT_SCS3LD_OFS		    0x418
-#define GT_SCS3HD_OFS		    0x41c
-#define GT_CS0LD_OFS		    0x420
-#define GT_CS0HD_OFS		    0x424
-#define GT_CS1LD_OFS		    0x428
-#define GT_CS1HD_OFS		    0x42c
-#define GT_CS2LD_OFS		    0x430
-#define GT_CS2HD_OFS		    0x434
-#define GT_CS3LD_OFS		    0x438
-#define GT_CS3HD_OFS		    0x43c
-#define GT_BOOTLD_OFS		    0x440
-#define GT_BOOTHD_OFS		    0x444
-
-#define GT_PCI0_BS_SCS10_OFS	    0xc08
-#define GT_PCI0_BS_SCS32_OFS	    0xc0c
-#define GT_PCI0_BARE_OFS	    0xc3c
-
-#define GT_PCI0_TOR_OFS	            0xc04
-
-#define GT_PCI0_IACK_OFS            0xc34
-
-
-/************************************************************************
- *  Register encodings
- ************************************************************************/
-
-#define GT_CPU_WR_SHF		16
-#define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
-#define GT_CPU_WR_BIT		GT_CPU_WR_MSK
-#define GT_CPU_WR_DXDXDXDX	0
-#define GT_CPU_WR_DDDD		1
-
-
-#define GT_CFGADDR_CFGEN_SHF	31
-#define GT_CFGADDR_CFGEN_MSK	(MSK(1) << GT_CFGADDR_CFGEN_SHF)
-#define GT_CFGADDR_CFGEN_BIT	GT_CFGADDR_CFGEN_MSK
-
-#define GT_CFGADDR_BUSNUM_SHF   16
-#define GT_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_CFGADDR_BUSNUM_SHF)
-
-#define GT_CFGADDR_DEVNUM_SHF	11
-#define GT_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_CFGADDR_DEVNUM_SHF)
-
-#define GT_CFGADDR_FUNCNUM_SHF	8
-#define GT_CFGADDR_FUNCNUM_MSK	(MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
-
-#define GT_CFGADDR_REGNUM_SHF	2
-#define GT_CFGADDR_REGNUM_MSK	(MSK(6) << GT_CFGADDR_REGNUM_SHF)
-
-
-#define GT_SDRAM_BM_ORDER_SHF	2
-#define GT_SDRAM_BM_ORDER_MSK	(MSK(1) << GT_SDRAM_BM_ORDER_SHF)
-#define GT_SDRAM_BM_ORDER_BIT	GT_SDRAM_BM_ORDER_MSK
-#define GT_SDRAM_BM_ORDER_SUB	1
-#define GT_SDRAM_BM_ORDER_LIN	0
-
-#define GT_SDRAM_BM_RSVD_ALL1	0xFFB
-
-
-#define GT_SDRAM_ADDRDECODE_ADDR_SHF	0
-#define GT_SDRAM_ADDRDECODE_ADDR_MSK	(MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
-#define GT_SDRAM_ADDRDECODE_ADDR_0	0
-#define GT_SDRAM_ADDRDECODE_ADDR_1	1
-#define GT_SDRAM_ADDRDECODE_ADDR_2	2
-#define GT_SDRAM_ADDRDECODE_ADDR_3	3
-#define GT_SDRAM_ADDRDECODE_ADDR_4	4
-#define GT_SDRAM_ADDRDECODE_ADDR_5	5
-#define GT_SDRAM_ADDRDECODE_ADDR_6	6
-#define GT_SDRAM_ADDRDECODE_ADDR_7	7
-
-
-#define GT_SDRAM_B0_CASLAT_SHF		0
-#define GT_SDRAM_B0_CASLAT_MSK		(MSK(2) << GT_SDRAM_B0__SHF)
-#define GT_SDRAM_B0_CASLAT_2		1
-#define GT_SDRAM_B0_CASLAT_3		2
-
-#define GT_SDRAM_B0_FTDIS_SHF		2
-#define GT_SDRAM_B0_FTDIS_MSK		(MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
-#define GT_SDRAM_B0_FTDIS_BIT		GT_SDRAM_B0_FTDIS_MSK
-
-#define GT_SDRAM_B0_SRASPRCHG_SHF	3
-#define GT_SDRAM_B0_SRASPRCHG_MSK	(MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
-#define GT_SDRAM_B0_SRASPRCHG_BIT	GT_SDRAM_B0_SRASPRCHG_MSK
-#define GT_SDRAM_B0_SRASPRCHG_2		0
-#define GT_SDRAM_B0_SRASPRCHG_3		1
-
-#define GT_SDRAM_B0_B0COMPAB_SHF	4
-#define GT_SDRAM_B0_B0COMPAB_MSK	(MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
-#define GT_SDRAM_B0_B0COMPAB_BIT	GT_SDRAM_B0_B0COMPAB_MSK
-
-#define GT_SDRAM_B0_64BITINT_SHF	5
-#define GT_SDRAM_B0_64BITINT_MSK	(MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
-#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
-#define GT_SDRAM_B0_64BITINT_2		0
-#define GT_SDRAM_B0_64BITINT_4		1
-
-#define GT_SDRAM_B0_BW_SHF		6
-#define GT_SDRAM_B0_BW_MSK		(MSK(1) << GT_SDRAM_B0_BW_SHF)
-#define GT_SDRAM_B0_BW_BIT		GT_SDRAM_B0_BW_MSK
-#define GT_SDRAM_B0_BW_32		0
-#define GT_SDRAM_B0_BW_64		1
-
-#define GT_SDRAM_B0_BLODD_SHF		7
-#define GT_SDRAM_B0_BLODD_MSK		(MSK(1) << GT_SDRAM_B0_BLODD_SHF)
-#define GT_SDRAM_B0_BLODD_BIT		GT_SDRAM_B0_BLODD_MSK
-
-#define GT_SDRAM_B0_PAR_SHF		8
-#define GT_SDRAM_B0_PAR_MSK		(MSK(1) << GT_SDRAM_B0_PAR_SHF)
-#define GT_SDRAM_B0_PAR_BIT		GT_SDRAM_B0_PAR_MSK
-
-#define GT_SDRAM_B0_BYPASS_SHF		9
-#define GT_SDRAM_B0_BYPASS_MSK		(MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
-#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
-
-#define GT_SDRAM_B0_SRAS2SCAS_SHF	10
-#define GT_SDRAM_B0_SRAS2SCAS_MSK	(MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
-#define GT_SDRAM_B0_SRAS2SCAS_BIT	GT_SDRAM_B0_SRAS2SCAS_MSK
-#define GT_SDRAM_B0_SRAS2SCAS_2		0
-#define GT_SDRAM_B0_SRAS2SCAS_3		1
-
-#define GT_SDRAM_B0_SIZE_SHF		11
-#define GT_SDRAM_B0_SIZE_MSK		(MSK(1) << GT_SDRAM_B0_SIZE_SHF)
-#define GT_SDRAM_B0_SIZE_BIT		GT_SDRAM_B0_SIZE_MSK
-#define GT_SDRAM_B0_SIZE_16M		0
-#define GT_SDRAM_B0_SIZE_64M		1
-
-#define GT_SDRAM_B0_EXTPAR_SHF		12
-#define GT_SDRAM_B0_EXTPAR_MSK		(MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
-#define GT_SDRAM_B0_EXTPAR_BIT		GT_SDRAM_B0_EXTPAR_MSK
-
-#define GT_SDRAM_B0_BLEN_SHF		13
-#define GT_SDRAM_B0_BLEN_MSK		(MSK(1) << GT_SDRAM_B0_BLEN_SHF)
-#define GT_SDRAM_B0_BLEN_BIT		GT_SDRAM_B0_BLEN_MSK
-#define GT_SDRAM_B0_BLEN_8		0
-#define GT_SDRAM_B0_BLEN_4		1
-
-
-#define GT_SDRAM_CFG_REFINT_SHF		0
-#define GT_SDRAM_CFG_REFINT_MSK		(MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
-
-#define GT_SDRAM_CFG_NINTERLEAVE_SHF	14
-#define GT_SDRAM_CFG_NINTERLEAVE_MSK    (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
-#define GT_SDRAM_CFG_NINTERLEAVE_BIT	GT_SDRAM_CFG_NINTERLEAVE_MSK
-
-#define GT_SDRAM_CFG_RMW_SHF		15
-#define GT_SDRAM_CFG_RMW_MSK		(MSK(1) << GT_SDRAM_CFG_RMW_SHF)
-#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
-
-#define GT_SDRAM_CFG_NONSTAGREF_SHF	16
-#define GT_SDRAM_CFG_NONSTAGREF_MSK	(MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
-#define GT_SDRAM_CFG_NONSTAGREF_BIT	GT_SDRAM_CFG_NONSTAGREF_MSK
-
-#define GT_SDRAM_CFG_DUPCNTL_SHF	19
-#define GT_SDRAM_CFG_DUPCNTL_MSK	(MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
-#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK
-
-#define GT_SDRAM_CFG_DUPBA_SHF		20
-#define GT_SDRAM_CFG_DUPBA_MSK		(MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
-#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
-
-#define GT_SDRAM_CFG_DUPEOT0_SHF	21
-#define GT_SDRAM_CFG_DUPEOT0_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
-#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
-
-#define GT_SDRAM_CFG_DUPEOT1_SHF	22
-#define GT_SDRAM_CFG_DUPEOT1_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
-#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
-
-#define GT_SDRAM_OPMODE_OP_SHF		0
-#define GT_SDRAM_OPMODE_OP_MSK		(MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
-#define GT_SDRAM_OPMODE_OP_NORMAL	0
-#define GT_SDRAM_OPMODE_OP_NOP		1
-#define GT_SDRAM_OPMODE_OP_PRCHG	2
-#define GT_SDRAM_OPMODE_OP_MODE		3
-#define GT_SDRAM_OPMODE_OP_CBR		4
-
-
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT	GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
-
-#define GT_PCI0_BARE_SWSCS32DIS_SHF	1
-#define GT_PCI0_BARE_SWSCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
-#define GT_PCI0_BARE_SWSCS32DIS_BIT	GT_PCI0_BARE_SWSCS32DIS_MSK
-	
-#define GT_PCI0_BARE_SWSCS10DIS_SHF	2
-#define GT_PCI0_BARE_SWSCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
-#define GT_PCI0_BARE_SWSCS10DIS_BIT	GT_PCI0_BARE_SWSCS10DIS_MSK
-
-#define GT_PCI0_BARE_INTIODIS_SHF	3
-#define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
-#define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK
-
-#define GT_PCI0_BARE_INTMEMDIS_SHF	4
-#define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
-#define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK
-
-#define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
-#define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
-#define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK
-
-#define GT_PCI0_BARE_CS20DIS_SHF	6
-#define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
-#define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK
-
-#define GT_PCI0_BARE_SCS32DIS_SHF	7
-#define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
-#define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK
-
-#define GT_PCI0_BARE_SCS10DIS_SHF	8
-#define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
-#define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK
-
-
-#define GT_INTRCAUSE_MASABORT0_SHF	18
-#define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
-#define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK
-
-#define GT_INTRCAUSE_TARABORT0_SHF	19
-#define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
-#define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK
-
-
-#define GT_PCI0_CFGADDR_REGNUM_SHF	2
-#define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
-#define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
-#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
-#define GT_PCI0_CFGADDR_DEVNUM_SHF	11
-#define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
-#define GT_PCI0_CFGADDR_BUSNUM_SHF	16
-#define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
-#define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
-#define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
-#define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
-
-
-/************************************************************************
- *  Misc
- ************************************************************************/
-
-#define GT_DEF_BASE		0x14000000
-#define GT_DEF_PCI0_MEM0_BASE	0x12000000
-#define GT_MAX_BANKSIZE		(256 * 1024 * 1024)   /* Max 256MB bank */
-#define GT_LATTIM_MIN    	6		      /* Minimum lat	*/
-
-#endif /* #ifndef GT64120_H */
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h
index 5d7fb0ef2..b5b61c1ca 100644
--- a/include/asm-mips/mips-boards/prom.h
+++ b/include/asm-mips/mips-boards/prom.h
@@ -28,7 +28,7 @@
 
 extern char *prom_getcmdline(void);
 extern char *prom_getenv(char *name);
-extern void setup_prom_printf(void);
+extern void setup_prom_printf(int tty_no);
 extern void prom_printf(char *fmt, ...);
 extern void prom_init_cmdline(void);
 extern void prom_meminit(void);
diff --git a/include/asm-mips/mips-boards/saa9730_uart.h b/include/asm-mips/mips-boards/saa9730_uart.h
new file mode 100644
index 000000000..c913143d5
--- /dev/null
+++ b/include/asm-mips/mips-boards/saa9730_uart.h
@@ -0,0 +1,69 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Register definitions for the UART part of the Philips SAA9730 chip.
+ *
+ */
+
+#ifndef SAA9730_UART_H
+#define SAA9730_UART_H
+
+/* The SAA9730 UART register map, as seen via the PCI bus */
+
+#define SAA9730_UART_REGS_ADDR	0x21800
+
+struct uart_saa9730_regmap {
+	volatile unsigned char Thr_Rbr;
+	volatile unsigned char Ier;
+	volatile unsigned char Iir_Fcr;
+	volatile unsigned char Lcr;
+	volatile unsigned char Mcr;
+	volatile unsigned char Lsr;
+	volatile unsigned char Msr;
+	volatile unsigned char Scr;
+	volatile unsigned char BaudDivLsb;
+	volatile unsigned char BaudDivMsb;
+	volatile unsigned char Junk0;
+	volatile unsigned char Junk1;
+	volatile unsigned int Config;		/* 0x2180c */
+	volatile unsigned int TxStart;		/* 0x21810 */
+	volatile unsigned int TxLength;		/* 0x21814 */
+	volatile unsigned int TxCounter;	/* 0x21818 */
+	volatile unsigned int RxStart;		/* 0x2181c */
+	volatile unsigned int RxLength;		/* 0x21820 */
+	volatile unsigned int RxCounter;	/* 0x21824 */
+};
+typedef volatile struct uart_saa9730_regmap t_uart_saa9730_regmap;
+
+/*
+ * Only a subset of the UART control bits are defined here,
+ * enough to make the serial debug port work.
+ */
+
+#define SAA9730_LCR_DATA8	0x03
+
+#define SAA9730_MCR_DTR		0x01
+#define SAA9730_MCR_RTS		0x02
+
+#define SAA9730_LSR_DR		0x01
+#define SAA9730_LSR_THRE	0x20
+
+#endif /* !(SAA9730_UART_H) */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index cbedf0ae5..9d3f591f6 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -203,7 +203,7 @@
 	"move\t%0,$1\n\t"                                       \
 	".set\tat\n\t"                                          \
 	".set\treorder"                                         \
-:"=r" (__res));                                         \
+	:"=r" (__res));                                         \
         __res;})
 #endif
 
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 0d810b826..78f6a63e9 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -202,6 +202,16 @@ extern inline void pci_dma_sync_sg(struct pci_dev *hwdev,
 #endif
 }
 
+/* Return whether the given PCI device DMA address mask can
+ * be supported properly.  For example, if your device can
+ * only drive the low 24-bits during PCI bus mastering, then
+ * you would pass 0x00ffffff as the mask to this function.
+ */
+extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+{
+	return 1;
+}
+
 /*
  * These macros should be used after a pci_map_sg call has been done
  * to get bus addresses of each of the SG entries and their lengths.
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index d039f59cd..c4ca95b4e 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -75,6 +75,16 @@
 #define JAZZ_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_MIPS_ATLAS
+#include <asm/mips-boards/atlas.h>
+#include <asm/mips-boards/atlasint.h>
+#define ATLAS_SERIAL_PORT_DEFNS			\
+	/* UART CLK   PORT IRQ     FLAGS        */			\
+	{ 0, ATLAS_BASE_BAUD, ATLAS_UART_REGS_BASE, ATLASINT_UART, STD_COM_FLAGS },     /* ttyS0 */
+#else
+#define ATLAS_SERIAL_PORT_DEFNS
+#endif
+
 /*
  * Both Galileo boards have the same UART mappings.
  */
@@ -92,8 +102,7 @@
 #define EV96100_SERIAL_PORT_DEFNS
 #endif
 
-
-#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORTS
+#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
 #define STD_SERIAL_PORT_DEFNS			\
 	/* UART CLK   PORT IRQ     FLAGS        */			\
 	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
@@ -195,6 +204,7 @@
 #endif
 
 #define SERIAL_PORT_DFNS		\
+	ATLAS_SERIAL_PORT_DEFNS		\
 	EV96100_SERIAL_PORT_DEFNS	\
 	JAZZ_SERIAL_PORT_DEFNS		\
 	STD_SERIAL_PORT_DEFNS		\