diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-07-03 21:46:06 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-07-03 21:46:06 +0000 |
| commit | 3e414096429d55fbc8116171bba3487647bbe638 (patch) | |
| tree | 2b5fcfd9d16fa3a32c829fc2076f6e3785b43374 /arch/i386 | |
| parent | 20b23bfcf36fcb2d16d8b844501072541970637c (diff) | |
Merge with Linux 2.4.0-test3-pre2.
Diffstat (limited to 'arch/i386')
| -rw-r--r-- | arch/i386/kernel/apic.c | 4 | ||||
| -rw-r--r-- | arch/i386/kernel/pci-irq.c | 2 | ||||
| -rw-r--r-- | arch/i386/kernel/setup.c | 5 |
3 files changed, 9 insertions, 2 deletions
diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c index 6a1a8aa40..100a5ba5a 100644 --- a/arch/i386/kernel/apic.c +++ b/arch/i386/kernel/apic.c @@ -597,7 +597,9 @@ static inline void handle_smp_time (int user, int cpu) } kstat.cpu_system += system; kstat.per_cpu_system[cpu] += system; - + } else if (local_bh_count(cpu) || local_irq_count(cpu) > 1) { + kstat.cpu_system += system; + kstat.per_cpu_system[cpu] += system; } irq_exit(cpu, 0); } diff --git a/arch/i386/kernel/pci-irq.c b/arch/i386/kernel/pci-irq.c index 933d6c3c9..b98bf4748 100644 --- a/arch/i386/kernel/pci-irq.c +++ b/arch/i386/kernel/pci-irq.c @@ -464,7 +464,7 @@ void __init pcibios_fixup_irqs(void) } } -void __init pcibios_penalize_isa_irq(int irq) +void pcibios_penalize_isa_irq(int irq) { /* * If any ISAPnP device reports an IRQ in its list of possible diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c index e0425f411..771caa7e7 100644 --- a/arch/i386/kernel/setup.c +++ b/arch/i386/kernel/setup.c @@ -43,6 +43,11 @@ * Pentium III FXSR, SSE support * General FPU state handling cleanups * Gareth Hughes <gareth@valinux.com>, May 2000 + * + * Added proper Cascades CPU and L2 cache detection for Cascades + * and 8-way type cache happy bunch from Intel:^) + * Dragan Stancevic <visitor@valinux.com>, May 2000 + * */ /* |