diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2001-06-05 23:24:07 +0000 |
commit | 1385617929e09545f9858785ea3dc1068fedfde1 (patch) | |
tree | 728aa64786357d033a263299df97c98b28f31f0c /arch/mips/gt64120/momenco_ocelot/ocelot_pld.h | |
parent | e4598d1f9097360d265a55f468db81d751e29a1d (diff) |
Support 512mb RAM configuration for Momenco Ocelot. Patch from
David Woodhouse (dwmw2@infradead.org).
Diffstat (limited to 'arch/mips/gt64120/momenco_ocelot/ocelot_pld.h')
-rw-r--r-- | arch/mips/gt64120/momenco_ocelot/ocelot_pld.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h new file mode 100644 index 000000000..e840ed42f --- /dev/null +++ b/arch/mips/gt64120/momenco_ocelot/ocelot_pld.h @@ -0,0 +1,34 @@ +/* + * $Id$ + * + * Ocelot Board Register Definitions + * + * (C) 2001 Red Hat, Inc. + * + * GPL'd + * + */ + +#ifndef __MOMENCO_OCELOT_PLD_H__ +#define __MOMENCO_OCELOT_PLD_H__ + +#define OCELOT_CS0_ADDR (0xe0020000) + +#define OCELOT_REG_BOARDREV (0) +#define OCELOT_REG_PLD1_ID (1) +#define OCELOT_REG_PLD2_ID (2) +#define OCELOT_REG_RESET_STATUS (3) +#define OCELOT_REG_BOARD_STATUS (4) +#define OCELOT_REG_CPCI_ID (5) +#define OCELOT_REG_I2C_CTRL (8) +#define OCELOT_REG_EEPROM_MODE (9) +#define OCELOT_REG_INTMASK (10) +#define OCELOT_REG_INTSTATUS (11) +#define OCELOT_REG_INTSET (12) +#define OCELOT_REG_INTCLR (13) + +#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) +#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) + + +#endif /* __MOMENCO_OCELOT_PLD_H__ */ |