diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1997-12-01 17:57:09 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 1997-12-01 17:57:09 +0000 |
| commit | a62a0f262e0179df8c632f529c95abf54ef78332 (patch) | |
| tree | 80e6a7a7d407d08e218332bb3fcccdaf9f28fcc1 /arch/mips/kernel/r2300_fpu.S | |
| parent | fd095d09f2d475dc2e8599b1b8bae1cd65e91685 (diff) | |
Part #2 merging back my changes ...
Diffstat (limited to 'arch/mips/kernel/r2300_fpu.S')
| -rw-r--r-- | arch/mips/kernel/r2300_fpu.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S index fc4e04617..6c699c74d 100644 --- a/arch/mips/kernel/r2300_fpu.S +++ b/arch/mips/kernel/r2300_fpu.S @@ -10,7 +10,7 @@ * Multi-arch abstraction and asm macros for easier reading: * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * - * $Id: r2300_fpu.S,v 1.2 1997/06/25 14:44:51 ralf Exp $ + * $Id: r2300_fpu.S,v 1.3 1997/12/01 16:54:20 ralf Exp $ */ #include <asm/asm.h> #include <asm/fpregdef.h> @@ -30,7 +30,7 @@ nop cfc1 t0,fcr31 - /* Store the 16 odd double precision registers */ + /* Store the 32 single precision registers */ swc1 $f0,(SC_FPREGS+0)(a0) swc1 $f1,(SC_FPREGS+8)(a0) swc1 $f2,(SC_FPREGS+16)(a0) @@ -76,7 +76,8 @@ .set macro END(r2300_save_fp_context) -/* Restore fpu state: +/* + * Restore fpu state: * - fp gp registers * - cp1 status/control register * @@ -91,7 +92,6 @@ bgez t0,1f nop - bgez t0,1f lw t0,SC_FPC_CSR(a0) /* Restore the 16 odd double precision registers only * when enabled in the cp0 status register. |