diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-12-13 19:43:03 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-12-13 19:43:03 +0000 |
| commit | 8ecd5b87ddd65325753a989b80a64c60294adbab (patch) | |
| tree | 0c0d0030d4b7e4468e507cdbce8121c3bdc28cfd /arch/mips/kernel/traps.c | |
| parent | ce0560ca5cf571fea993f6ea6f4ea19699824b92 (diff) | |
First batch of PMC Ocelot CP7000 patches.
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 27451eb37..1b1038c19 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -694,14 +694,15 @@ static inline void setup_dedicated_int(void) */ static inline void parity_protection_init(void) { - switch(mips_cpu.cputype) - { + switch(mips_cpu.cputype) { case CPU_5KC: - /* Set the PE bit (bit 31) in the CP0_ECC register. */ - printk("Enable the cache parity protection for MIPS 5KC CPUs.\n"); - write_32bit_cp0_register(CP0_ECC, read_32bit_cp0_register(CP0_ECC) - | 0x80000000); - break; + /* Set the PE bit (bit 31) in the CP0_ECC register. */ + printk(KERN_INFO "Enable the cache parity protection for " + "MIPS 5KC CPUs.\n"); + write_32bit_cp0_register(CP0_ECC, + read_32bit_cp0_register(CP0_ECC) + | 0x80000000); + break; default: } } @@ -815,8 +816,8 @@ void __init trap_init(void) /* * Handling the following exceptions depends mostly of the cpu type */ - if((mips_cpu.options & MIPS_CPU_4KEX) - && (mips_cpu.options & MIPS_CPU_4KTLB)) { + if ((mips_cpu.options & MIPS_CPU_4KEX) + && (mips_cpu.options & MIPS_CPU_4KTLB)) { if(mips_cpu.cputype == CPU_NEVADA) { memcpy((void *)KSEG0, &except_vec0_nevada, 0x80); } else if (mips_cpu.cputype == CPU_R4600) @@ -861,7 +862,6 @@ void __init trap_init(void) case CPU_R6000A: save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; -#if 0 /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and @@ -870,9 +870,8 @@ void __init trap_init(void) * current list of targets for Linux/MIPS. * (Duh, crap, there is someone with a tripple R6k machine) */ - (void)set_except_vector(14, handle_mc); - (void)set_except_vector(15, handle_ndc); -#endif + //set_except_vector(14, handle_mc); + //set_except_vector(15, handle_ndc); case CPU_R2000: case CPU_R3000: case CPU_R3000A: |