diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-24 03:10:57 +0000 |
| commit | 93f107ba6cceee2c35d207349976936da48393bc (patch) | |
| tree | c33ea3d9e7e92245d6593b694cb514c8db5ff05d /arch/mips/kernel/traps.c | |
| parent | f79c44e04169d10b07b53d4a524c8c41ea5504d5 (diff) | |
Add code to support the SB1 core, including mmu routines, processor
detection. This also tweaks cpu_probe() to use bits 15:8 of PRId as
a company ID, as per the mips32/mips64 specs, and use bits 7:0 as the
processor ID within the company. Patch from Justin with mods and some
additional bits by me.
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 363dfd778..e2c3663cb 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -791,7 +791,7 @@ void __init trap_init(void) memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80); memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); - + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200); /* * Setup default vectors */ @@ -885,10 +885,21 @@ void __init trap_init(void) */ panic("CPU too expensive - making holiday in the ANDES!"); break; + case CPU_SB1: + /* XXX - This should be folded in to the "cleaner" handling, above */ + memcpy((void *)KSEG0, &except_vec0_r4000, 0x80); + memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80); + save_fp_context = _save_fp_context; + restore_fp_context = _restore_fp_context; + /* Enable timer interrupt and scd mapped interrupt in status register */ + clear_cp0_status(0xf000); + set_cp0_status(0xc00); + break; case CPU_R6000: case CPU_R6000A: save_fp_context = _save_fp_context; restore_fp_context = _restore_fp_context; + /* * The R6000 is the only R-series CPU that features a machine * check exception (similar to the R4000 cache error) and |