diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-05-04 19:51:18 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-05-04 19:51:18 +0000 |
| commit | af142756744156e7ffd1e7ac64efb8a895096aec (patch) | |
| tree | d817f283313243ad7574c1933573466cfb5c9956 /arch/mips/kernel | |
| parent | a9a931336a3c21c6a0e830c25c1372280e80cc6b (diff) | |
Alchemy support. Done by Pete and further hacked up a bit by me ...
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/proc.c | 7 | ||||
| -rw-r--r-- | arch/mips/kernel/setup.c | 29 |
2 files changed, 35 insertions, 1 deletions
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 2a066ccaa..773d72c0d 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -44,12 +44,17 @@ int get_cpuinfo(char *buffer) const char *mach_momenco_names[] = GROUP_MOMENCO_NAMES; const char *mach_ite_names[] = GROUP_ITE_NAMES; const char *mach_philips_names[] = GROUP_PHILIPS_NAMES; + const char *mach_globespan_names[] = GROUP_GLOBESPAN_NAMES; + const char *mach_sibyte_names[] = GROUP_SIBYTE_NAMES; + const char *mach_toshiba_names[] = GROUP_TOSHIBA_NAMES; + const char *mach_alchemy_names[] = GROUP_ALCHEMY_NAMES; const char **mach_group_to_name[] = { mach_unknown_names, mach_jazz_names, mach_dec_names, mach_arc_names, mach_sni_rm_names, mach_acn_names, mach_sgi_names, mach_cobalt_names, mach_nec_ddb_names, mach_baget_names, mach_cosine_names, mach_galileo_names, mach_momenco_names, - mach_ite_names, mach_philips_names}; + mach_ite_names, mach_philips_names, mach_globespan_names, + mach_sibyte_names, mach_toshiba_names, mach_alchemy_names}; unsigned int version = read_32bit_cp0_register(CP0_PRID); int len; diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 587adaadd..82d44e33e 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -341,6 +341,30 @@ static inline void cpu_probe(void) } break; #endif + case PRID_COMP_ALCHEMY: + switch (mips_cpu.processor_id & 0xff00) { +#ifdef CONFIG_CPU_MIPS32 + case PRID_IMP_AU1000: + mips_cpu.cputype = CPU_AU1000; + mips_cpu.isa_level = MIPS_CPU_ISA_M32; + mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_WATCH; + config1 = read_mips32_cp0_config1(); + if (config1 & (1 << 3)) + mips_cpu.options |= MIPS_CPU_WATCH; + if (config1 & (1 << 2)) + mips_cpu.options |= MIPS_CPU_MIPS16; + if (config1 & 1) + mips_cpu.options |= MIPS_CPU_FPU; + mips_cpu.scache.flags = MIPS_CACHE_NOT_PRESENT; + break; +#endif + default: + mips_cpu.cputype = CPU_UNKNOWN; + break; + } + break; case PRID_COMP_SIBYTE: switch (mips_cpu.processor_id & 0xff00) { case PRID_IMP_SB1: @@ -596,6 +620,11 @@ void __init setup_arch(char **cmdline_p) nino_setup(); break; #endif +#ifdef CONFIG_MIPS_PB1000 + case MACH_GROUP_ALCHEMY: + au1000_setup(); + break; +#endif default: panic("Unsupported architecture"); } |