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authorRalf Baechle <ralf@linux-mips.org>2000-01-17 23:32:45 +0000
committerRalf Baechle <ralf@linux-mips.org>2000-01-17 23:32:45 +0000
commitbb382d1cd598a97151a0edf5ac26e36afb0a64ce (patch)
treefd9f0ca1b31e5af2faa0d7165e6fd0fbb5524ebf /arch/mips64/sgi-ip27/ip27-irq-glue.S
parentaf38bda129551834653720f277a920d7d284bd3d (diff)
- IOC3 driver now will panic when encountering a RX/TX PCI DMA error.
- IOC3 driver does no longer use GFP_DMA which given the _very_ small number of available GFP_DMA pages might have deadlocked the system. - First cut of Origin support. Last minute change: Do no longer use ARC memory / MD hub memory configuration information but klconfig.h stuff. Simpler, faster, shorter. - Zillions of MIPS64 fixes.
Diffstat (limited to 'arch/mips64/sgi-ip27/ip27-irq-glue.S')
-rw-r--r--arch/mips64/sgi-ip27/ip27-irq-glue.S65
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/mips64/sgi-ip27/ip27-irq-glue.S b/arch/mips64/sgi-ip27/ip27-irq-glue.S
new file mode 100644
index 000000000..40517c2d4
--- /dev/null
+++ b/arch/mips64/sgi-ip27/ip27-irq-glue.S
@@ -0,0 +1,65 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+ .text
+ .set noat
+ .align 5
+NESTED(ip27_irq, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+
+ /* IP27 may signal interrupt which we're not interested in.
+ Mask them out. */
+ mfc0 s0, CP0_CAUSE
+ mfc0 t0, CP0_STATUS
+ and s0, t0
+
+ /* First check for RT interrupt. */
+ andi a0, s0, CAUSEF_IP4
+ beqz a0, 1f
+
+ /* Ok, a timer interrupt. */
+ move a0, sp
+ jal rt_timer_interrupt
+
+ j ret_from_irq
+
+1: andi a0, s0, (CAUSEF_IP2 | CAUSEF_IP3)
+ beqz a0, 1f
+
+ /* ... a device interrupt ... */
+ move a0, sp
+ jal ip27_do_irq
+
+ j ret_from_irq
+
+1:
+#if 1
+ mfc0 a1, CP0_STATUS
+ srl a1, a1, 8
+ andi a1, 0xff
+
+ mfc0 a2, CP0_CAUSE
+ srl a2, a2, 8
+ andi a2, 0xff
+
+ move a3, s0
+ PRINT("Spurious interrupt, c0_status = %02x, c0_cause = %02x, pending %02x.\n")
+ ld a1, PT_EPC(sp)
+0: b 0b
+#endif
+
+ j ret_from_irq
+ END(ip27_irq)