diff options
| author | Harald Koerfgen <hkoerfg@web.de> | 2000-08-03 09:37:26 +0000 |
|---|---|---|
| committer | Harald Koerfgen <hkoerfg@web.de> | 2000-08-03 09:37:26 +0000 |
| commit | 268f75a8e5c22c58a216746be2d11958d2ad2146 (patch) | |
| tree | 72248313a1646f7ffced01446df2a3309eaeb5a6 /arch/mips | |
| parent | f7bbf9552e93a3fa9e5aa7c5cfed458b77b37695 (diff) | |
r3k_flush_cache_sigtramp() still assumed 8 byte cachelines
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/mm/r2300.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/mips/mm/r2300.c b/arch/mips/mm/r2300.c index 5482cc339..fa1cc970a 100644 --- a/arch/mips/mm/r2300.c +++ b/arch/mips/mm/r2300.c @@ -20,13 +20,6 @@ #include <asm/io.h> #include <asm/wbflush.h> -/* - * According to the paper written by D. Miller about Linux cache & TLB - * flush implementation, DMA/Driver coherence should be done at the - * driver layer. Thus, normally, we don't need flush dcache for R3000. - * Define this if driver does not handle cache consistency during DMA ops. - */ - /* Primary cache parameters. */ static int icache_size, dcache_size; /* Size in bytes */ /* the linesizes are usually fixed on R3000s */ @@ -387,16 +380,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr) #ifdef DEBUG_CACHE printk("csigtramp[%08lx]", addr); #endif - /* - * I am assuming an 8 Byte cacheline here. HK - */ - addr &= ~7; save_and_cli(flags); write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC); asm ( "sb\t$0,0x000(%0)\n\t" + "sb\t$0,0x004(%0)\n\t" "sb\t$0,0x008(%0)\n\t" : : "r" (addr) ); |