Introduce __flush_cache_all() which flushes the cache no matter if

this operation is necessary from the mm point of view or not.

8 files changed, 30 insertions, 28 deletions

diff --git a/arch/mips/mm/andes.c b/arch/mips/mm/andes.c
index 1405c4cfd..29a960742 100644
--- a/arch/mips/mm/andes.c
+++ b/arch/mips/mm/andes.c
@@ -173,6 +173,7 @@ void __init ld_mmu_andes(void)
 	_copy_page = andes_copy_page;
 
 	_flush_cache_all = andes_flush_cache_all;
+	___flush_cache_all = andes_flush_cache_all;
 	_flush_cache_mm = andes_flush_cache_mm;
 	_flush_cache_range = andes_flush_cache_range;
 	_flush_cache_page = andes_flush_cache_page;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index cf0775cce..4cd36e9e4 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -111,8 +111,9 @@ pte_t *get_pte_slow(pmd_t *pmd, unsigned long offset)
 
 asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
 {
-	/* XXX Just get it working for now... */
-	flush_cache_all();
+	/* This should flush more selectivly ...  */
+	__flush_cache_all();
+
 	return 0;
 }
 
diff --git a/arch/mips/mm/loadmmu.c b/arch/mips/mm/loadmmu.c
index 26b287f4c..b77ef4079 100644
--- a/arch/mips/mm/loadmmu.c
+++ b/arch/mips/mm/loadmmu.c
@@ -23,6 +23,7 @@ void (*_copy_page)(void * to, void * from);
 
 /* Cache operations. */
 void (*_flush_cache_all)(void);
+void (*___flush_cache_all)(void);
 void (*_flush_cache_mm)(struct mm_struct *mm);
 void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
 			  unsigned long end);
diff --git a/arch/mips/mm/mips32.c b/arch/mips/mm/mips32.c
index 6f44efea9..32f7e132b 100644
--- a/arch/mips/mm/mips32.c
+++ b/arch/mips/mm/mips32.c
@@ -979,6 +979,7 @@ static void __init setup_noscache_funcs(void)
 static void __init setup_scache_funcs(void)
 {
         _flush_cache_all = mips32_flush_cache_all_sc;
+        ___flush_cache_all = mips32_flush_cache_all_sc;
 	_flush_cache_mm = mips32_flush_cache_mm_sc;
 	_flush_cache_range = mips32_flush_cache_range_sc;
 	_flush_cache_page = mips32_flush_cache_page_sc;
@@ -1062,7 +1063,7 @@ void __init ld_mmu_mips32(void)
 	_flush_cache_sigtramp = mips32_flush_cache_sigtramp;
 	_flush_icache_range = mips32_flush_icache_range;	/* Ouch */
 
-	flush_cache_all();
+	__flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);
 
 	/*
diff --git a/arch/mips/mm/r2300.c b/arch/mips/mm/r2300.c
index 3ced671ff..465b75175 100644
--- a/arch/mips/mm/r2300.c
+++ b/arch/mips/mm/r2300.c
@@ -660,6 +660,7 @@ void __init ld_mmu_r2300(void)
 	probe_dcache();
 
 	_flush_cache_all = r3k_flush_cache_all;
+	___flush_cache_all = r3k_flush_cache_all;
 	_flush_cache_mm = r3k_flush_cache_mm;
 	_flush_cache_range = r3k_flush_cache_range;
 	_flush_cache_page = r3k_flush_cache_page;
diff --git a/arch/mips/mm/r4xx0.c b/arch/mips/mm/r4xx0.c
index 64b21bb27..f4c05d8a3 100644
--- a/arch/mips/mm/r4xx0.c
+++ b/arch/mips/mm/r4xx0.c
@@ -1961,24 +1961,18 @@ r4k_flush_icache_range(unsigned long start, unsigned long end)
 	flush_cache_all();
 }
 
+/*
+ * Ok, this seriously sucks.  We use them to flush a user page but don't
+ * know the virtual address, so we have to blast away the whole icache
+ * which is significantly more expensive than the real thing.
+ */
 static void
-r4k_flush_icache_page_i16(struct vm_area_struct *vma, struct page *page)
-{
-	if (!(vma->vm_flags & VM_EXEC))
-		return;
-
-	blast_icache16_page((unsigned long)page_address(page));
-}
-
-static void
-r4k_flush_icache_page_i32(struct vm_area_struct *vma, struct page *page)
+r4k_flush_icache_page_p(struct vm_area_struct *vma, struct page *page)
 {
-	int address;
 	if (!(vma->vm_flags & VM_EXEC))
 		return;
 
-	address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1));
-	blast_icache32_page_indexed(address);
+	flush_cache_all();
 }
 
 /*
@@ -2563,13 +2557,9 @@ static void __init setup_noscache_funcs(void)
 		_flush_cache_page = r4k_flush_cache_page_d32i32;
 		break;
 	}
+	___flush_cache_all = _flush_cache_all;
 
-	switch(ic_lsize) {
-	case 16:
-		_flush_icache_page = r4k_flush_icache_page_i16;
-	case 32:
-		_flush_icache_page = r4k_flush_icache_page_i32;
-	}
+	_flush_icache_page = r4k_flush_icache_page_p;
 
 	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc;
 	_dma_cache_wback = r4k_dma_cache_wback;
@@ -2652,6 +2642,7 @@ static void __init setup_scache_funcs(void)
 		_copy_page = r4k_copy_page_s128;
 		break;
 	}
+	___flush_cache_all = _flush_cache_all;
 	_flush_icache_page = r4k_flush_icache_page_s;
 	_dma_cache_wback_inv = r4k_dma_cache_wback_inv_sc;
 	_dma_cache_wback = r4k_dma_cache_wback;
@@ -2707,7 +2698,7 @@ void __init ld_mmu_r4xx0(void)
 		_flush_cache_sigtramp = r4600v20k_flush_cache_sigtramp;
 	}
 
-	flush_cache_all();
+	__flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);
 
 	/*
diff --git a/arch/mips/mm/r5432.c b/arch/mips/mm/r5432.c
index 0229d0a44..80fa8deef 100644
--- a/arch/mips/mm/r5432.c
+++ b/arch/mips/mm/r5432.c
@@ -459,17 +459,21 @@ static void r5432_flush_page_to_ram_d32(struct page *page)
 static void 
 r5432_flush_icache_range(unsigned long start, unsigned long end)
 {
-	flush_cache_all();
+	r5432_flush_cache_all_d32i32();
 }
 
+/*
+ * Ok, this seriously sucks.  We use them to flush a user page but don't
+ * know the virtual address, so we have to blast away the whole icache
+ * which is significantly more expensive than the real thing.
+ */
 static void
 r5432_flush_icache_page_i32(struct vm_area_struct *vma, struct page *page)
 {
 	if (!(vma->vm_flags & VM_EXEC))
 		return;
 
-	address = KSEG0 + (address & PAGE_MASK & (dcache_size - 1));
-	blast_icache32_page_indexed(address);
+	r5432_flush_cache_all_d32i32();
 }
 
 /*
@@ -835,8 +839,9 @@ void __init ld_mmu_r5432(void)
 
 	_clear_page = r5432_clear_page_d32;
 	_copy_page = r5432_copy_page_d32;
-	_flush_page_to_ram = r5432_flush_page_to_ram_d32;
 	_flush_cache_all = r5432_flush_cache_all_d32i32;
+	___flush_cache_all = r5432_flush_cache_all_d32i32;
+	_flush_page_to_ram = r5432_flush_page_to_ram_d32;
 	_flush_cache_mm = r5432_flush_cache_mm_d32i32;
 	_flush_cache_range = r5432_flush_cache_range_d32i32;
 	_flush_cache_page = r5432_flush_cache_page_d32i32;
@@ -848,7 +853,7 @@ void __init ld_mmu_r5432(void)
 	_flush_cache_sigtramp = r5432_flush_cache_sigtramp;
 	_flush_icache_range = r5432_flush_icache_range;	/* Ouch */
 
-	flush_cache_all();
+	__flush_cache_all();
 	write_32bit_cp0_register(CP0_WIRED, 0);
 
 	/*
diff --git a/arch/mips/mm/rm7k.c b/arch/mips/mm/rm7k.c
index c7a80ff54..4258465c5 100644
--- a/arch/mips/mm/rm7k.c
+++ b/arch/mips/mm/rm7k.c
@@ -547,6 +547,7 @@ void __init ld_mmu_rm7k(void)
 	_copy_page = rm7k_copy_page;
 
 	_flush_cache_all = rm7k_flush_cache_all_d32i32;
+	___flush_cache_all = rm7k_flush_cache_all_d32i32;
 	_flush_cache_mm = rm7k_flush_cache_mm_d32i32;
 	_flush_cache_range = rm7k_flush_cache_range_d32i32;
 	_flush_cache_page = rm7k_flush_cache_page_d32i32;