One gt64120.h file is enough.

8 files changed, 265 insertions, 292 deletions

diff --git a/arch/mips/galileo-boards/ev64120/.cvsignore b/arch/mips/galileo-boards/ev64120/.cvsignore
new file mode 100644
index 000000000..857dd22e9
--- /dev/null
+++ b/arch/mips/galileo-boards/ev64120/.cvsignore
@@ -0,0 +1,2 @@
+.depend
+.*.flags
diff --git a/arch/mips/galileo-boards/ev64120/irq-handler.c b/arch/mips/galileo-boards/ev64120/irq-handler.c
index a259ea7cd..795c33754 100644
--- a/arch/mips/galileo-boards/ev64120/irq-handler.c
+++ b/arch/mips/galileo-boards/ev64120/irq-handler.c
@@ -2,7 +2,6 @@
  * Galileo Technology chip interrupt handler
  *
  *  Modified by RidgeRun, Inc.
- *    
  */
 #include <linux/module.h>
 #include <linux/interrupt.h>
@@ -12,55 +11,54 @@
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
 #include <asm/io.h>
-#include <asm/galileo-boards/gt64120.h>
+#include <asm/gt64120.h>
 #include <asm/galileo-boards/ev64120.h>
 #include <asm/galileo-boards/ev64120int.h>
 
 /*
-  These are interrupt handlers for the GT on-chip interrupts.  They
-  all come in to the MIPS on a single interrupt line, and have to
-  be handled and ack'ed differently than other MIPS interrupts.
-*/
+ * These are interrupt handlers for the GT on-chip interrupts.  They all come
+ * in to the MIPS on a single interrupt line, and have to be handled and ack'ed
+ * differently than other MIPS interrupts.
+ */
 
 #if CURRENTLY_UNUSED
 
 struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
 
-/********************************************************************
- *hook_irq_handler
- *
- *Hooks IRQ handler to the system. When the system is interrupted
- *the interrupt service routine is called.
+/*
+ * hook_irq_handler
  *
- *Inputs :
- *int_cause - The interrupt cause number. In EVB64120 two parameters 
- *            are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. 
- *bit_num   - Indicates which bit number in the cause register
- *isr_ptr   - Pointer to the interrupt service routine
+ * Hooks IRQ handler to the system. When the system is interrupted
+ * the interrupt service routine is called.
  *
- *Outputs :
+ * Inputs :
+ * int_cause - The interrupt cause number. In EVB64120 two parameters 
+ *             are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. 
+ * bit_num   - Indicates which bit number in the cause register
+ * isr_ptr   - Pointer to the interrupt service routine
  *
- *********************************************************************/
+ * Outputs :
+ */
 void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr)
 {
 	irq_handlers[int_cause][bit_num].routine = isr_ptr;
 }
 
 
-/********************************************************************
- *enable_galileo_irq
+/*
+ * enable_galileo_irq
  *
- *Enables the IRQ on Galileo Chip
+ * Enables the IRQ on Galileo Chip
  *
- *Inputs :
- *int_cause -  The interrupt cause number. In EVB64120 two parameters 
+ * Inputs :
+ * int_cause -  The interrupt cause number. In EVB64120 two parameters 
  *            are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
- *bit_num   - Indicates which bit number in the cause register
+ * bit_num   - Indicates which bit number in the cause register
  *
- *Outputs :
- *1 if succesful, 0 if failure
- *********************************************************************/
+ * Outputs :
+ * 1 if succesful, 0 if failure
+ */
 int enable_galileo_irq(int int_cause, int bit_num)
 {
 	if (int_cause == INT_CAUSE_MAIN)
@@ -73,19 +71,19 @@ int enable_galileo_irq(int int_cause, int bit_num)
 	return 1;
 }
 
-/********************************************************************
- *disable_galileo_irq
+/*
+ * disable_galileo_irq
  *
- *Disables the IRQ on Galileo Chip
+ * Disables the IRQ on Galileo Chip
  *
- *Inputs :
- *int_cause -  The interrupt cause number. In EVB64120 two parameters 
+ * Inputs :
+ * int_cause -  The interrupt cause number. In EVB64120 two parameters 
  *            are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
- *bit_num   - Indicates which bit number in the cause register
+ * bit_num   - Indicates which bit number in the cause register
  *
- *Outputs :
- *1 if succesful, 0 if failure
- *********************************************************************/
+ * Outputs :
+ * 1 if succesful, 0 if failure
+ */
 int disable_galileo_irq(int int_cause, int bit_num)
 {
 	if (int_cause == INT_CAUSE_MAIN)
@@ -101,17 +99,17 @@ int disable_galileo_irq(int int_cause, int bit_num)
 
 #endif				/*  UNUSED  */
 
-/********************************************************************
- *galileo_irq -
- *	
- *Interrupt handler for interrupts coming from the Galileo chip.
- *It could be timer interrupt, built in ethernet ports etc...
+/*
+ * galileo_irq -
  *
- *Inputs :
+ * Interrupt handler for interrupts coming from the Galileo chip.
+ * It could be timer interrupt, built in ethernet ports etc...
  *
- *Outputs :
+ * Inputs :
  *
- *********************************************************************/
+ * Outputs :
+ *
+ */
 static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs)
 {
 	unsigned int irq_src, int_high_src, irq_src_mask,
@@ -191,20 +189,18 @@ static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs)
 #endif
 }
 
-/********************************************************************
- *galileo_time_init -
+/*
+ * galileo_time_init -
  *
- *Initializes timer using galileo's built in timer.
+ * Initializes timer using galileo's built in timer.
  *
  *
- *Inputs :
- *irq - number of irq to be used by the timer
+ * Inputs :
+ * irq - number of irq to be used by the timer
  *
- *Outpus :
+ * Outpus :
  *
- *********************************************************************/
-
-
+ */
 #ifdef CONFIG_SYSCLK_100
 #define Sys_clock (100 * 1000000)	// 100 MHz
 #endif
@@ -216,10 +212,10 @@ static void galileo_irq(int irq, void *dev_id, struct pt_regs *regs)
 #endif
 
 /*
-  This will ignore the standard MIPS timer interrupt handler
-  that is passed in as *irq (=irq0 in ../kernel/time.c).
-  We will do our own timer interrupt handling.
-*/
+ * This will ignore the standard MIPS timer interrupt handler that is passed
+ * in as *irq (=irq0 in ../kernel/time.c).  We will do our own timer interrupt
+ * handling.
+ */
 void galileo_time_init(struct irqaction *irq)
 {
 	extern irq_desc_t irq_desc[NR_IRQS];
@@ -230,9 +226,10 @@ void galileo_time_init(struct irqaction *irq)
 	/* Load timer value for 100 Hz */
 	GT_WRITE(GT_TC3_OFS, Sys_clock / 100);
 
-	/*  Create the IRQ structure entry for the timer.  Since we're too early
-	   in the boot process to use the "request_irq()" call, we'll hard-code
-	   the values to the correct interrupt line.
+	/*
+	 * Create the IRQ structure entry for the timer.  Since we're too early
+	 * in the boot process to use the "request_irq()" call, we'll hard-code
+	 * the values to the correct interrupt line.
 	 */
 	timer.handler = &galileo_irq;
 	timer.flags = SA_SHIRQ;
@@ -270,5 +267,4 @@ void galileo_irq_init(void)
 		}
 	}
 #endif
-
 }
diff --git a/arch/mips/galileo-boards/ev64120/irq.c b/arch/mips/galileo-boards/ev64120/irq.c
index 16aef239b..44b0bf092 100644
--- a/arch/mips/galileo-boards/ev64120/irq.c
+++ b/arch/mips/galileo-boards/ev64120/irq.c
@@ -240,7 +240,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
 #endif
 
 	cpu = smp_processor_id();
-	irq_enter(cpu);
+	irq_enter(cpu, irq);
 	kstat.irqs[cpu][irq]++;
 
 	if (irq_desc[irq].handler->ack) {
@@ -273,7 +273,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
 	}
 
 	enable_irq(irq);
-	irq_exit(cpu);
+	irq_exit(cpu, irq);
 
 	if (softirq_active(cpu) & softirq_mask(cpu))
 		do_softirq();
diff --git a/arch/mips/galileo-boards/ev64120/pci_bios.c b/arch/mips/galileo-boards/ev64120/pci_bios.c
index 96a85a0e0..01fc2ccbb 100644
--- a/arch/mips/galileo-boards/ev64120/pci_bios.c
+++ b/arch/mips/galileo-boards/ev64120/pci_bios.c
@@ -1,6 +1,4 @@
 /*
- * pci_bios.c
- *
  * BRIEF MODULE DESCRIPTION
  * Galileo Evaluation Boards PCI support.
  *
@@ -33,9 +31,7 @@
  *  You should have received a copy of the  GNU General Public License along
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
  */
-
 #include <linux/config.h>
 #include <linux/types.h>
 #include <linux/pci.h>
@@ -45,7 +41,7 @@
 #include <asm/pci.h>
 #include <asm/io.h>
 #include <asm/galileo-boards/ev64120.h>
-#include <asm/galileo-boards/gt64120.h>
+#include <asm/gt64120.h>
 
 #include <linux/init.h>
 
@@ -62,8 +58,9 @@
 #define SELF 0
 
 /*
-  These functions and structures provide the BIOS scan and mapping of the PCI devices.
-*/
+ * These functions and structures provide the BIOS scan and mapping of the PCI
+ * devices.
+ */
 
 #define MAX_PCI_DEVS 10
 
@@ -80,10 +77,9 @@ static void __init allocate_pci_space(struct pci_device *pci_devices);
 static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus);
 
 /*
-  The functions that actually read and write to the controller.
-
-  Copied from or modified from Galileo Technology code.
-*/
+ * The functions that actually read and write to the controller.
+ * Copied from or modified from Galileo Technology code.
+ */
 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device);
 static void pci0WriteConfigReg(unsigned int offset,
 			       struct pci_dev *device, unsigned int data);
@@ -133,16 +129,14 @@ static int galileo_pcibios_write_config_dword(struct pci_dev *dev,
 static void galileo_pcibios_set_master(struct pci_dev *dev);
 
 /*
-  General-purpose PCI functions.
-*/
-
-/********************************************************************
-* pci0MapIOspace - Maps PCI0 IO space for the master.
-* Inputs: base and length of pci0Io
-*********************************************************************/
+ * General-purpose PCI functions.
+ */
 
-static void pci0MapIOspace(unsigned int pci0IoBase,
-			   unsigned int pci0IoLength)
+/*
+ * pci0MapIOspace - Maps PCI0 IO space for the master.
+ * Inputs: base and length of pci0Io
+ */
+static void pci0MapIOspace(unsigned int pci0IoBase, unsigned int pci0IoLength)
 {
 	unsigned int pci0IoTop =
 	    (unsigned int) (pci0IoBase + pci0IoLength);
@@ -156,10 +150,10 @@ static void pci0MapIOspace(unsigned int pci0IoBase,
 	GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop);
 }
 
-/********************************************************************
-* pci1MapIOspace - Maps PCI1 IO space for the master.
-* Inputs: base and length of pci1Io
-*********************************************************************/
+/*
+ * pci1MapIOspace - Maps PCI1 IO space for the master.
+ * Inputs: base and length of pci1Io
+ */
 
 static void pci1MapIOspace(unsigned int pci1IoBase,
 			   unsigned int pci1IoLength)
@@ -176,10 +170,10 @@ static void pci1MapIOspace(unsigned int pci1IoBase,
 	GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop);
 }
 
-/********************************************************************
-* pci0MapMemory0space - Maps PCI0 memory0 space for the master.
-* Inputs: base and length of pci0Mem0
-*********************************************************************/
+/*
+ * pci0MapMemory0space - Maps PCI0 memory0 space for the master.
+ * Inputs: base and length of pci0Mem0
+ */
 
 static void pci0MapMemory0space(unsigned int pci0Mem0Base,
 				unsigned int pci0Mem0Length)
@@ -195,10 +189,10 @@ static void pci0MapMemory0space(unsigned int pci0Mem0Base,
 	GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top);
 }
 
-/********************************************************************
-* pci1MapMemory0space - Maps PCI1 memory0 space for the master.
-* Inputs: base and length of pci1Mem0
-*********************************************************************/
+/*
+ * pci1MapMemory0space - Maps PCI1 memory0 space for the master.
+ * Inputs: base and length of pci1Mem0
+ */
 
 static void pci1MapMemory0space(unsigned int pci1Mem0Base,
 				unsigned int pci1Mem0Length)
@@ -214,10 +208,10 @@ static void pci1MapMemory0space(unsigned int pci1Mem0Base,
 	GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top);
 }
 
-/********************************************************************
-* pci0MapMemory1space - Maps PCI0 memory1 space for the master.
-* Inputs: base and length of pci0Mem1
-*********************************************************************/
+/*
+ * pci0MapMemory1space - Maps PCI0 memory1 space for the master.
+ * Inputs: base and length of pci0Mem1
+ */
 
 static void pci0MapMemory1space(unsigned int pci0Mem1Base,
 				unsigned int pci0Mem1Length)
@@ -234,10 +228,10 @@ static void pci0MapMemory1space(unsigned int pci0Mem1Base,
 
 }
 
-/********************************************************************
-* pci1MapMemory1space - Maps PCI1 memory1 space for the master.
-* Inputs: base and length of pci1Mem1
-*********************************************************************/
+/*
+ * pci1MapMemory1space - Maps PCI1 memory1 space for the master.
+ * Inputs: base and length of pci1Mem1
+ */
 
 static void pci1MapMemory1space(unsigned int pci1Mem1Base,
 				unsigned int pci1Mem1Length)
@@ -253,11 +247,11 @@ static void pci1MapMemory1space(unsigned int pci1Mem1Base,
 	GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top);
 }
 
-/********************************************************************
-* pci0GetIOspaceBase - Return PCI0 IO Base Address.
-* Inputs: N/A
-* Returns: PCI0 IO Base Address.
-*********************************************************************/
+/*
+ * pci0GetIOspaceBase - Return PCI0 IO Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 IO Base Address.
+ */
 
 static unsigned int pci0GetIOspaceBase(void)
 {
@@ -267,12 +261,11 @@ static unsigned int pci0GetIOspaceBase(void)
 	return base;
 }
 
-/********************************************************************
-* pci0GetIOspaceSize - Return PCI0 IO Bar Size.
-* Inputs: N/A
-* Returns: PCI0 IO Bar Size.
-*********************************************************************/
-
+/*
+ * pci0GetIOspaceSize - Return PCI0 IO Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 IO Bar Size.
+ */
 static unsigned int pci0GetIOspaceSize(void)
 {
 	unsigned int top, base, size;
@@ -285,12 +278,11 @@ static unsigned int pci0GetIOspaceSize(void)
 	return (size + 1);
 }
 
-/********************************************************************
-* pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
-* Inputs: N/A
-* Returns: PCI0 Memory 0 Base Address.
-*********************************************************************/
-
+/*
+ * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 0 Base Address.
+ */
 static unsigned int pci0GetMemory0Base(void)
 {
 	unsigned int base;
@@ -299,12 +291,11 @@ static unsigned int pci0GetMemory0Base(void)
 	return base;
 }
 
-/********************************************************************
-* pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
-* Inputs: N/A
-* Returns: PCI0 Memory 0 Bar Size.
-*********************************************************************/
-
+/*
+ * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 0 Bar Size.
+ */
 static unsigned int pci0GetMemory0Size(void)
 {
 	unsigned int top, base, size;
@@ -317,12 +308,11 @@ static unsigned int pci0GetMemory0Size(void)
 	return (size + 1);
 }
 
-/********************************************************************
-* pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
-* Inputs: N/A
-* Returns: PCI0 Memory 1 Base Address.
-*********************************************************************/
-
+/*
+ * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 1 Base Address.
+ */
 static unsigned int pci0GetMemory1Base(void)
 {
 	unsigned int base;
@@ -331,11 +321,11 @@ static unsigned int pci0GetMemory1Base(void)
 	return base;
 }
 
-/********************************************************************
-* pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
-* Inputs: N/A
-* Returns: PCI0 Memory 1 Bar Size.
-*********************************************************************/
+/*
+ * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI0 Memory 1 Bar Size.
+ */
 
 static unsigned int pci0GetMemory1Size(void)
 {
@@ -349,11 +339,11 @@ static unsigned int pci0GetMemory1Size(void)
 	return (size + 1);
 }
 
-/********************************************************************
-* pci1GetIOspaceBase - Return PCI1 IO Base Address.
-* Inputs: N/A
-* Returns: PCI1 IO Base Address.
-*********************************************************************/
+/*
+ * pci1GetIOspaceBase - Return PCI1 IO Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 IO Base Address.
+ */
 
 static unsigned int pci1GetIOspaceBase(void)
 {
@@ -363,11 +353,11 @@ static unsigned int pci1GetIOspaceBase(void)
 	return base;
 }
 
-/********************************************************************
-* pci1GetIOspaceSize - Return PCI1 IO Bar Size.
-* Inputs: N/A
-* Returns: PCI1 IO Bar Size.
-*********************************************************************/
+/*
+ * pci1GetIOspaceSize - Return PCI1 IO Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 IO Bar Size.
+ */
 
 static unsigned int pci1GetIOspaceSize(void)
 {
@@ -381,11 +371,11 @@ static unsigned int pci1GetIOspaceSize(void)
 	return (size + 1);
 }
 
-/********************************************************************
-* pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
-* Inputs: N/A
-* Returns: PCI1 Memory 0 Base Address.
-*********************************************************************/
+/*
+ * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 0 Base Address.
+ */
 
 static unsigned int pci1GetMemory0Base(void)
 {
@@ -395,11 +385,11 @@ static unsigned int pci1GetMemory0Base(void)
 	return base;
 }
 
-/********************************************************************
-* pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
-* Inputs: N/A
-* Returns: PCI1 Memory 0 Bar Size.
-*********************************************************************/
+/*
+ * pci1GetMemory0Size - Return PCI1 Memory 0 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 0 Bar Size.
+ */
 
 static unsigned int pci1GetMemory0Size(void)
 {
@@ -413,11 +403,11 @@ static unsigned int pci1GetMemory0Size(void)
 	return (size + 1);
 }
 
-/********************************************************************
-* pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
-* Inputs: N/A
-* Returns: PCI1 Memory 1 Base Address.
-*********************************************************************/
+/*
+ * pci1GetMemory1Base - Return PCI1 Memory 1 Base Address.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 1 Base Address.
+ */
 
 static unsigned int pci1GetMemory1Base(void)
 {
@@ -427,11 +417,11 @@ static unsigned int pci1GetMemory1Base(void)
 	return base;
 }
 
-/********************************************************************
-* pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
-* Inputs: N/A
-* Returns: PCI1 Memory 1 Bar Size.
-*********************************************************************/
+/*
+ * pci1GetMemory1Size - Return PCI1 Memory 1 Bar Size.
+ * Inputs: N/A
+ * Returns: PCI1 Memory 1 Bar Size.
+ */
 
 static unsigned int pci1GetMemory1Size(void)
 {
@@ -447,19 +437,19 @@ static unsigned int pci1GetMemory1Size(void)
 
 
 
-/********************************************************************
- *pci_range_ck -
+/*
+ * pci_range_ck -
  *
- *Check if the pci device that are trying to access does really exists
- *on the evaluation board.  
+ * Check if the pci device that are trying to access does really exists
+ * on the evaluation board.  
  *
- *Inputs :
- *bus - bus number (0 for PCI 0 ; 1 for PCI 1)
- *dev - number of device on the specific pci bus
+ * Inputs :
+ * bus - bus number (0 for PCI 0 ; 1 for PCI 1)
+ * dev - number of device on the specific pci bus
  *
- *Outpus :
- *0 - if OK , 1 - if failure
- *********************************************************************/
+ * Outpus :
+ * 0 - if OK , 1 - if failure
+ */
 static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
 {
 	//DBG(KERN_INFO "p_r_c %d %d\n",bus,dev);
@@ -468,24 +458,24 @@ static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev)
 	return -1;		// Bus/Device Number not OK  
 }
 
-/********************************************************************
-* pciXReadConfigReg  - Read from a PCI configuration register
-*                    - Make sure the GT is configured as a master before 
-*                      reading from another device on the PCI.
-*                   - The function takes care of Big/Little endian conversion.
-* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
-*                        spec)
-*           pciDevNum: The device number needs to be addressed.                
-* RETURNS: data , if the data == 0xffffffff check the master abort bit in the 
-*                 cause register to make sure the data is valid
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
+/*
+ * pciXReadConfigReg  - Read from a PCI configuration register
+ *                    - Make sure the GT is configured as a master before 
+ *                      reading from another device on the PCI.
+ *                   - The function takes care of Big/Little endian conversion.
+ * INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+ *                        spec)
+ *           pciDevNum: The device number needs to be addressed.                
+ * RETURNS: data , if the data == 0xffffffff check the master abort bit in the 
+ *                 cause register to make sure the data is valid
+ *
+ *  Configuration Address 0xCF8:
+ *
+ *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+ *  |congif|Reserved|  Bus |Device|Function|Register|00|
+ *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+ *
+ */
 static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
 {
 	unsigned int DataForRegCf8;
@@ -506,7 +496,7 @@ static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device)
 	if (PCI_SLOT(device->devfn) == SELF) {	/* This board */
 		GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 		return data;
-	} else {		/* The PCI is working in LE Mode so swap the Data. */
+	} else {	/* The PCI is working in LE Mode so swap the Data. */
 		GT_READ(GT_PCI0_CFGDATA_OFS, &data);
 		return cpu_to_le32(data);
 	}
@@ -546,22 +536,23 @@ static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device)
 
 
 
-/********************************************************************
-* pciXWriteConfigReg - Write to a PCI configuration register
-*                    - Make sure the GT is configured as a master before 
-*                      writingto another device on the PCI.
-*                    - The function takes care of Big/Little endian conversion.
-* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec 
-*                   (or any other PCI device spec)
-*           pciDevNum: The device number needs to be addressed.                
-*
-*  Configuration Address 0xCF8:
-*
-*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
-*  |congif|Reserved|  Bus |Device|Function|Register|00|
-*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
-*
-*********************************************************************/
+/*
+ * pciXWriteConfigReg - Write to a PCI configuration register
+ *                    - Make sure the GT is configured as a master before 
+ *                      writingto another device on the PCI.
+ *                    - The function takes care of Big/Little endian conversion.
+ * Inputs:   unsigned int regOffset: The register offset as it apears in the
+ *           GT spec 
+ *                   (or any other PCI device spec)
+ *           pciDevNum: The device number needs to be addressed.                
+ *
+ *  Configuration Address 0xCF8:
+ *
+ *       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+ *  |congif|Reserved|  Bus |Device|Function|Register|00|
+ *  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+ *
+ */
 static void pci0WriteConfigReg(unsigned int offset,
 			       struct pci_dev *device, unsigned int data)
 {
@@ -609,23 +600,23 @@ static void pci1WriteConfigReg(unsigned int offset,
 }
 
 
-/********************************************************************
- *galileo_pcibios_(read/write)_config_(dword/word/byte) -
+/*
+ * galileo_pcibios_(read/write)_config_(dword/word/byte) -
  *
- *reads/write a dword/word/byte register from the configuration space
- *of a device.
+ * reads/write a dword/word/byte register from the configuration space
+ * of a device.
  *
- *Inputs :
- *bus - bus number
- *dev - device number
- *offset - register offset in the configuration space
- *val - value to be written / read
+ * Inputs :
+ * bus - bus number
+ * dev - device number
+ * offset - register offset in the configuration space
+ * val - value to be written / read
  *
- *Outputs :
- *PCIBIOS_SUCCESSFUL when operation was succesfull
- *PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
- *PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
- *********************************************************************/
+ * Outputs :
+ * PCIBIOS_SUCCESSFUL when operation was succesfull
+ * PCIBIOS_DEVICE_NOT_FOUND when the bus or dev is errorneous
+ * PCIBIOS_BAD_REGISTER_NUMBER when accessing non aligned
+ */
 
 static int galileo_pcibios_read_config_dword(struct pci_dev *device,
 					     int offset, u32 * val)
@@ -646,8 +637,10 @@ static int galileo_pcibios_read_config_dword(struct pci_dev *device,
 //  if (bus == 1) *val = pci1ReadConfigReg (offset,device);
 	DBG(KERN_INFO "rr: rcd dev %d offset %x %x\n", dev, offset, *val);
 
-	/*  This is so that the upper PCI layer will get the correct return value if
-	   we're not attached to anything.  */
+	/*
+	 * This is so that the upper PCI layer will get the correct return
+	 * value if we're not attached to anything.
+	 */
 	if ((offset == 0) && (*val == 0xffffffff)) {
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
@@ -671,12 +664,12 @@ static int galileo_pcibios_read_config_word(struct pci_dev *device,
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 
 	if (bus == 0)
-		*val =
-		    (unsigned short) (pci0ReadConfigReg(offset, device) >>
-				      ((offset & ~0x3) * 8));
+		*val = (unsigned short) (pci0ReadConfigReg(offset, device) >>
+				         ((offset & ~0x3) * 8));
 //  if (bus == 1) *val = (unsigned short) (pci1ReadConfigReg(offset,device) >> ((offset & ~0x3) * 8));
 
 	DBG(KERN_INFO "rr: rcw dev %d offset %x %x\n", dev, offset, *val);
+
 	return PCIBIOS_SUCCESSFUL;
 }
 
@@ -936,15 +929,13 @@ void pcibios_align_resource(void *data, struct resource *res,
 	}
 }
 
-/********************************************************************
- *structure galileo_pci_ops
- *
- *This structure holds the pointers for the PCI configuration space
- *access, and the fixup for the interrupts.
- *This structure is registered to the operating system in boot time
+/*
+ * structure galileo_pci_ops
  *
- *********************************************************************/
-
+ * This structure holds the pointers for the PCI configuration space
+ * access, and the fixup for the interrupts.
+ * This structure is registered to the operating system in boot time
+ */
 struct pci_ops galileo_pci_ops = {
 	galileo_pcibios_read_config_byte,
 	galileo_pcibios_read_config_word,
@@ -954,19 +945,19 @@ struct pci_ops galileo_pci_ops = {
 	galileo_pcibios_write_config_dword
 };
 
-/********************************************************************
- *galileo_pcibios_fixup_bus -
+/*
+ * galileo_pcibios_fixup_bus -
  *
- *After detecting all agents over the PCI , this function is called
- *in order to give an interrupt number for each PCI device starting
- *from IRQ 20. It does also enables master for each device.
+ * After detecting all agents over the PCI , this function is called
+ * in order to give an interrupt number for each PCI device starting
+ * from IRQ 20. It does also enables master for each device.
  *
- *Inputs :
- *mem_start , mem_end are not relevant in MIPS architecture.
+ * Inputs :
+ * mem_start , mem_end are not relevant in MIPS architecture.
  *
- *Outpus :
- *return always mem_start
- *********************************************************************/
+ * Outpus :
+ * return always mem_start
+ */
 static void __init galileo_pcibios_fixup_bus(struct pci_bus *bus)
 {
 	unsigned int Current_IRQ = 20;
@@ -1002,14 +993,13 @@ void __init pcibios_fixup_bus(struct pci_bus *c)
 }
 
 /*
-  This code was derived from Galileo Technology's example
-  and significantly reworked.
-
-  This is very simple.  It does not scan multiple function devices.  It does not
-  scan behind bridges.  Those would be simple to implement, but we don't currently
-  need this.
-*/
-
+ * This code was derived from Galileo Technology's example
+ * and significantly reworked.
+ *
+ * This is very simple.  It does not scan multiple function devices.  It does
+ * not scan behind bridges.  Those would be simple to implement, but we don't
+ * currently need this.
+ */
 static void __init scan_and_initialize_pci(void)
 {
 	struct pci_device pci_devices[MAX_PCI_DEVS];
@@ -1020,10 +1010,10 @@ static void __init scan_and_initialize_pci(void)
 }
 
 /*
-  This is your basic PCI scan.  It goes through each slot and checks to
-  see if there's something that responds.  If so, then get the size and
-  type of each of the responding BARs.  Save them for later.
-*/
+ * This is your basic PCI scan.  It goes through each slot and checks to
+ * see if there's something that responds.  If so, then get the size and
+ * type of each of the responding BARs.  Save them for later.
+ */
 
 static u32 __init scan_pci_bus(struct pci_device *pci_devices)
 {
@@ -1098,10 +1088,10 @@ static u32 __init scan_pci_bus(struct pci_device *pci_devices)
 #define MAX(val1, val2) ((val1) > (val2) ? (val1) : (val2))
 
 /*
-  This function goes through the list of devices and allocates the BARs in
-  either IO or MEM space.  It does it in order of size, which will limit the
-  amount of fragmentation we have in the IO and MEM spaces.
-*/
+ * This function goes through the list of devices and allocates the BARs in
+ * either IO or MEM space.  It does it in order of size, which will limit the
+ * amount of fragmentation we have in the IO and MEM spaces.
+ */
 
 static void __init allocate_pci_space(struct pci_device *pci_devices)
 {
@@ -1205,10 +1195,10 @@ void __init pcibios_init(void)
 	GT_READ(GT_PCI0_BARE_OFS, &tmp);
 	DBG(KERN_INFO "rr: BAR0 - %x\n", tmp);
 
-/*
-  You have to enable bus mastering to configure any other
-  card on the bus.
-*/
+	/*
+	 * You have to enable bus mastering to configure any other
+	 * card on the bus.
+	 */
 	tmp = pci0ReadConfigReg(PCI_COMMAND, &controller);
 	DBG(KERN_INFO "rr: command/status - %x\n", tmp);
 	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
@@ -1218,8 +1208,8 @@ void __init pcibios_init(void)
 	/*  This scans the PCI bus and sets up initial values.  */
 	scan_and_initialize_pci();
 
-	/*  Reset PCI I/O and PCI MEM values to ones supported
-	   by EVM.
+	/*
+	 * Reset PCI I/O and PCI MEM values to ones supported by EVM.
 	 */
 	ioport_resource.start = 0x10000000;
 	ioport_resource.end = 0x11ffffff;	/*  32 MB */
@@ -1263,4 +1253,4 @@ void pci_free_consistent(struct pci_dev *hwdev, size_t size,
 }
 #endif
 
-#endif				/* CONFIG_PCI */
+#endif /* CONFIG_PCI */
diff --git a/arch/mips/galileo-boards/generic/pci.c b/arch/mips/galileo-boards/generic/pci.c
index c49e86963..f88bca012 100644
--- a/arch/mips/galileo-boards/generic/pci.c
+++ b/arch/mips/galileo-boards/generic/pci.c
@@ -1,5 +1,4 @@
 /*
- *
  * BRIEF MODULE DESCRIPTION
  *	Galileo EV96100 board specific pci support.
  *
@@ -43,7 +42,7 @@
 #include <linux/init.h>
 
 #include <asm/galileo-boards/ev96100.h>
-#include <asm/galileo-boards/gt64120.h>
+#include <asm/gt64120.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index 388ea3c9a..d11a4d8ac 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -2,8 +2,6 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  *
- * ########################################################################
- *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
@@ -17,10 +15,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
- * ########################################################################
- *
- * Atlas specific setup, including init of the feature struct.
- *
+ * Atlas specific setup.
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -33,7 +28,7 @@
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
-#include <asm/mips-boards/gt64120.h>
+#include <asm/gt64120.h>
 #include <asm/mips-boards/atlasint.h>
 
 #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 9fee19547..90b67001e 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -2,8 +2,6 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
  *
- * ########################################################################
- *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
@@ -17,8 +15,6 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
- * ########################################################################
- *
  * MIPS boards specific PCI support.
  *
  */
@@ -32,7 +28,7 @@
 #include <linux/init.h>
 
 #include <asm/mips-boards/generic.h>
-#include <asm/mips-boards/gt64120.h>
+#include <asm/gt64120.h>
 #ifdef CONFIG_MIPS_MALTA
 #include <asm/mips-boards/malta.h>
 #endif
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 62932ace8..8f90e6413 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -2,8 +2,6 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  *
- * ########################################################################
- *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *  published by the Free Software Foundation.
@@ -17,13 +15,10 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  *
- * ########################################################################
- *
  * Routines for generic manipulation of the interrupts found on the MIPS 
  * Malta board.
  * The interrupt controller is located in the South Bridge a PIIX4 device 
  * with two internal 82C95 interrupt controllers.
- *
  */
 #include <linux/config.h>
 #include <linux/init.h>
@@ -38,7 +33,7 @@
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
 #include <asm/mips-boards/piix4.h>
-#include <asm/mips-boards/gt64120.h>
+#include <asm/gt64120.h>
 #include <asm/mips-boards/generic.h>
 
 extern asmlinkage void mipsIRQ(void);