Merge with Linux 2.2.8.

1 files changed, 26 insertions, 90 deletions

diff --git a/arch/ppc/boot/head.S b/arch/ppc/boot/head.S
index 43facf7e2..552e82fa1 100644
--- a/arch/ppc/boot/head.S
+++ b/arch/ppc/boot/head.S
@@ -1,4 +1,3 @@
-#include <linux/config.h>
 #include "../kernel/ppc_defs.h"
 #include "../kernel/ppc_asm.tmpl"
 #include <asm/processor.h>
@@ -7,43 +6,24 @@
 	.text
 
 /*
- * $Id: head.S,v 1.26 1998/09/19 01:21:20 cort Exp $
+ * $Id: head.S,v 1.31 1999/04/22 06:32:00 davem Exp $
  *	
- * This code is loaded by the ROM loader at some arbitrary location.
- * Move it to high memory so that it can load the kernel at 0x0000.
- *
- * The MBX EPPC-Bug understands ELF, so it loads us into the location
- * specified in the header.  This is a two step process.  First, EPPC-Bug
- * loads the file into the intermediate buffer memory location specified
- * by the environment parameters.  When it discovers this is an ELF
- * binary, it relocates to the link address for us.  Unfortunately, the
- * header does not move with the file, so we have to find the
- * intermediate load location and read the header from there.  From
- * information provided by Motorola (thank you), we know this intermediate
- * location can be found from the NVRAM environment.
- * All of these addresses must be somewhat carefully chosen to make sure
- * we don't overlap the regions.  I chose to load the kernel at 0, the
- * compressed image loads at 0x00100000, and the MBX intermediate buffer
- * was set to 0x00200000.  Provided the loaded kernel image never grows
- * over one megabyte (which I am going to ensure never happens :-), these
- * will work fine.  When we get called from EPPC-Bug, registers are:
- *              R1 - Stack pointer at a high memory address.
- *              R3 - Pointer to Board Information Block.
- *              R4 - Pointer to argument string.
- *              Interrupts masked, cache and MMU disabled.
+ * Boot loader philosophy:
+ *      ROM loads us to some arbitrary location
+ *      Move the boot code to the link address (8M)
+ *      Call decompress_kernel()
+ *         Relocate the initrd, zimage and residual data to 8M
+ *         Decompress the kernel to 0
+ *      Jump to the kernel entry
+ *            -- Cort
  */
-
 	.globl	start
 start:
 	bl	start_
 start_:
 	mr	r11,r3		/* Save pointer to residual/board data */
-	
-#ifndef CONFIG_MBX
-	mfmsr	r3		/* Turn off interrupts  */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r3,r3,r4
+	mr      r25,r5          /* Save OFW pointer */
+	li	r3,MSR_IP	/* Establish default MSR value */
 	mtmsr	r3
 
 /* check if we need to relocate ourselves to the link addr or were we
@@ -68,25 +48,6 @@ start_:
 	mr	r7,r5
 	b	start_ldr
 1010:
-#if 0	
-/* Copy relocation code down to location 0x0100 (where we hope it's safe!) */
-	mflr	r3
-	addi	r5,r3,start_ldr-start_
-	addi	r3,r3,relocate-start_
-	li	r4,0x0100
-	mtctr	r4
-	subi	r3,r3,4
-	subi	r4,r4,4
-00:	lwzu	r6,4(r3)
-	stwu	r6,4(r4)
-	cmp	0,r3,r5
-	bne	00b
-	mflr	r21
-	mfctr	r22
-	mtlr	r21
-	mtctr	r22
-	bctr			/* Jump to code */
-#endif	
 /* 
  * no matter where we're loaded, move ourselves to -Ttext address
  */
@@ -96,13 +57,8 @@ relocate:
 	mr	r8,r3
 	lis	r4,start@h
 	ori	r4,r4,start@l
-#if 0	
-	lis	r5,edata@h
-	ori	r5,r5,edata@l
-#else
 	lis	r5,end@h
 	ori	r5,r5,end@l
-#endif		
 	addi	r5,r5,3			/* Round up - just in case */
 	sub	r5,r5,r4		/* Compute # longwords to move */
 	srwi	r5,r5,2
@@ -120,7 +76,6 @@ relocate:
 	mtlr	r3			/* Easiest way to do an absolute jump */
 	blr
 start_ldr:
-#endif /* ndef CONFIG_MBX */
 /* Clear all of BSS */
 	lis	r3,edata@h
 	ori	r3,r3,edata@l
@@ -140,31 +95,11 @@ start_ldr:
 	li	r2,0x000F		/* Mask pointer to 16-byte boundary */
 	andc	r1,r1,r2
 /* Run loader */
-#ifdef CONFIG_MBX
-	mr	r3, r11
-        mr      r21, r11
-	bl      serial_init		/* Init MBX serial port */
-
-	lis	r8, 0xfa200000@h	/* Disable Ethernet SCC */
-	li	r0, 0
-	stw	r0, 0x0a00(r8)
-
-	mr      r11, r21
-	lis	r8,start@h
-	ori	r8,r8,start@l
-	li	r9,end@h
-	ori	r9,r9,end@l
-	sub	r7,r8,r9
-	srwi	r7,r7,2
-#define ILAP_ADDRESS    0xfa000020
-        lis     r8, ILAP_ADDRESS@h
-        lwz     r8, ILAP_ADDRESS@l(r8)
-        addis   r8, r8, 1               /* Add 64K */
-#endif	
 	mr	r3,r8			/* Load point */
 	mr	r4,r7			/* Program length */
 	mr	r5,r6			/* Checksum */
 	mr	r6,r11			/* Residual data */
+	mr      r7,r25                  /* OFW interfaces */
 	bl	decompress_kernel
 	
 	/* changed to use r3 (as firmware does) for kernel
@@ -193,12 +128,24 @@ start_ldr:
 	li	r9,0x0
 	lwz	r9,0(r9)
 	mtlr	r9
-#ifndef CONFIG_MBX
 	li	r9,0
 	lis	r10,0xdeadc0de@h
 	ori	r10,r10,0xdeadc0de@l
 	stw	r10,0(r9)
-#endif
+/*
+ * The Radstone firmware maps PCI memory at 0xc0000000 using BAT2
+ * so disable BATs before setting this to avoid a clash
+ */
+	li      r8,0
+	mtspr   DBAT0U,r8
+	mtspr   DBAT1U,r8
+	mtspr   DBAT2U,r8
+	mtspr   DBAT3U,r8
+	mtspr   IBAT0U,r8
+	mtspr   IBAT1U,r8
+	mtspr   IBAT2U,r8
+	mtspr   IBAT3U,r8
+
 	blr
 hang:
 	b	hang	
@@ -269,7 +216,6 @@ _put_MSR:
 _GLOBAL(flush_instruction_cache)
 	mflr	r5
 	bl	flush_data_cache
-#ifndef CONFIG_MBX
 	mfspr	r3,HID0	/* Caches are controlled by this register */
 	li	r4,0
 	ori	r4,r4,(HID0_ICE|HID0_ICFI)
@@ -278,18 +224,12 @@ _GLOBAL(flush_instruction_cache)
 	andc	r3,r3,r4
 	ori	r3,r3,HID0_ICE	/* Enable cache */
 	mtspr	HID0,r3
-#endif	
 	mtlr	r5
 	blr
 	
 #define NUM_CACHE_LINES 128*8
 #define CACHE_LINE_SIZE 32 
-#if 0
-cache_flush_buffer:
-	.space	NUM_CACHE_LINES*CACHE_LINE_SIZE	/* CAUTION! these need to match hardware */
-#else
 #define cache_flush_buffer 0x1000
-#endif
 
 /*
  * Flush data cache
@@ -300,11 +240,7 @@ _GLOBAL(flush_data_cache)
 	ori	r3,r3,cache_flush_buffer@l
 	li	r4,NUM_CACHE_LINES
 	mtctr	r4
-#if 0
-00:	dcbz	0,r3			/* Flush cache line with minimal BUS traffic */
-#else
 00:	lwz	r4,0(r3)
-#endif
 	addi	r3,r3,CACHE_LINE_SIZE	/* Next line, please */
 	bdnz	00b	
 10:	blr