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authorRalf Baechle <ralf@linux-mips.org>2000-02-18 00:24:27 +0000
committerRalf Baechle <ralf@linux-mips.org>2000-02-18 00:24:27 +0000
commitb9558d5f86c471a125abf1fb3a3882fb053b1f8c (patch)
tree707b53ec64e740a7da87d5f36485e3cd9b1c794e /arch/ppc/kernel
parentb3ac367c7a3e6047abe74817db27e34e759f279f (diff)
Merge with Linux 2.3.41.
Diffstat (limited to 'arch/ppc/kernel')
-rw-r--r--arch/ppc/kernel/entry.S21
-rw-r--r--arch/ppc/kernel/i8259.c18
-rw-r--r--arch/ppc/kernel/misc.S4
3 files changed, 31 insertions, 12 deletions
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index cb92163d6..2c4ff5554 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -271,6 +271,7 @@ ret_from_smpfork:
bl schedule_tail
b ret_from_except
#endif
+
.globl ret_from_intercept
ret_from_intercept:
/*
@@ -278,7 +279,16 @@ ret_from_intercept:
* -- Cort
*/
cmpi 0,r3,0
- beq 10f
+ bne ret_from_except
+ /*
+ * If we're returning from user mode we do things differently
+ * -- Cort
+ */
+ lwz r3,_MSR(r1)
+ andi. r3,r3,MSR_PR
+ beq+ 10f
+ b 8f
+
.globl ret_from_except
ret_from_except:
0: /* disable interrupts */
@@ -315,7 +325,6 @@ do_bottom_half_ret:
lwz r30,0(r30)
mtlr r30
blrl
-
lwz r3,_MSR(r1) /* Returning to user mode? */
andi. r3,r3,MSR_PR
beq+ 10f /* if so, check need_resched and signals */
@@ -337,7 +346,13 @@ do_signal_ret:
stw r4,THREAD+KSP(r2) /* save kernel stack pointer */
tophys(r3,r1)
mtspr SPRG2,r3 /* phys exception stack pointer */
-10: lwz r2,_CTR(r1)
+10: /* make sure we hard disable here, even if rtl is active -- Cort */
+ mfmsr r0 /* Get current interrupt state */
+ rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
+ sync /* Some chip revs have problems here... */
+ mtmsr r0 /* Update machine state */
+
+ lwz r2,_CTR(r1)
lwz r0,_LINK(r1)
mtctr r2
mtlr r0
diff --git a/arch/ppc/kernel/i8259.c b/arch/ppc/kernel/i8259.c
index 3a3a16d9e..5dfe902df 100644
--- a/arch/ppc/kernel/i8259.c
+++ b/arch/ppc/kernel/i8259.c
@@ -10,6 +10,8 @@ unsigned char cached_8259[2] = { 0xff, 0xff };
#define cached_A1 (cached_8259[0])
#define cached_21 (cached_8259[1])
+int i8259_pic_irq_offset;
+
int i8259_irq(int cpu)
{
int irq;
@@ -46,8 +48,8 @@ int i8259_irq(int cpu)
static void i8259_mask_and_ack_irq(unsigned int irq_nr)
{
- if ( irq_nr >= i8259_pic.irq_offset )
- irq_nr -= i8259_pic.irq_offset;
+ if ( irq_nr >= i8259_pic_irq_offset )
+ irq_nr -= i8259_pic_irq_offset;
if (irq_nr > 7) {
cached_A1 |= 1 << (irq_nr-8);
@@ -71,8 +73,8 @@ static void i8259_set_irq_mask(int irq_nr)
static void i8259_mask_irq(unsigned int irq_nr)
{
- if ( irq_nr >= i8259_pic.irq_offset )
- irq_nr -= i8259_pic.irq_offset;
+ if ( irq_nr >= i8259_pic_irq_offset )
+ irq_nr -= i8259_pic_irq_offset;
if ( irq_nr < 8 )
cached_21 |= 1 << irq_nr;
else
@@ -83,8 +85,8 @@ static void i8259_mask_irq(unsigned int irq_nr)
static void i8259_unmask_irq(unsigned int irq_nr)
{
- if ( irq_nr >= i8259_pic.irq_offset )
- irq_nr -= i8259_pic.irq_offset;
+ if ( irq_nr >= i8259_pic_irq_offset )
+ irq_nr -= i8259_pic_irq_offset;
if ( irq_nr < 8 )
cached_21 &= ~(1 << irq_nr);
else
@@ -123,7 +125,7 @@ void __init i8259_init(void)
outb(0xFF, 0xA1); /* Mask all */
outb(cached_A1, 0xA1);
outb(cached_21, 0x21);
- request_irq( i8259_pic.irq_offset + 2, no_action, SA_INTERRUPT,
+ request_irq( i8259_pic_irq_offset + 2, no_action, SA_INTERRUPT,
"82c59 secondary cascade", NULL );
- enable_irq(i8259_pic.irq_offset + 2); /* Enable cascade interrupt */
+ enable_irq(i8259_pic_irq_offset + 2); /* Enable cascade interrupt */
}
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 444654ec6..aa9f5ac83 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -1068,4 +1068,6 @@ _GLOBAL(sys_call_table)
.long sys_ni_syscall /* streams2 */
.long sys_vfork
.long sys_getrlimit /* 190 */
- .space (NR_syscalls-190)*4
+ .rept NR_syscalls-190
+ .long sys_ni_syscall
+ .endr