diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1999-10-09 00:00:47 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 1999-10-09 00:00:47 +0000 |
| commit | d6434e1042f3b0a6dfe1b1f615af369486f9b1fa (patch) | |
| tree | e2be02f33984c48ec019c654051d27964e42c441 /arch/sh/kernel/head.S | |
| parent | 609d1e803baf519487233b765eb487f9ec227a18 (diff) | |
Merge with 2.3.19.
Diffstat (limited to 'arch/sh/kernel/head.S')
| -rw-r--r-- | arch/sh/kernel/head.S | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S new file mode 100644 index 000000000..ed466ba38 --- /dev/null +++ b/arch/sh/kernel/head.S @@ -0,0 +1,69 @@ +/* $Id$ + * + * arch/sh/kernel/head.S + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Head.S contains the SH exception handlers and startup code. + */ +#include <linux/config.h> +#include <linux/threads.h> +#include <linux/linkage.h> +#include <asm/page.h> +#include <asm/pgtable.h> + +#ifdef CONFIG_CPU_SH3 +/* Following values are assumed to be as small as immediate. */ +#define CCR 0xffffffec /* Address of Cache Control Register */ +#define CACHE_INIT 0x00000009 /* 8k-byte cache, flush, enable */ +#elif CONFIG_CPU_SH4 +/* Should fill here. */ +#endif + +ENTRY(_stext) + ! Switch to register bank 0 + stc sr,r1 ! + mov.l 1f,r0 ! RB=0, BL=1 + and r1,r0 + ldc r0,sr + ! Enable cache +#ifdef CONFIG_CPU_SH3 + mov #CCR,r1 + mov.l @r1,r0 + cmp/eq #1,r0 ! If it's enabled already, don't flush it + bt/s 8f + mov #CACHE_INIT,r0 + mov.l r0,@r1 +#elif CONFIG_CPU_SH4 + ! Should fill here. +#endif +8: + ! + mov.l 2f,r0 + mov r0,r15 ! Set initial r15 (stack pointer) + ldc r0,r4_bank ! and stack base + ! Clear BSS area + mov.l 3f,r1 + mov.l 4f,r2 + mov #0,r0 +9: mov.l r0,@r1 + cmp/hs r2,r1 + bf/s 9b + add #4,r1 + ! Start kernel + mov.l 5f,r0 + jmp @r0 + nop + + .balign 4 +1: .long 0xdfffffff ! RB=0, BL=1 +2: .long SYMBOL_NAME(stack) +3: .long SYMBOL_NAME(__bss_start) +4: .long SYMBOL_NAME(_end) +5: .long SYMBOL_NAME(start_kernel) + +.data |