Merge with Linux 2.4.1.

13 files changed, 310 insertions, 79 deletions

diff --git a/arch/sparc64/kernel/ioctl32.c b/arch/sparc64/kernel/ioctl32.c
index 81e11af70..67c1ec6d0 100644
--- a/arch/sparc64/kernel/ioctl32.c
+++ b/arch/sparc64/kernel/ioctl32.c
@@ -1,4 +1,4 @@
-/* $Id: ioctl32.c,v 1.104 2001/01/03 09:28:19 anton Exp $
+/* $Id: ioctl32.c,v 1.105 2001/01/18 04:47:44 davem Exp $
  * ioctl32.c: Conversion between 32bit and 64bit native ioctls.
  *
  * Copyright (C) 1997-2000  Jakub Jelinek  (jakub@redhat.com)
@@ -73,6 +73,7 @@
 #include <asm/audioio.h>
 #include <linux/ethtool.h>
 #include <asm/display7seg.h>
+#include <asm/watchdog.h>
 #include <asm/module.h>
 #include <linux/soundcard.h>
 
@@ -3600,6 +3601,16 @@ COMPATIBLE_IOCTL(DRM_IOCTL_FINISH)
 /* elevator */
 COMPATIBLE_IOCTL(BLKELVGET)
 COMPATIBLE_IOCTL(BLKELVSET)
+/* Big W */
+/* WIOC_GETSUPPORT not yet implemented -E */
+COMPATIBLE_IOCTL(WDIOC_GETSTATUS)
+COMPATIBLE_IOCTL(WDIOC_GETBOOTSTATUS)
+COMPATIBLE_IOCTL(WDIOC_GETTEMP)
+COMPATIBLE_IOCTL(WDIOC_SETOPTIONS)
+COMPATIBLE_IOCTL(WDIOC_KEEPALIVE)
+COMPATIBLE_IOCTL(WIOCSTART)
+COMPATIBLE_IOCTL(WIOCSTOP)
+COMPATIBLE_IOCTL(WIOCGSTAT)
 /* And these ioctls need translation */
 HANDLE_IOCTL(SIOCGIFNAME, dev_ifname32)
 HANDLE_IOCTL(SIOCGIFCONF, dev_ifconf)
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 2b697dd87..009900165 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -1,4 +1,4 @@
-/* $Id: pci.c,v 1.20 2000/12/14 22:57:25 davem Exp $
+/* $Id: pci.c,v 1.21 2001/01/10 18:22:59 davem Exp $
  * pci.c: UltraSparc PCI controller support.
  *
  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
@@ -78,6 +78,9 @@ volatile int pci_poke_faulted;
 /* Probe for all PCI controllers in the system. */
 extern void sabre_init(int);
 extern void psycho_init(int);
+#if 0
+extern void schizo_init(int);
+#endif
 
 static struct {
 	char *model_name;
@@ -87,6 +90,10 @@ static struct {
 	{ "pci108e,a000", sabre_init },
 	{ "SUNW,psycho", psycho_init },
 	{ "pci108e,8000", psycho_init }
+#if 0
+	{ "SUNW,schizo", schizo_init },
+	{ "pci108e,8001", schizo_init }
+#endif
 };
 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 				  sizeof(pci_controller_table[0]))
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index d7267880a..08d5b8ee3 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -1,4 +1,4 @@
-/* $Id: pci_iommu.c,v 1.11 2000/03/10 02:42:15 davem Exp $
+/* $Id: pci_iommu.c,v 1.12 2001/01/11 16:26:45 davem Exp $
  * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
  *
  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
@@ -187,7 +187,7 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_ad
 	memset((char *)first_page, 0, PAGE_SIZE << order);
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 
 	spin_lock_irqsave(&iommu->lock, flags);
 	iopte = alloc_consistent_cluster(iommu, size >> PAGE_SHIFT);
@@ -241,7 +241,7 @@ void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_
 
 	npages = PAGE_ALIGN(size) >> PAGE_SHIFT;
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	iopte = iommu->page_table +
 		((dvma - iommu->page_table_map_base) >> PAGE_SHIFT);
 
@@ -308,7 +308,7 @@ dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direct
 	unsigned long iopte_protection;
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 
 	if (direction == PCI_DMA_NONE)
@@ -356,7 +356,7 @@ void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int
 		BUG();
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 
 	npages = PAGE_ALIGN(bus_addr + sz) - (bus_addr & PAGE_MASK);
@@ -504,7 +504,7 @@ int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int
 	}
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 	
 	if (direction == PCI_DMA_NONE)
@@ -568,7 +568,7 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
 		BUG();
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 	
 	bus_addr = sglist->dvma_address & PAGE_MASK;
@@ -639,7 +639,7 @@ void pci_dma_sync_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, i
 	unsigned long flags, ctx, npages;
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 
 	if (!strbuf->strbuf_enabled)
@@ -700,7 +700,7 @@ void pci_dma_sync_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelem
 	unsigned long flags, ctx;
 
 	pcp = pdev->sysdata;
-	iommu = &pcp->pbm->parent->iommu;
+	iommu = pcp->pbm->iommu;
 	strbuf = &pcp->pbm->stc;
 
 	if (!strbuf->strbuf_enabled)
@@ -762,7 +762,7 @@ int pci_dma_supported(struct pci_dev *pdev, dma_addr_t device_mask)
 	if (pdev == NULL) {
 		dma_addr_mask = 0xffffffff;
 	} else {
-		struct pci_iommu *iommu = &pcp->pbm->parent->iommu;
+		struct pci_iommu *iommu = pcp->pbm->iommu;
 
 		dma_addr_mask = iommu->dma_addr_mask;
 	}
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
index aff2de594..fbd7832cd 100644
--- a/arch/sparc64/kernel/pci_psycho.c
+++ b/arch/sparc64/kernel/pci_psycho.c
@@ -1,4 +1,4 @@
-/* $Id: pci_psycho.c,v 1.17 2000/09/21 06:25:14 anton Exp $
+/* $Id: pci_psycho.c,v 1.18 2001/01/11 16:26:45 davem Exp $
  * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
  *
  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
@@ -619,20 +619,21 @@ static void psycho_check_iommu_error(struct pci_controller_info *p,
 				     unsigned long afar,
 				     enum psycho_error_type type)
 {
+	struct pci_iommu *iommu = p->pbm_A.iommu;
 	unsigned long iommu_tag[16];
 	unsigned long iommu_data[16];
 	unsigned long flags;
 	u64 control;
 	int i;
 
-	spin_lock_irqsave(&p->iommu.lock, flags);
-	control = psycho_read(p->iommu.iommu_control);
+	spin_lock_irqsave(&iommu->lock, flags);
+	control = psycho_read(iommu->iommu_control);
 	if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
 		char *type_string;
 
 		/* Clear the error encountered bit. */
 		control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
-		psycho_write(p->iommu.iommu_control, control);
+		psycho_write(iommu->iommu_control, control);
 
 		switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
 		case 0:
@@ -662,7 +663,7 @@ static void psycho_check_iommu_error(struct pci_controller_info *p,
 		 * get as much diagnostic information to the
 		 * console as we can.
 		 */
-		psycho_write(p->iommu.iommu_control,
+		psycho_write(iommu->iommu_control,
 			     control | PSYCHO_IOMMU_CTRL_DENAB);
 		for (i = 0; i < 16; i++) {
 			unsigned long base = p->controller_regs;
@@ -678,7 +679,7 @@ static void psycho_check_iommu_error(struct pci_controller_info *p,
 		}
 
 		/* Leave diagnostic mode. */
-		psycho_write(p->iommu.iommu_control, control);
+		psycho_write(iommu->iommu_control, control);
 
 		for (i = 0; i < 16; i++) {
 			unsigned long tag, data;
@@ -717,7 +718,7 @@ static void psycho_check_iommu_error(struct pci_controller_info *p,
 		}
 	}
 	__psycho_check_stc_error(p, afsr, afar, type);
-	spin_unlock_irqrestore(&p->iommu.lock, flags);
+	spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
 /* Uncorrectable Errors.  Cause of the error and the address are
@@ -1255,24 +1256,25 @@ static void __init psycho_scan_bus(struct pci_controller_info *p)
 
 static void __init psycho_iommu_init(struct pci_controller_info *p)
 {
+	struct pci_iommu *iommu = p->pbm_A.iommu;
 	unsigned long tsbbase, i;
 	u64 control;
 
 	/* Setup initial software IOMMU state. */
-	spin_lock_init(&p->iommu.lock);
-	p->iommu.iommu_cur_ctx = 0;
+	spin_lock_init(&iommu->lock);
+	iommu->iommu_cur_ctx = 0;
 
 	/* Register addresses. */
-	p->iommu.iommu_control  = p->controller_regs + PSYCHO_IOMMU_CONTROL;
-	p->iommu.iommu_tsbbase  = p->controller_regs + PSYCHO_IOMMU_TSBBASE;
-	p->iommu.iommu_flush    = p->controller_regs + PSYCHO_IOMMU_FLUSH;
+	iommu->iommu_control  = p->controller_regs + PSYCHO_IOMMU_CONTROL;
+	iommu->iommu_tsbbase  = p->controller_regs + PSYCHO_IOMMU_TSBBASE;
+	iommu->iommu_flush    = p->controller_regs + PSYCHO_IOMMU_FLUSH;
 	/* PSYCHO's IOMMU lacks ctx flushing. */
-	p->iommu.iommu_ctxflush = 0;
+	iommu->iommu_ctxflush = 0;
 
 	/* We use the main control register of PSYCHO as the write
 	 * completion register.
 	 */
-	p->iommu.write_complete_reg = p->controller_regs + PSYCHO_CONTROL;
+	iommu->write_complete_reg = p->controller_regs + PSYCHO_CONTROL;
 
 	/*
 	 * Invalidate TLB Entries.
@@ -1298,19 +1300,19 @@ static void __init psycho_iommu_init(struct pci_controller_info *p)
 		prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
 		prom_halt();
 	}
-	p->iommu.page_table = (iopte_t *)tsbbase;
-	p->iommu.page_table_sz_bits = 17;
-	p->iommu.page_table_map_base = 0xc0000000;
-	p->iommu.dma_addr_mask = 0xffffffff;
+	iommu->page_table = (iopte_t *)tsbbase;
+	iommu->page_table_sz_bits = 17;
+	iommu->page_table_map_base = 0xc0000000;
+	iommu->dma_addr_mask = 0xffffffff;
 	memset((char *)tsbbase, 0, PAGE_SIZE << 7);
 
 	/* We start with no consistent mappings. */
-	p->iommu.lowest_consistent_map =
-		1 << (p->iommu.page_table_sz_bits - PBM_LOGCLUSTERS);
+	iommu->lowest_consistent_map =
+		1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
 
 	for (i = 0; i < PBM_NCLUSTERS; i++) {
-		p->iommu.alloc_info[i].flush = 0;
-		p->iommu.alloc_info[i].next = 0;
+		iommu->alloc_info[i].flush = 0;
+		iommu->alloc_info[i].next = 0;
 	}
 
 	psycho_write(p->controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));
@@ -1515,6 +1517,7 @@ void __init psycho_init(int node)
 {
 	struct linux_prom64_registers pr_regs[3];
 	struct pci_controller_info *p;
+	struct pci_iommu *iommu;
 	unsigned long flags;
 	u32 upa_portid;
 	int is_pbm_a, err;
@@ -1538,6 +1541,13 @@ void __init psycho_init(int node)
 		prom_halt();
 	}
 	memset(p, 0, sizeof(*p));
+	iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
+	if (!iommu) {
+		prom_printf("PSYCHO: Fatal memory allocation error.\n");
+		prom_halt();
+	}
+	memset(iommu, 0, sizeof(*iommu));
+	p->pbm_A.iommu = p->pbm_B.iommu = iommu;
 
 	spin_lock_irqsave(&pci_controller_lock, flags);
 	p->next = pci_controller_root;
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
index f3a5adbec..ec74a3696 100644
--- a/arch/sparc64/kernel/pci_sabre.c
+++ b/arch/sparc64/kernel/pci_sabre.c
@@ -1,4 +1,4 @@
-/* $Id: pci_sabre.c,v 1.20 2000/06/26 19:40:27 davem Exp $
+/* $Id: pci_sabre.c,v 1.22 2001/01/16 13:03:48 anton Exp $
  * pci_sabre.c: Sabre specific PCI controller support.
  *
  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
@@ -672,14 +672,15 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
 				    unsigned long afsr,
 				    unsigned long afar)
 {
+	struct pci_iommu *iommu = p->pbm_A.iommu;
 	unsigned long iommu_tag[16];
 	unsigned long iommu_data[16];
 	unsigned long flags;
 	u64 control;
 	int i;
 
-	spin_lock_irqsave(&p->iommu.lock, flags);
-	control = sabre_read(p->iommu.iommu_control);
+	spin_lock_irqsave(&iommu->lock, flags);
+	control = sabre_read(iommu->iommu_control);
 	if (control & SABRE_IOMMUCTRL_ERR) {
 		char *type_string;
 
@@ -687,7 +688,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
 		 * NOTE: On Sabre this is write 1 to clear,
 		 *       which is different from Psycho.
 		 */
-		sabre_write(p->iommu.iommu_control, control);
+		sabre_write(iommu->iommu_control, control);
 		switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 		case 1:
 			type_string = "Invalid Error";
@@ -706,7 +707,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
 		 * entries in the IOTLB.
 		 */
 		control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
-		sabre_write(p->iommu.iommu_control,
+		sabre_write(iommu->iommu_control,
 			    (control | SABRE_IOMMUCTRL_DENAB));
 		for (i = 0; i < 16; i++) {
 			unsigned long base = p->controller_regs;
@@ -718,7 +719,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
 			sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 			sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 		}
-		sabre_write(p->iommu.iommu_control, control);
+		sabre_write(iommu->iommu_control, control);
 
 		for (i = 0; i < 16; i++) {
 			unsigned long tag, data;
@@ -752,7 +753,7 @@ static void sabre_check_iommu_error(struct pci_controller_info *p,
 			       ((data & SABRE_IOMMUDATA_PPN) << PAGE_SHIFT));
 		}
 	}
-	spin_unlock_irqrestore(&p->iommu.lock, flags);
+	spin_unlock_irqrestore(&iommu->lock, flags);
 }
 
 static void sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
@@ -1158,20 +1159,21 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
 				    int tsbsize, unsigned long dvma_offset,
 				    u32 dma_mask)
 {
+	struct pci_iommu *iommu = p->pbm_A.iommu;
 	unsigned long tsbbase, i, order;
 	u64 control;
 
 	/* Setup initial software IOMMU state. */
-	spin_lock_init(&p->iommu.lock);
-	p->iommu.iommu_cur_ctx = 0;
+	spin_lock_init(&iommu->lock);
+	iommu->iommu_cur_ctx = 0;
 
 	/* Register addresses. */
-	p->iommu.iommu_control  = p->controller_regs + SABRE_IOMMU_CONTROL;
-	p->iommu.iommu_tsbbase  = p->controller_regs + SABRE_IOMMU_TSBBASE;
-	p->iommu.iommu_flush    = p->controller_regs + SABRE_IOMMU_FLUSH;
-	p->iommu.write_complete_reg = p->controller_regs + SABRE_WRSYNC;
+	iommu->iommu_control  = p->controller_regs + SABRE_IOMMU_CONTROL;
+	iommu->iommu_tsbbase  = p->controller_regs + SABRE_IOMMU_TSBBASE;
+	iommu->iommu_flush    = p->controller_regs + SABRE_IOMMU_FLUSH;
+	iommu->write_complete_reg = p->controller_regs + SABRE_WRSYNC;
 	/* Sabre's IOMMU lacks ctx flushing. */
-	p->iommu.iommu_ctxflush = 0;
+	iommu->iommu_ctxflush = 0;
                                         
 	/* Invalidate TLB Entries. */
 	control = sabre_read(p->controller_regs + SABRE_IOMMU_CONTROL);
@@ -1192,9 +1194,9 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
 		prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");
 		prom_halt();
 	}
-	p->iommu.page_table = (iopte_t *)tsbbase;
-	p->iommu.page_table_map_base = dvma_offset;
-	p->iommu.dma_addr_mask = dma_mask;
+	iommu->page_table = (iopte_t *)tsbbase;
+	iommu->page_table_map_base = dvma_offset;
+	iommu->dma_addr_mask = dma_mask;
 	memset((char *)tsbbase, 0, PAGE_SIZE << order);
 
 	sabre_write(p->controller_regs + SABRE_IOMMU_TSBBASE, __pa(tsbbase));
@@ -1205,11 +1207,11 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
 	switch(tsbsize) {
 	case 64:
 		control |= SABRE_IOMMU_TSBSZ_64K;
-		p->iommu.page_table_sz_bits = 16;
+		iommu->page_table_sz_bits = 16;
 		break;
 	case 128:
 		control |= SABRE_IOMMU_TSBSZ_128K;
-		p->iommu.page_table_sz_bits = 17;
+		iommu->page_table_sz_bits = 17;
 		break;
 	default:
 		prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
@@ -1219,12 +1221,12 @@ static void __init sabre_iommu_init(struct pci_controller_info *p,
 	sabre_write(p->controller_regs + SABRE_IOMMU_CONTROL, control);
 
 	/* We start with no consistent mappings. */
-	p->iommu.lowest_consistent_map =
-		1 << (p->iommu.page_table_sz_bits - PBM_LOGCLUSTERS);
+	iommu->lowest_consistent_map =
+		1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
 
 	for (i = 0; i < PBM_NCLUSTERS; i++) {
-		p->iommu.alloc_info[i].flush = 0;
-		p->iommu.alloc_info[i].next = 0;
+		iommu->alloc_info[i].flush = 0;
+		iommu->alloc_info[i].next = 0;
 	}
 }
 
@@ -1368,6 +1370,7 @@ void __init sabre_init(int pnode)
 {
 	struct linux_prom64_registers pr_regs[2];
 	struct pci_controller_info *p;
+	struct pci_iommu *iommu;
 	unsigned long flags;
 	int tsbsize, err;
 	u32 busrange[2];
@@ -1380,10 +1383,17 @@ void __init sabre_init(int pnode)
 		prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
 		prom_halt();
 	}
+	memset(p, 0, sizeof(*p));
 
-	upa_portid = prom_getintdefault(pnode, "upa-portid", 0xff);
+	iommu = kmalloc(sizeof(*iommu), GFP_ATOMIC);
+	if (!iommu) {
+		prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
+		prom_halt();
+	}
+	memset(iommu, 0, sizeof(*iommu));
+	p->pbm_A.iommu = p->pbm_B.iommu = iommu;
 
-	memset(p, 0, sizeof(*p));
+	upa_portid = prom_getintdefault(pnode, "upa-portid", 0xff);
 
 	spin_lock_irqsave(&pci_controller_lock, flags);
 	p->next = pci_controller_root;
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
new file mode 100644
index 000000000..9299c2531
--- /dev/null
+++ b/arch/sparc64/kernel/pci_schizo.c
@@ -0,0 +1,169 @@
+/* $Id: pci_schizo.c,v 1.2 2001/01/12 02:43:30 davem Exp $
+ * pci_schizo.c: SCHIZO specific PCI controller support.
+ *
+ * Copyright (C) 2001 David S. Miller (davem@redhat.com)
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/malloc.h>
+
+#include <asm/pbm.h>
+#include <asm/iommu.h>
+#include <asm/irq.h>
+
+#include "pci_impl.h"
+
+static int schizo_read_byte(struct pci_dev *dev, int where, u8 *value)
+{
+	/* IMPLEMENT ME */
+}
+
+static int schizo_read_word(struct pci_dev *dev, int where, u16 *value)
+{
+	/* IMPLEMENT ME */
+}
+
+static int schizo_read_dword(struct pci_dev *dev, int where, u32 *value)
+{
+	/* IMPLEMENT ME */
+}
+
+static int schizo_write_byte(struct pci_dev *dev, int where, u8 value)
+{
+	/* IMPLEMENT ME */
+}
+
+static int schizo_write_word(struct pci_dev *dev, int where, u16 value)
+{
+	/* IMPLEMENT ME */
+}
+
+static int schizo_write_dword(struct pci_dev *dev, int where, u32 value)
+{
+	/* IMPLEMENT ME */
+}
+
+static struct pci_ops schizo_ops = {
+	schizo_read_byte,
+	schizo_read_word,
+	schizo_read_dword,
+	schizo_write_byte,
+	schizo_write_word,
+	schizo_write_dword
+};
+
+static void __init schizo_scan_bus(struct pci_controller_info *p)
+{
+	/* IMPLEMENT ME */
+}
+
+static unsigned int __init schizo_irq_build(struct pci_controller_info *p,
+					    struct pci_dev *pdev,
+					    unsigned int ino)
+{
+	/* IMPLEMENT ME */
+}
+
+static void __init schizo_base_address_update(struct pci_dev *pdev, int resource)
+{
+	/* IMPLEMENT ME */
+}
+
+static void __init schizo_resource_adjust(struct pci_dev *pdev,
+					  struct resource *res,
+					  struct resource *root)
+{
+	/* IMPLEMENT ME */
+}
+
+static void schizo_pbm_init(struct pci_controller_info *p,
+			    int prom_node, int is_pbm_a)
+{
+	/* IMPLEMENT ME */
+}
+
+void __init schizo_init(int node)
+{
+	struct linux_prom64_registers pr_regs[3];
+	struct pci_controller_info *p;
+	struct pci_iommu *iommu;
+	u32 portid;
+	int is_pbm_a, err;
+
+	portid = prom_getintdefault(node, "portid", 0xff);
+
+	spin_lock_irqsave(&pci_controller_lock, flags);
+	for(p = pci_controller_root; p; p = p->next) {
+		if (p->portid == portid) {
+			spin_unlock_irqrestore(&pci_controller_lock, flags);
+			is_pbm_a = (p->pbm_A.prom_node == 0);
+			schizo_pbm_init(p, node, is_pbm_a);
+			return;
+		}
+	}
+	spin_unlock_irqrestore(&pci_controller_lock, flags);
+
+	p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
+	if (!p) {
+		prom_printf("SCHIZO: Fatal memory allocation error.\n");
+		prom_halt();
+	}
+	memset(p, 0, sizeof(*p));
+
+	iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
+	if (!iommu) {
+		prom_printf("SCHIZO: Fatal memory allocation error.\n");
+		prom_halt();
+	}
+	memset(iommu, 0, sizeof(*iommu));
+	p->pbm_A.iommu = iommu;
+
+	iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
+	if (!iommu) {
+		prom_printf("SCHIZO: Fatal memory allocation error.\n");
+		prom_halt();
+	}
+	memset(iommu, 0, sizeof(*iommu));
+	p->pbm_B.iommu = iommu;
+
+	spin_lock_irqsave(&pci_controller_lock, flags);
+	p->next = pci_controller_root;
+	pci_controller_root = p;
+	spin_unlock_irqrestore(&pci_controller_lock, flags);
+
+	p->portid = portid;
+	p->index = pci_num_controllers++;
+	p->scan_bus = schizo_scan_bus;
+	p->irq_build = schizo_irq_build;
+	p->base_address_update = schizo_base_address_update;
+	p->resource_adjust = schizo_resource_adjust;
+	p->pci_ops = &schizo_ops;
+
+pbm_init:
+	/* Three OBP regs:
+	 * 1) PBM controller regs
+	 * 2) Schizo front-end controller regs (same for both PBMs)
+	 * 3) Unknown... (0x7ffec000000 and 0x7ffee000000 on Excalibur)
+	 */
+	err = prom_getproperty(node, "reg",
+			       (char *)&pr_regs[0],
+			       sizeof(pr_regs));
+	if (err == 0 || err == -1) {
+		prom_printf("SCHIZO: Fatal error, no reg property.\n");
+		prom_halt();
+	}
+
+	/* XXX Read REG base, record in controller/pbm structures. */
+
+	/* XXX Report controller to console. */
+
+	/* XXX Setup pci_memspace_mask */
+
+	/* XXX Init core controller and IOMMU */
+
+	is_pbm_a = XXX; /* Figure out this test */
+	schizo_pbm_init(p, node, is_pbm_a);
+}
diff --git a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
index c2a7833fb..23d0774b4 100644
--- a/arch/sparc64/kernel/signal.c
+++ b/arch/sparc64/kernel/signal.c
@@ -1,4 +1,4 @@
-/*  $Id: signal.c,v 1.54 2000/09/05 21:44:54 davem Exp $
+/*  $Id: signal.c,v 1.55 2001/01/24 21:05:13 davem Exp $
  *  arch/sparc64/kernel/signal.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
@@ -31,9 +31,6 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
-asmlinkage int sys_wait4(pid_t pid, unsigned long *stat_addr,
-			 int options, unsigned long *ru);
-
 asmlinkage int do_signal(sigset_t *oldset, struct pt_regs * regs,
 			 unsigned long orig_o0, int ret_from_syscall);
 
diff --git a/arch/sparc64/kernel/signal32.c b/arch/sparc64/kernel/signal32.c
index 6d06328dd..0886d9d39 100644
--- a/arch/sparc64/kernel/signal32.c
+++ b/arch/sparc64/kernel/signal32.c
@@ -1,4 +1,4 @@
-/*  $Id: signal32.c,v 1.67 2000/09/05 21:44:54 davem Exp $
+/*  $Id: signal32.c,v 1.68 2001/01/24 21:05:13 davem Exp $
  *  arch/sparc64/kernel/signal32.c
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
@@ -29,9 +29,6 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
-asmlinkage int sys_wait4(pid_t pid, unsigned long *stat_addr,
-			 int options, unsigned long *ru);
-
 asmlinkage int do_signal32(sigset_t *oldset, struct pt_regs *regs,
 			 unsigned long orig_o0, int ret_from_syscall);
 
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 25f6ecff3..76045d0d2 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -290,8 +290,8 @@ void __init smp_boot_cpus(void)
 		}
 		printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
 		       cpucount + 1,
-		       (bogosum + 2500)/500000,
-		       ((bogosum + 2500)/5000)%100);
+		       bogosum/(500000/HZ),
+		       (bogosum/(5000/HZ))%100);
 		smp_activated = 1;
 		smp_num_cpus = cpucount + 1;
 	}
diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
index a0311626e..f35e38a5d 100644
--- a/arch/sparc64/kernel/sparc64_ksyms.c
+++ b/arch/sparc64/kernel/sparc64_ksyms.c
@@ -1,4 +1,4 @@
-/* $Id: sparc64_ksyms.c,v 1.99 2000/12/09 04:15:24 anton Exp $
+/* $Id: sparc64_ksyms.c,v 1.100 2001/01/11 15:07:09 davem Exp $
  * arch/sparc64/kernel/sparc64_ksyms.c: Sparc64 specific ksyms support.
  *
  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
@@ -182,6 +182,7 @@ EXPORT_SYMBOL(__flushw_user);
 EXPORT_SYMBOL(flush_icache_range);
 EXPORT_SYMBOL(__flush_dcache_page);
 
+EXPORT_SYMBOL(mostek_lock);
 EXPORT_SYMBOL(mstk48t02_regs);
 EXPORT_SYMBOL(request_fast_irq);
 #if CONFIG_SBUS
diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c
index 775c986c8..184b4169d 100644
--- a/arch/sparc64/kernel/sys_sparc32.c
+++ b/arch/sparc64/kernel/sys_sparc32.c
@@ -1,4 +1,4 @@
-/* $Id: sys_sparc32.c,v 1.171 2000/12/13 16:34:55 davem Exp $
+/* $Id: sys_sparc32.c,v 1.172 2001/01/24 21:05:13 davem Exp $
  * sys_sparc32.c: Conversion between 32bit and 64bit native syscalls.
  *
  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
@@ -1794,9 +1794,6 @@ static int put_rusage (struct rusage32 *ru, struct rusage *r)
 	return err;
 }
 
-extern asmlinkage int sys_wait4(pid_t pid,unsigned int * stat_addr,
-				int options, struct rusage * ru);
-
 asmlinkage int sys32_wait4(__kernel_pid_t32 pid, unsigned int *stat_addr, int options, struct rusage32 *ru)
 {
 	if (!ru)
diff --git a/arch/sparc64/kernel/sys_sunos32.c b/arch/sparc64/kernel/sys_sunos32.c
index a9d143759..58e4704c4 100644
--- a/arch/sparc64/kernel/sys_sunos32.c
+++ b/arch/sparc64/kernel/sys_sunos32.c
@@ -1,4 +1,4 @@
-/* $Id: sys_sunos32.c,v 1.55 2000/11/18 02:10:59 davem Exp $
+/* $Id: sys_sunos32.c,v 1.56 2001/01/04 05:35:48 davem Exp $
  * sys_sunos32.c: SunOS binary compatability layer on sparc64.
  *
  * Copyright (C) 1995, 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -1047,6 +1047,7 @@ asmlinkage int sunos_msgsys(int op, u32 arg1, u32 arg2, u32 arg3, u32 arg4)
 			(current->thread.kregs->u_regs[UREG_FP] & 0xffffffffUL);
 		if(get_user(arg5, &sp->xxargs[0])) {
 			rval = -EFAULT;
+			kfree(kmbuf);
 			break;
 		}
 		set_fs(KERNEL_DS);
diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
index 0264f9418..a3340f54a 100644
--- a/arch/sparc64/kernel/time.c
+++ b/arch/sparc64/kernel/time.c
@@ -1,4 +1,4 @@
-/* $Id: time.c,v 1.32 2000/09/22 23:02:13 davem Exp $
+/* $Id: time.c,v 1.33 2001/01/11 15:07:09 davem Exp $
  * time.c: UltraSparc timer and TOD clock support.
  *
  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -34,7 +34,9 @@
 
 extern rwlock_t xtime_lock;
 
+spinlock_t mostek_lock = SPIN_LOCK_UNLOCKED;
 unsigned long mstk48t02_regs = 0UL;
+
 static unsigned long mstk48t08_regs = 0UL;
 static unsigned long mstk48t59_regs = 0UL;
 
@@ -187,6 +189,8 @@ static void __init kick_start_clock(void)
 
 	prom_printf("CLOCK: Clock was stopped. Kick start ");
 
+	spin_lock_irq(&mostek_lock);
+
 	/* Turn on the kick start bit to start the oscillator. */
 	tmp = mostek_read(regs + MOSTEK_CREG);
 	tmp |= MSTK_CREG_WRITE;
@@ -201,6 +205,8 @@ static void __init kick_start_clock(void)
 	tmp &= ~MSTK_CREG_WRITE;
 	mostek_write(regs + MOSTEK_CREG, tmp);
 
+	spin_unlock_irq(&mostek_lock);
+
 	/* Delay to allow the clock oscillator to start. */
 	sec = MSTK_REG_SEC(regs);
 	for (i = 0; i < 3; i++) {
@@ -212,6 +218,8 @@ static void __init kick_start_clock(void)
 	}
 	prom_printf("\n");
 
+	spin_lock_irq(&mostek_lock);
+
 	/* Turn off kick start and set a "valid" time and date. */
 	tmp = mostek_read(regs + MOSTEK_CREG);
 	tmp |= MSTK_CREG_WRITE;
@@ -230,9 +238,14 @@ static void __init kick_start_clock(void)
 	tmp &= ~MSTK_CREG_WRITE;
 	mostek_write(regs + MOSTEK_CREG, tmp);
 
+	spin_unlock_irq(&mostek_lock);
+
 	/* Ensure the kick start bit is off. If it isn't, turn it off. */
 	while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
 		prom_printf("CLOCK: Kick start still on!\n");
+
+		spin_lock_irq(&mostek_lock);
+
 		tmp = mostek_read(regs + MOSTEK_CREG);
 		tmp |= MSTK_CREG_WRITE;
 		mostek_write(regs + MOSTEK_CREG, tmp);
@@ -244,6 +257,8 @@ static void __init kick_start_clock(void)
 		tmp = mostek_read(regs + MOSTEK_CREG);
 		tmp &= ~MSTK_CREG_WRITE;
 		mostek_write(regs + MOSTEK_CREG, tmp);
+
+		spin_unlock_irq(&mostek_lock);
 	}
 
 	prom_printf("CLOCK: Kick start procedure successful.\n");
@@ -255,11 +270,15 @@ static int __init has_low_battery(void)
 	unsigned long regs = mstk48t02_regs;
 	u8 data1, data2;
 
+	spin_lock_irq(&mostek_lock);
+
 	data1 = mostek_read(regs + MOSTEK_EEPROM);	/* Read some data. */
 	mostek_write(regs + MOSTEK_EEPROM, ~data1);	/* Write back the complement. */
 	data2 = mostek_read(regs + MOSTEK_EEPROM);	/* Read back the complement. */
 	mostek_write(regs + MOSTEK_EEPROM, data1);	/* Restore original value. */
 
+	spin_unlock_irq(&mostek_lock);
+
 	return (data1 == data2);	/* Was the write blocked? */
 }
 
@@ -278,6 +297,8 @@ static void __init set_system_time(void)
 		prom_halt();
 	}		
 
+	spin_lock_irq(&mostek_lock);
+
 	tmp = mostek_read(mregs + MOSTEK_CREG);
 	tmp |= MSTK_CREG_READ;
 	mostek_write(mregs + MOSTEK_CREG, tmp);
@@ -294,6 +315,8 @@ static void __init set_system_time(void)
 	tmp = mostek_read(mregs + MOSTEK_CREG);
 	tmp &= ~MSTK_CREG_READ;
 	mostek_write(mregs + MOSTEK_CREG, tmp);
+
+	spin_unlock_irq(&mostek_lock);
 }
 
 void __init clock_probe(void)
@@ -512,6 +535,7 @@ static int set_rtc_mmss(unsigned long nowtime)
 {
 	int real_seconds, real_minutes, mostek_minutes;
 	unsigned long regs = mstk48t02_regs;
+	unsigned long flags;
 	u8 tmp;
 
 	/* 
@@ -521,6 +545,8 @@ static int set_rtc_mmss(unsigned long nowtime)
 	if (!regs) 
 		return -1;
 
+	spin_lock_irqsave(&mostek_lock, flags);
+
 	/* Read the current RTC minutes. */
 	tmp = mostek_read(regs + MOSTEK_CREG);
 	tmp |= MSTK_CREG_READ;
@@ -555,8 +581,13 @@ static int set_rtc_mmss(unsigned long nowtime)
 		tmp = mostek_read(regs + MOSTEK_CREG);
 		tmp &= ~MSTK_CREG_WRITE;
 		mostek_write(regs + MOSTEK_CREG, tmp);
-	} else
-		return -1;
 
-	return 0;
+		spin_unlock_irqrestore(&mostek_lock, flags);
+
+		return 0;
+	} else {
+		spin_unlock_irqrestore(&mostek_lock, flags);
+
+		return -1;
+	}
 }