Merge with 2.3.19.

9 files changed, 120 insertions, 95 deletions

diff --git a/arch/sparc64/lib/PeeCeeI.c b/arch/sparc64/lib/PeeCeeI.c
index 6677f581a..56c005dfe 100644
--- a/arch/sparc64/lib/PeeCeeI.c
+++ b/arch/sparc64/lib/PeeCeeI.c
@@ -1,4 +1,4 @@
-/* $Id: PeeCeeI.c,v 1.3 1997/08/28 23:59:52 davem Exp $
+/* $Id: PeeCeeI.c,v 1.4 1999/09/06 01:17:35 davem Exp $
  * PeeCeeI.c: The emerging standard...
  *
  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
@@ -9,6 +9,7 @@
 #ifdef CONFIG_PCI
 
 #include <asm/io.h>
+#include <asm/byteorder.h>
 
 void outsb(unsigned long addr, const void *src, unsigned long count)
 {
@@ -21,25 +22,29 @@ void outsb(unsigned long addr, const void *src, unsigned long count)
 void outsw(unsigned long addr, const void *src, unsigned long count)
 {
 	if(count) {
-		const u16 *ps = src;
-		const u32 *pi;
+		u16 *ps = (u16 *)src;
+		u32 *pi;
 
 		if(((u64)src) & 0x2) {
-			outw(*ps++, addr);
+			u16 val = le16_to_cpup(ps);
+			outw(val, addr);
+			ps++;
 			count--;
 		}
-		pi = (const u32 *)ps;
+		pi = (u32 *)ps;
 		while(count >= 2) {
-			u32 w;
+			u32 w = le32_to_cpup(pi);
 
-			w = *pi++;
+			pi++;
+			outw(w >> 0, addr);
 			outw(w >> 16, addr);
-			outw(w, addr);
 			count -= 2;
 		}
-		ps = (const u16 *)pi;
-		if(count)
-			outw(*ps, addr);
+		ps = (u16 *)pi;
+		if(count) {
+			u16 val = le16_to_cpup(ps);
+			outw(val, addr);
+		}
 	}
 }
 
@@ -47,60 +52,71 @@ void outsl(unsigned long addr, const void *src, unsigned long count)
 {
 	if(count) {
 		if((((u64)src) & 0x3) == 0) {
-			const u32 *p = src;
-			while(count--)
-				outl(*p++, addr);
+			u32 *p = (u32 *)src;
+			while(count--) {
+				u32 val = cpu_to_le32p(p);
+				outl(val, addr);
+				p++;
+			}
 		} else {
-			const u8 *pb;
-			const u16 *ps = src;
+			u8 *pb;
+			u16 *ps = (u16 *)src;
 			u32 l = 0, l2;
-			const u32 *pi;
+			u32 *pi;
 
 			switch(((u64)src) & 0x3) {
 			case 0x2:
 				count -= 1;
-				l = *ps++;
-				pi = (const u32 *)ps;
+				l = cpu_to_le16p(ps) << 16;
+				ps++;
+				pi = (u32 *)ps;
 				while(count--) {
-					l2 = *pi++;
-					outl(((l <<16) | (l2 >> 16)), addr);
+					l2 = cpu_to_le32p(pi);
+					pi++;
+					outl(((l >> 16) | (l2 << 16)), addr);
 					l = l2;
 				}
-				ps = (const u16 *)pi;
-				outl(((l << 16) | (*ps >> 16)), addr);
+				ps = (u16 *)pi;
+				l2 = cpu_to_le16p(ps);
+				outl(((l >> 16) | (l2 << 16)), addr);
 				break;
 
 			case 0x1:
 				count -= 1;
-				pb = src;
-				l = (*pb++ << 16);
-				ps = (const u16 *)pb;
-				l |= *ps++;
-				pi = (const u32 *)ps;
+				pb = (u8 *)src;
+				l = (*pb++ << 8);
+				ps = (u16 *)pb;
+				l2 = cpu_to_le16p(ps);
+				ps++;
+				l |= (l2 << 16);
+				pi = (u32 *)ps;
 				while(count--) {
-					l2 = *pi++;
-					outl(((l << 8) | (l2 >> 24)), addr);
+					l2 = cpu_to_le32p(pi);
+					pi++;
+					outl(((l >> 8) | (l2 << 24)), addr);
 					l = l2;
 				}
-				pb = (const u8 *)pi;
-				outl(((l << 8) | (*pb >> 24)), addr);
+				pb = (u8 *)pi;
+				outl(((l >> 8) | (*pb << 24)), addr);
 				break;
 
 			case 0x3:
 				count -= 1;
-				pb = src;
-				l = (*pb++ >> 24);
-				pi = (const u32 *)pb;
+				pb = (u8 *)src;
+				l = (*pb++ << 24);
+				pi = (u32 *)pb;
 				while(count--) {
-					l2 = *pi++;
-					outl(((l << 24) | (l2 >> 8)), addr);
+					l2 = cpu_to_le32p(pi);
+					pi++;
+					outl(((l >> 24) | (l2 << 8)), addr);
 					l = l2;
 				}
-				ps = (const u16 *)pi;
-				l2 = (*ps++ << 16);
-				pb = (const u8 *)ps;
-				l2 |= (*pb << 8);
-				outl(((l << 24) | (l2 >> 8)), addr);
+				ps = (u16 *)pi;
+				l2 = cpu_to_le16p(ps);
+				ps++;
+				pb = (u8 *)ps;
+				l2 |= (*pb << 16);
+				outl(((l >> 24) | (l2 << 8)), addr);
 				break;
 			}
 		}
@@ -122,7 +138,7 @@ void insb(unsigned long addr, void *dst, unsigned long count)
 			w  = (inb(addr) << 24);
 			w |= (inb(addr) << 16);
 			w |= (inb(addr) << 8);
-			w |= inb(addr);
+			w |= (inb(addr) << 0);
 			*pi++ = w;
 			count -= 4;
 		}
@@ -139,21 +155,21 @@ void insw(unsigned long addr, void *dst, unsigned long count)
 		u32 *pi;
 
 		if(((unsigned long)ps) & 0x2) {
-			*ps++ = inw(addr);
+			*ps++ = le16_to_cpu(inw(addr));
 			count--;
 		}
 		pi = (u32 *)ps;
 		while(count >= 2) {
 			u32 w;
 
-			w  = (inw(addr) << 16);
-			w |= inw(addr);
+			w  = (le16_to_cpu(inw(addr)) << 16);
+			w |= (le16_to_cpu(inw(addr)) << 0);
 			*pi++ = w;
 			count -= 2;
 		}
 		ps = (u16 *)pi;
 		if(count)
-			*ps = inw(addr);
+			*ps = le16_to_cpu(inw(addr));
 	}
 }
 
@@ -163,7 +179,7 @@ void insl(unsigned long addr, void *dst, unsigned long count)
 		if((((unsigned long)dst) & 0x3) == 0) {
 			u32 *pi = dst;
 			while(count--)
-				*pi++ = inl(addr);
+				*pi++ = le32_to_cpu(inl(addr));
 		} else {
 			u32 l = 0, l2, *pi;
 			u16 *ps;
@@ -173,47 +189,48 @@ void insl(unsigned long addr, void *dst, unsigned long count)
 			case 0x2:
 				ps = dst;
 				count -= 1;
-				l = inl(addr);
-				*ps++ = (l >> 16);
+				l = le32_to_cpu(inl(addr));
+				*ps++ = l;
 				pi = (u32 *)ps;
 				while(count--) {
-					l2 = inl(addr);
+					l2 = le32_to_cpu(inl(addr));
 					*pi++ = (l << 16) | (l2 >> 16);
 					l = l2;
 				}
 				ps = (u16 *)pi;
-				*ps = (l << 16);
+				*ps = l;
 				break;
 
 			case 0x1:
 				pb = dst;
 				count -= 1;
-				*pb++ = (l >> 24);
+				l = le32_to_cpu(inl(addr));
+				*pb++ = l >> 24;
 				ps = (u16 *)pb;
-				*ps++ = (l >> 8);
+				*ps++ = ((l >> 8) & 0xffff);
 				pi = (u32 *)ps;
 				while(count--) {
-					l2 = inl(addr);
-					*pi++ = ((l << 24) | (l2 >> 8));
+					l2 = le32_to_cpu(inl(addr));
+					*pi++ = (l << 24) | (l2 >> 8);
 					l = l2;
 				}
 				pb = (u8 *)pi;
-				*pb = (l >> 8);
+				*pb = l;
 				break;
 
 			case 0x3:
 				pb = (u8 *)dst;
 				count -= 1;
-				l = inl(addr);
+				l = le32_to_cpu(inl(addr));
 				*pb++ = l >> 24;
 				pi = (u32 *)pb;
 				while(count--) {
-					l2 = inl(addr);
-					*pi++ = ((l >> 24) | (l2 << 8));
+					l2 = le32_to_cpu(inl(addr));
+					*pi++ = (l << 8) | (l2 >> 24);
 					l = l2;
 				}
 				ps = (u16 *)pi;
-				*ps++ = l >> 8;
+				*ps++ = ((l >> 8) & 0xffff);
 				pb = (u8 *)ps;
 				*pb = l;
 				break;
diff --git a/arch/sparc64/lib/VIScopy.S b/arch/sparc64/lib/VIScopy.S
index bb1d81acd..57cf6b0f1 100644
--- a/arch/sparc64/lib/VIScopy.S
+++ b/arch/sparc64/lib/VIScopy.S
@@ -1,4 +1,4 @@
-/* $Id: VIScopy.S,v 1.20 1999/05/25 16:52:57 jj Exp $
+/* $Id: VIScopy.S,v 1.21 1999/07/30 09:35:35 davem Exp $
  * VIScopy.S: High speed copy operations utilizing the UltraSparc
  *            Visual Instruction Set.
  *
@@ -29,19 +29,19 @@
 #include <asm/asm_offsets.h>
 
 #define FPU_CLEAN_RETL								\
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %o1;	\
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %o1;	\
 	VISExit									\
 	clr		%o0;							\
 	retl;									\
 	 wr		%o1, %g0, %asi;
 #define FPU_RETL								\
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %o1;	\
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %o1;	\
 	VISExit									\
 	clr		%o0;							\
 	retl;									\
 	 wr		%o1, %g0, %asi;
 #define NORMAL_RETL								\
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %o1;	\
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %o1;	\
 	clr		%o0;							\
 	retl;									\
 	 wr		%o1, %g0, %asi;
@@ -1009,7 +1009,7 @@ VIScopyfixup_ret:
 		/* If this is copy_from_user(), zero out the rest of the
 		 * kernel buffer.
 		 */
-		ldub		[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %o4
+		ldub		[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %o4
 		andcc		asi_src, 0x1, %g0
 		be,pt		%icc, 1f
 		 VISExit
diff --git a/arch/sparc64/lib/VIScsum.S b/arch/sparc64/lib/VIScsum.S
index 0326ff057..aad5d941a 100644
--- a/arch/sparc64/lib/VIScsum.S
+++ b/arch/sparc64/lib/VIScsum.S
@@ -1,4 +1,4 @@
-/* $Id: VIScsum.S,v 1.4 1999/05/25 16:53:00 jj Exp $
+/* $Id: VIScsum.S,v 1.5 1999/07/30 09:35:36 davem Exp $
  * VIScsum.S: High bandwidth IP checksumming utilizing the UltraSparc
  *            Visual Instruction Set.
  *
@@ -341,7 +341,7 @@ csum_partial:
 	DO_THE_TRICK(f44,f46,f48,f50,f52,f54,f56,f58,f60,f62,f0,f2,f4,f6,f8,f10,f12,f14)
 	END_THE_TRICK(f60,f62,f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30)
 #ifdef __KERNEL__
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %g7
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %g7
 #endif
 	and		%o1, 0x3f, %o1		/*  IEU0	Group			*/
 #ifdef __KERNEL__
diff --git a/arch/sparc64/lib/VISsave.S b/arch/sparc64/lib/VISsave.S
index a189d0db6..2254ba5c5 100644
--- a/arch/sparc64/lib/VISsave.S
+++ b/arch/sparc64/lib/VISsave.S
@@ -1,4 +1,4 @@
-/* $Id: VISsave.S,v 1.3 1998/10/21 10:36:39 jj Exp $
+/* $Id: VISsave.S,v 1.4 1999/07/30 09:35:37 davem Exp $
  * VISsave.S: Code for saving FPU register state for
  *            VIS routines. One should not call this directly,
  *            but use macros provided in <asm/visasm.h>.
@@ -19,35 +19,35 @@
 
 	.align		32
 VISenter:
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpdepth], %g1
 	brnz,a,pn	%g1, 1f
 	 cmp		%g1, 1
-	stb		%g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+	stb		%g0, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 9:	jmpl		%g7 + %g0, %g0
 	 nop
 1:	bne,pn		%icc, 2f
 
 	 srl		%g1, 1, %g1
-vis1:	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpsaved], %g3
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+vis1:	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpsaved], %g3
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 	or		%g3, %o5, %g3
-	stb		%g3, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%g3, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
 	rd		%gsr, %g3
 	clr		%g1
 	ba,pt		%xcc, 3f
 
-	 stb		%g3, [%g6 + AOFF_task_tss + AOFF_thread_gsr]
+	 stb		%g3, [%g6 + AOFF_task_thread + AOFF_thread_gsr]
 2:	add		%g6, %g1, %g3
 	cmp		%o5, FPRS_DU
 	be,pn		%icc, 6f
 	 sll		%g1, 3, %g1
-	stb		%o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%o5, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 	rd		%gsr, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_gsr]
 
 	add		%g6, %g1, %g2
-	stx		%fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr]
+	stx		%fsr, [%g2 + AOFF_task_thread + AOFF_thread_xfsr]
 	sll		%g1, 5, %g1
 3:	andcc		%o5, FPRS_DL|FPRS_DU, %g0
 	be,pn		%icc, 9b
@@ -69,10 +69,10 @@ vis1:	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpsaved], %g3
 	jmpl		%g7 + %g0, %g0
 	 nop
 
-6:	ldub		[%g3 + AOFF_task_tss + AOFF_thread_fpsaved], %o5
+6:	ldub		[%g3 + AOFF_task_thread + AOFF_thread_fpsaved], %o5
 	or		%o5, FPRS_DU, %o5
 	add		%g6, AOFF_task_fpregs+0x80, %g2
-	stb		%o5, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%o5, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 
 	sll		%g1, 5, %g1
 	add		%g6, AOFF_task_fpregs+0xc0, %g3
@@ -87,11 +87,11 @@ vis1:	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpsaved], %g3
 
 	.align		32
 VISenterhalf:
-	ldub		[%g6 + AOFF_task_tss + AOFF_thread_fpdepth], %g1
+	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fpdepth], %g1
 	brnz,a,pn	%g1, 1f
 	 cmp		%g1, 1
-	stb		%g0, [%g6 + AOFF_task_tss + AOFF_thread_fpsaved]
-	stx		%fsr, [%g6 + AOFF_task_tss + AOFF_thread_xfsr]
+	stb		%g0, [%g6 + AOFF_task_thread + AOFF_thread_fpsaved]
+	stx		%fsr, [%g6 + AOFF_task_thread + AOFF_thread_xfsr]
 	clr		%o5
 	jmpl		%g7 + %g0, %g0
 	 wr		%g0, FPRS_FEF, %fprs
@@ -103,12 +103,12 @@ VISenterhalf:
 2:	addcc		%g6, %g1, %g3
 	sll		%g1, 3, %g1
 	andn		%o5, FPRS_DU, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_fpsaved]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_fpsaved]
 
 	rd		%gsr, %g2
-	stb		%g2, [%g3 + AOFF_task_tss + AOFF_thread_gsr]
+	stb		%g2, [%g3 + AOFF_task_thread + AOFF_thread_gsr]
 	add		%g6, %g1, %g2
-	stx		%fsr, [%g2 + AOFF_task_tss + AOFF_thread_xfsr]
+	stx		%fsr, [%g2 + AOFF_task_thread + AOFF_thread_xfsr]
 	sll		%g1, 5, %g1
 3:	andcc		%o5, FPRS_DL, %g0
 	be,pn		%icc, 4f
diff --git a/arch/sparc64/lib/atomic.S b/arch/sparc64/lib/atomic.S
index 3c0dce16a..cac9d15dd 100644
--- a/arch/sparc64/lib/atomic.S
+++ b/arch/sparc64/lib/atomic.S
@@ -1,4 +1,4 @@
-/* $Id: atomic.S,v 1.1 1999/07/03 22:11:04 davem Exp $
+/* $Id: atomic.S,v 1.2 1999/08/23 05:15:58 davem Exp $
  * atomic.S: These things are too big to do inline.
  *
  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
@@ -9,7 +9,10 @@
 	.text
 	.align	64
 
+	.globl	atomic_impl_begin, atomic_impl_end
+
 	.globl	__atomic_add
+atomic_impl_begin:
 __atomic_add:
 	lduw	[%g1], %g5
 	add	%g5, %g2, %g7
@@ -30,3 +33,4 @@ __atomic_sub:
 	 nop
 	jmpl	%g3 + 8, %g0
 	 sub	%g7, %g2, %g2
+atomic_impl_end:
diff --git a/arch/sparc64/lib/blockops.S b/arch/sparc64/lib/blockops.S
index 840839c95..202b57270 100644
--- a/arch/sparc64/lib/blockops.S
+++ b/arch/sparc64/lib/blockops.S
@@ -1,4 +1,4 @@
-/* $Id: blockops.S,v 1.17 1999/05/25 16:52:52 jj Exp $
+/* $Id: blockops.S,v 1.18 1999/07/30 09:35:37 davem Exp $
  * blockops.S: UltraSparc block zero optimized routines.
  *
  * Copyright (C) 1996,1998 David S. Miller (davem@caip.rutgers.edu)
@@ -29,7 +29,7 @@
 	.type		copy_page,@function
 copy_page: /* %o0=dest, %o1=src */
 	VISEntry
-	ldx		[%g6 + AOFF_task_mm], %o2
+	ldx		[%g6 + AOFF_task_active_mm], %o2
 	sub		%o0, %g4, %g1
 	sethi		%uhi(_PAGE_VALID), %g3
 	sub		%o1, %g4, %g2
@@ -107,7 +107,7 @@ copy_page: /* %o0=dest, %o1=src */
 	.type		clear_page,@function
 clear_page:		/* %o0=dest */
 	VISEntryHalf
-	ldx		[%g6 + AOFF_task_mm], %o2
+	ldx		[%g6 + AOFF_task_active_mm], %o2
 	sub		%o0, %g4, %g1
 	sethi		%uhi(_PAGE_VALID), %g3
 	sllx		%g3, 32, %g3
diff --git a/arch/sparc64/lib/checksum.S b/arch/sparc64/lib/checksum.S
index d720bb55e..07d10ba42 100644
--- a/arch/sparc64/lib/checksum.S
+++ b/arch/sparc64/lib/checksum.S
@@ -266,7 +266,7 @@ cpc_end:
 	.globl	cpc_handler
 cpc_handler:
 	ldx	[%sp + 0x7ff + 128], %g1
-	ldub	[%g6 + AOFF_task_tss + AOFF_thread_current_ds], %g3
+	ldub	[%g6 + AOFF_task_thread + AOFF_thread_current_ds], %g3
 	sub	%g0, EFAULT, %g2
 	brnz,a,pt %g1, 1f
 	 st	%g2, [%g1]
diff --git a/arch/sparc64/lib/debuglocks.c b/arch/sparc64/lib/debuglocks.c
index 69286c4b7..315724ec3 100644
--- a/arch/sparc64/lib/debuglocks.c
+++ b/arch/sparc64/lib/debuglocks.c
@@ -1,4 +1,4 @@
-/* $Id: debuglocks.c,v 1.2 1998/10/13 09:07:27 davem Exp $
+/* $Id: debuglocks.c,v 1.3 1999/09/10 10:40:50 davem Exp $
  * debuglocks.c: Debugging versions of SMP locking primitives.
  *
  * Copyright (C) 1998 David S. Miller (davem@dm.cobaltmicro.com)
@@ -6,8 +6,8 @@
 
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/spinlock.h>
 #include <asm/system.h>
-#include <asm/spinlock.h>
 
 #ifdef __SMP__
 
diff --git a/arch/sparc64/lib/rwlock.S b/arch/sparc64/lib/rwlock.S
index cee94eef0..74360bf68 100644
--- a/arch/sparc64/lib/rwlock.S
+++ b/arch/sparc64/lib/rwlock.S
@@ -1,4 +1,4 @@
-/* $Id: rwlock.S,v 1.1 1999/07/03 22:11:06 davem Exp $
+/* $Id: rwlock.S,v 1.2 1999/08/23 05:15:58 davem Exp $
  * rwlocks.S: These things are too big to do inline.
  *
  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
@@ -7,10 +7,13 @@
 	.text
 	.align	64
 
+	.globl	rwlock_impl_begin, rwlock_impl_end
+
 	/* The non-contention read lock usage is 2 cache lines. */
 
 	.globl	__read_lock, __read_unlock
 	/* g1=lock, g3=retpc, g5/g7=scratch */
+rwlock_impl_begin:
 __read_lock:
 	ldsw		[%g1], %g5
 	brlz,pn		%g5, __read_wait_for_writer
@@ -78,4 +81,5 @@ __write_lock:
 	be,pn		%icc, 99b
 	 membar		#LoadLoad
 	b,a,pt		%xcc, 99b
+rwlock_impl_end: