Clear the TS bit from the master's status register (don't know why

PROM is getting the bit set before entry into kernel).
Fix per cpu frequency reporting.
Fix bug so that we do not clear information about mips4 availability.
Have the slaves flush their cache/tlb and set status based on what
the master processor did.

4 files changed, 22 insertions, 6 deletions

diff --git a/arch/mips64/kernel/head.S b/arch/mips64/kernel/head.S
index 79f409c1b..8b43bb074 100644
--- a/arch/mips64/kernel/head.S
+++ b/arch/mips64/kernel/head.S
@@ -50,7 +50,12 @@ NESTED(kernel_entry, 16, sp)			# kernel entry point
 	CLI					# disable interrupts
 
 	mfc0	t0, CP0_STATUS
-	li	t1, ~(ST0_CU1|ST0_CU2|ST0_CU3)
+	/*
+	 * On IP27, I am seeing the TS bit set when the
+	 * kernel is loaded. Maybe because the kernel is
+	 * in ckseg0 and not xkphys? Clear it anyway ...
+	 */
+	li	t1, ~(ST0_TS|ST0_CU1|ST0_CU2|ST0_CU3)
 	and	t0, t1
 	or	t0, (ST0_CU0|ST0_KX|ST0_SX|ST0_FR) # Bogosity: cu0 indicates kernel
 	mtc0	t0, CP0_STATUS			   # thread in copy_thread.
diff --git a/arch/mips64/kernel/traps.c b/arch/mips64/kernel/traps.c
index 5fe51a31c..0b41f7b9d 100644
--- a/arch/mips64/kernel/traps.c
+++ b/arch/mips64/kernel/traps.c
@@ -446,7 +446,6 @@ static inline void mips4_setup(void)
 		mips4_available = 1;
 		set_cp0_status(ST0_XX, ST0_XX);
 	}
-	mips4_available = 0;
 }
 
 static inline void go_64(void)
diff --git a/arch/mips64/sgi-ip27/ip27-init.c b/arch/mips64/sgi-ip27/ip27-init.c
index fea427a16..40e8fd6be 100644
--- a/arch/mips64/sgi-ip27/ip27-init.c
+++ b/arch/mips64/sgi-ip27/ip27-init.c
@@ -2,6 +2,9 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/mmzone.h>	/* for numnodes */
+#include <linux/mm.h>
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sn0/addrs.h>
 #include <asm/sn/sn0/hubni.h>
@@ -311,6 +314,8 @@ cpuid_t getcpuid(void)
 
 void per_cpu_init(void)
 {
+	static int is_slave = 0;
+
 #if 0
 	cpuid_t cpu = getcpuid();
 #endif
@@ -322,10 +327,18 @@ void per_cpu_init(void)
 	set_cp0_status(ST0_IM, 0);
 	cpu_time_init();
 	per_hub_init(cnode);
+	if (is_slave) {
+		set_cp0_status(ST0_BEV, 0);
+		if (mips4_available)
+			set_cp0_status(ST0_XX, ST0_XX);
+		set_cp0_status(ST0_KX|ST0_SX|ST0_UX, ST0_KX|ST0_SX|ST0_UX);
+	}
 #if 0
 	install_cpuintr(cpu);
 	install_tlbintr(cpu);
 #endif
+	if (is_slave == 0)
+		is_slave = 1;
 }
 
 cnodeid_t get_compact_nodeid(void)
@@ -370,9 +383,9 @@ void cboot(void)
 	ecc_init();
 	bte_lateinit();
 	init_mfhi_war();
-	flush_tlb();
-	flush_cache();
 #endif
+	flush_tlb_all();
+	flush_cache_all();
 	start_secondary();
 }
 
diff --git a/arch/mips64/sgi-ip27/ip27-timer.c b/arch/mips64/sgi-ip27/ip27-timer.c
index 0a98885a5..f4cda8c99 100644
--- a/arch/mips64/sgi-ip27/ip27-timer.c
+++ b/arch/mips64/sgi-ip27/ip27-timer.c
@@ -271,8 +271,7 @@ void __init cpu_time_init(void)
 	if (!cpu)
 		panic("No information about myself?");
 
-	printk("CPU %d clock is %dMHz.\n", cpu->cpu_speed, smp_processor_id());
-	printk("CPU clock is %dMHz.\n", cpu->cpu_speed);
+	printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed);
 
 	set_cp0_status(SRB_TIMOCLK, SRB_TIMOCLK);
 }