diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2001-03-09 20:33:35 +0000 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2001-03-09 20:33:35 +0000 |
commit | 116674acc97ba75a720329996877077d988443a2 (patch) | |
tree | 6a3f2ff0b612ae2ee8a3f3509370c9e6333a53b3 /drivers/video | |
parent | 71118c319fcae4a138f16e35b4f7e0a6d53ce2ca (diff) |
Merge with Linux 2.4.2.
Diffstat (limited to 'drivers/video')
65 files changed, 3786 insertions, 1693 deletions
diff --git a/drivers/video/S3triofb.c b/drivers/video/S3triofb.c index e8c0c97da..9115ce37d 100644 --- a/drivers/video/S3triofb.c +++ b/drivers/video/S3triofb.c @@ -30,7 +30,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index 5289a4a83..bba3a3ce5 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c @@ -23,7 +23,7 @@ #include <linux/ctype.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/init.h> #include <linux/fb.h> diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c index 8a1e7f01e..fcdf286c8 100644 --- a/drivers/video/amifb.c +++ b/drivers/video/amifb.c @@ -46,7 +46,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/config.h> #include <linux/interrupt.h> @@ -1534,7 +1534,7 @@ static int amifb_ioctl(struct inode *inode, struct file *file, } return i; } -#endif */ DEBUG */ +#endif /* DEBUG */ } return -EINVAL; } diff --git a/drivers/video/atafb.c b/drivers/video/atafb.c index e305027a7..62a1461c2 100644 --- a/drivers/video/atafb.c +++ b/drivers/video/atafb.c @@ -54,7 +54,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/init.h> diff --git a/drivers/video/aty128fb.c b/drivers/video/aty128fb.c index 626bf3cad..93913b3b2 100644 --- a/drivers/video/aty128fb.c +++ b/drivers/video/aty128fb.c @@ -33,7 +33,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/atyfb.c b/drivers/video/atyfb.c index 3c0b9408f..833926b7b 100644 --- a/drivers/video/atyfb.c +++ b/drivers/video/atyfb.c @@ -45,7 +45,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/bwtwofb.c b/drivers/video/bwtwofb.c index ebb5d5e56..8c0cda173 100644 --- a/drivers/video/bwtwofb.c +++ b/drivers/video/bwtwofb.c @@ -1,4 +1,4 @@ -/* $Id: bwtwofb.c,v 1.13 2000/02/14 02:50:25 davem Exp $ +/* $Id: bwtwofb.c,v 1.14 2001/02/13 01:17:14 davem Exp $ * bwtwofb.c: BWtwo frame buffer driver * * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) @@ -15,7 +15,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/cgfourteenfb.c b/drivers/video/cgfourteenfb.c index 05a578bfd..14bad795e 100644 --- a/drivers/video/cgfourteenfb.c +++ b/drivers/video/cgfourteenfb.c @@ -1,4 +1,4 @@ -/* $Id: cgfourteenfb.c,v 1.8 2000/08/29 07:01:56 davem Exp $ +/* $Id: cgfourteenfb.c,v 1.9 2001/02/13 01:17:14 davem Exp $ * cgfourteenfb.c: CGfourteen frame buffer driver * * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) @@ -12,7 +12,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/cgsixfb.c b/drivers/video/cgsixfb.c index b569589d0..2d6954f58 100644 --- a/drivers/video/cgsixfb.c +++ b/drivers/video/cgsixfb.c @@ -1,4 +1,4 @@ -/* $Id: cgsixfb.c,v 1.23 2000/07/26 23:02:51 davem Exp $ +/* $Id: cgsixfb.c,v 1.24 2001/02/13 01:17:14 davem Exp $ * cgsixfb.c: CGsix (GX,GXplus) frame buffer driver * * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) @@ -13,7 +13,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/cgthreefb.c b/drivers/video/cgthreefb.c index 9cec20abf..c0e17cdad 100644 --- a/drivers/video/cgthreefb.c +++ b/drivers/video/cgthreefb.c @@ -1,4 +1,4 @@ -/* $Id: cgthreefb.c,v 1.9 2000/03/19 04:20:44 anton Exp $ +/* $Id: cgthreefb.c,v 1.10 2001/02/13 01:17:14 davem Exp $ * cgthreefb.c: CGthree frame buffer driver * * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) @@ -13,7 +13,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/chipsfb.c b/drivers/video/chipsfb.c index 9a3908c4b..c0bee62d4 100644 --- a/drivers/video/chipsfb.c +++ b/drivers/video/chipsfb.c @@ -21,7 +21,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/clgenfb.c b/drivers/video/clgenfb.c index 32a26c2d7..ecad3bbbe 100644 --- a/drivers/video/clgenfb.c +++ b/drivers/video/clgenfb.c @@ -40,7 +40,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> diff --git a/drivers/video/controlfb.c b/drivers/video/controlfb.c index fe64ab9a1..58ccd3e13 100644 --- a/drivers/video/controlfb.c +++ b/drivers/video/controlfb.c @@ -31,7 +31,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/creatorfb.c b/drivers/video/creatorfb.c index 22349c380..90689e4f2 100644 --- a/drivers/video/creatorfb.c +++ b/drivers/video/creatorfb.c @@ -1,4 +1,4 @@ -/* $Id: creatorfb.c,v 1.32 2000/07/26 23:02:51 davem Exp $ +/* $Id: creatorfb.c,v 1.33 2001/02/13 01:17:14 davem Exp $ * creatorfb.c: Creator/Creator3D frame buffer driver * * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz) @@ -11,7 +11,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index 5cb924fc8..d8c524e76 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c @@ -31,7 +31,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/pci.h> diff --git a/drivers/video/cyberfb.c b/drivers/video/cyberfb.c index 4510d1165..75f457092 100644 --- a/drivers/video/cyberfb.c +++ b/drivers/video/cyberfb.c @@ -82,7 +82,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/zorro.h> #include <linux/fb.h> diff --git a/drivers/video/dn_cfb4.c b/drivers/video/dn_cfb4.c index 205703be4..3f30e9d97 100644 --- a/drivers/video/dn_cfb4.c +++ b/drivers/video/dn_cfb4.c @@ -3,7 +3,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <asm/setup.h> diff --git a/drivers/video/dn_cfb8.c b/drivers/video/dn_cfb8.c index a654717b3..d200972a7 100644 --- a/drivers/video/dn_cfb8.c +++ b/drivers/video/dn_cfb8.c @@ -3,7 +3,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <asm/setup.h> diff --git a/drivers/video/dnfb.c b/drivers/video/dnfb.c index f7a5ffba3..7bc2f92b2 100644 --- a/drivers/video/dnfb.c +++ b/drivers/video/dnfb.c @@ -3,7 +3,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <asm/setup.h> diff --git a/drivers/video/fbcon.c b/drivers/video/fbcon.c index 32935dfc3..15230bb3b 100644 --- a/drivers/video/fbcon.c +++ b/drivers/video/fbcon.c @@ -67,7 +67,7 @@ #include <linux/console.h> #include <linux/string.h> #include <linux/kd.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/fb.h> #include <linux/vt_kern.h> #include <linux/selection.h> diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index a951ccf5e..ce0f0aae1 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -17,7 +17,7 @@ #include <linux/smp_lock.h> #include <linux/kernel.h> #include <linux/major.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/mman.h> #include <linux/tty.h> #include <linux/console.h> @@ -616,12 +616,9 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) pgprot_val(vma->vm_page_prot) &= ~_CACHE_MASK; pgprot_val(vma->vm_page_prot) |= _CACHE_UNCACHED; #elif defined(__arm__) -#if defined(CONFIG_CPU_32) && !defined(CONFIG_ARCH_ACORN) - /* On Acorn architectures, we want to keep the framebuffer - * cached. - */ - pgprot_val(vma->vm_page_prot) &= ~(PTE_CACHEABLE | PTE_BUFFERABLE); -#endif + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + /* This is an IO map - tell maydump to skip this VMA */ + vma->vm_flags |= VM_IO; #elif defined(__sh__) pgprot_val(vma->vm_page_prot) &= ~_PAGE_CACHABLE; #else diff --git a/drivers/video/g364fb.c b/drivers/video/g364fb.c index 43829e53c..15ed42857 100644 --- a/drivers/video/g364fb.c +++ b/drivers/video/g364fb.c @@ -21,7 +21,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/hgafb.c b/drivers/video/hgafb.c index 8b389f846..5bcdf0d8a 100644 --- a/drivers/video/hgafb.c +++ b/drivers/video/hgafb.c @@ -7,6 +7,8 @@ * * History: * + * - Revision 0.1.7 (23 Jan 2001): fix crash resulting from MDA only cards + * being detected as Hercules. (Paul G.) * - Revision 0.1.6 (17 Aug 2000): new style structs * documentation * - Revision 0.1.5 (13 Mar 2000): spinlocks instead of saveflags();cli();etc @@ -35,7 +37,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> @@ -358,21 +360,22 @@ static int __init hga_card_detect(void) udelay(2); } - if (p_save != q_save) { - switch (inb_p(HGA_STATUS_PORT) & 0x70) { - case 0x10: - hga_type = TYPE_HERCPLUS; - hga_type_name = "HerculesPlus"; - break; - case 0x50: - hga_type = TYPE_HERCCOLOR; - hga_type_name = "HerculesColor"; - break; - default: - hga_type = TYPE_HERC; - hga_type_name = "Hercules"; - break; - } + if (p_save == q_save) + return 0; + + switch (inb_p(HGA_STATUS_PORT) & 0x70) { + case 0x10: + hga_type = TYPE_HERCPLUS; + hga_type_name = "HerculesPlus"; + break; + case 0x50: + hga_type = TYPE_HERCCOLOR; + hga_type_name = "HerculesColor"; + break; + default: + hga_type = TYPE_HERC; + hga_type_name = "Hercules"; + break; } return 1; } diff --git a/drivers/video/hitfb.c b/drivers/video/hitfb.c index 91b2b77eb..747430ebf 100644 --- a/drivers/video/hitfb.c +++ b/drivers/video/hitfb.c @@ -17,7 +17,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/nubus.h> #include <linux/init.h> diff --git a/drivers/video/hpfb.c b/drivers/video/hpfb.c index df23d1aff..a39dbaa85 100644 --- a/drivers/video/hpfb.c +++ b/drivers/video/hpfb.c @@ -13,7 +13,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/fb.h> diff --git a/drivers/video/igafb.c b/drivers/video/igafb.c index ac176a8cf..aa08b6d8a 100644 --- a/drivers/video/igafb.c +++ b/drivers/video/igafb.c @@ -34,7 +34,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/imsttfb.c b/drivers/video/imsttfb.c index 1749f3246..f004fb3ad 100644 --- a/drivers/video/imsttfb.c +++ b/drivers/video/imsttfb.c @@ -22,7 +22,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/leofb.c b/drivers/video/leofb.c index 6b233e5f8..9fca152da 100644 --- a/drivers/video/leofb.c +++ b/drivers/video/leofb.c @@ -1,4 +1,4 @@ -/* $Id: leofb.c,v 1.11 2000/07/26 23:02:52 davem Exp $ +/* $Id: leofb.c,v 1.12 2001/02/13 01:17:15 davem Exp $ * leofb.c: Leo (ZX) 24/8bit frame buffer driver * * Copyright (C) 1996-1999 Jakub Jelinek (jj@ultra.linux.cz) @@ -12,7 +12,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/macfb.c b/drivers/video/macfb.c index 78538935a..d471d7a46 100644 --- a/drivers/video/macfb.c +++ b/drivers/video/macfb.c @@ -25,7 +25,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/nubus.h> #include <linux/init.h> diff --git a/drivers/video/matrox/matroxfb_DAC1064.c b/drivers/video/matrox/matroxfb_DAC1064.c index c080de89a..92ab4e4df 100644 --- a/drivers/video/matrox/matroxfb_DAC1064.c +++ b/drivers/video/matrox/matroxfb_DAC1064.c @@ -1,81 +1,12 @@ /* * - * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400 + * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450. * - * (c) 1998,1999,2000 Petr Vandrovec <vandrove@vc.cvut.cz> + * (c) 1998-2001 Petr Vandrovec <vandrove@vc.cvut.cz> * - * Version: 1.50 2000/08/10 + * Version: 1.52 2001/02/02 * - * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org> - * - * Contributors: "menion?" <menion@mindless.com> - * Betatesting, fixes, ideas - * - * "Kurt Garloff" <garloff@suse.de> - * Betatesting, fixes, ideas, videomodes, videomodes timmings - * - * "Tom Rini" <trini@kernel.crashing.org> - * MTRR stuff, PPC cleanups, betatesting, fixes, ideas - * - * "Bibek Sahu" <scorpio@dodds.net> - * Access device through readb|w|l and write b|w|l - * Extensive debugging stuff - * - * "Daniel Haun" <haund@usa.net> - * Testing, hardware cursor fixes - * - * "Scott Wood" <sawst46+@pitt.edu> - * Fixes - * - * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de> - * Betatesting - * - * "Kelly French" <targon@hazmat.com> - * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es> - * Betatesting, bug reporting - * - * "Pablo Bianucci" <pbian@pccp.com.ar> - * Fixes, ideas, betatesting - * - * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es> - * Fixes, enhandcements, ideas, betatesting - * - * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp> - * PPC betatesting, PPC support, backward compatibility - * - * "Paul Womar" <Paul@pwomar.demon.co.uk> - * "Owen Waller" <O.Waller@ee.qub.ac.uk> - * PPC betatesting - * - * "Thomas Pornin" <pornin@bolet.ens.fr> - * Alpha betatesting - * - * "Pieter van Leuven" <pvl@iae.nl> - * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de> - * G100 testing - * - * "H. Peter Arvin" <hpa@transmeta.com> - * Ideas - * - * "Cort Dougan" <cort@cs.nmt.edu> - * CHRP fixes and PReP cleanup - * - * "Mark Vojkovich" <mvojkovi@ucsd.edu> - * G400 support - * - * "Ken Aaker" <kdaaker@rchland.vnet.ibm.com> - * memtype extension (needed for GXT130P RS/6000 adapter) - * - * (following author is not in any relation with this code, but his code - * is included in this driver) - * - * Based on framebuffer driver for VBE 2.0 compliant graphic boards - * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de> - * - * (following author is not in any relation with this code, but his ideas - * were used when writting this driver) - * - * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk> + * See matroxfb_base.c for contributors. * */ @@ -787,6 +718,11 @@ static int MGAG100_preinit(WPMINFO struct matrox_hw_state* hw){ ACCESS_FBINFO(primout) = &m1064; + if (ACCESS_FBINFO(devflags.g450dac)) { + /* we must do this always, BIOS does not do it for us + and accelerator dies without it */ + mga_outl(0x1C0C, 0); + } if (ACCESS_FBINFO(devflags.noinit)) return 0; hw->MXoptionReg &= 0xC0000100; diff --git a/drivers/video/matrox/matroxfb_base.c b/drivers/video/matrox/matroxfb_base.c index 090895204..e07db7235 100644 --- a/drivers/video/matrox/matroxfb_base.c +++ b/drivers/video/matrox/matroxfb_base.c @@ -2,9 +2,9 @@ * * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400 * - * (c) 1998,1999,2000 Petr Vandrovec <vandrove@vc.cvut.cz> + * (c) 1998-2001 Petr Vandrovec <vandrove@vc.cvut.cz> * - * Version: 1.50 2000/08/10 + * Version: 1.52 2001/02/02 * * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org> * @@ -1409,12 +1409,12 @@ static struct video_board vbG400 = {0x2000000, 0x1000000, FB_ACCEL_MATROX_MGAG4 #define DEVF_VIDEO64BIT 0x0001 #define DEVF_SWAPS 0x0002 -#define DEVF_MILLENNIUM 0x0004 -#define DEVF_MILLENNIUM2 0x0008 +/* #define DEVF_recycled 0x0004 */ +/* #define DEVF_recycled 0x0008 */ #define DEVF_CROSS4MB 0x0010 #define DEVF_TEXT4B 0x0020 #define DEVF_DDC_8_2 0x0040 -#define DEVF_DMA 0x0080 +/* #define DEVF_recycled 0x0080 */ #define DEVF_SUPPORT32MB 0x0100 #define DEVF_ANY_VXRES 0x0200 #define DEVF_TEXT16B 0x0400 @@ -1441,19 +1441,19 @@ static struct board { #ifdef CONFIG_FB_MATROX_MILLENIUM {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL, 0xFF, 0, 0, - DEVF_MILLENNIUM | DEVF_TEXT4B, + DEVF_TEXT4B, 230000, &vbMillennium, "Millennium (PCI)"}, {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2, 0xFF, 0, 0, - DEVF_MILLENNIUM | DEVF_MILLENNIUM2 | DEVF_SWAPS, + DEVF_SWAPS, 220000, &vbMillennium2, "Millennium II (PCI)"}, {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP, 0xFF, 0, 0, - DEVF_MILLENNIUM | DEVF_MILLENNIUM2 | DEVF_SWAPS, + DEVF_SWAPS, 250000, &vbMillennium2A, "Millennium II (AGP)"}, @@ -1461,13 +1461,13 @@ static struct board { #ifdef CONFIG_FB_MATROX_MYSTIQUE {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0x02, 0, 0, - DEVF_VIDEO64BIT, + DEVF_VIDEO64BIT | DEVF_CROSS4MB, 180000, &vbMystique, "Mystique (PCI)"}, {PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0xFF, 0, 0, - DEVF_VIDEO64BIT | DEVF_SWAPS, + DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB, 220000, &vbMystique, "Mystique 220 (PCI)"}, @@ -1842,33 +1842,33 @@ static int initMatrox2(WPMINFO struct display* d, struct board* b){ } /* FIXME: Where to move this?! */ -#if defined(CONFIG_PPC) +#if defined(CONFIG_ALL_PPC) #if defined(CONFIG_FB_COMPAT_XPMAC) strcpy(ACCESS_FBINFO(matrox_name), "MTRX,"); /* OpenFirmware naming convension */ strncat(ACCESS_FBINFO(matrox_name), b->name, 26); if (!console_fb_info) console_fb_info = &ACCESS_FBINFO(fbcon); #endif - if ((xres <= 640) && (yres <= 480)) { +#ifndef MODULE + if (_machine == _MACH_Pmac) { struct fb_var_screeninfo var; - if (default_vmode == VMODE_NVRAM) { - default_vmode = nvram_read_byte(NV_VMODE); - if (default_vmode <= 0 || default_vmode > VMODE_MAX) - default_vmode = VMODE_CHOOSE; - } if (default_vmode <= 0 || default_vmode > VMODE_MAX) default_vmode = VMODE_640_480_60; +#ifdef CONFIG_NVRAM if (default_cmode == CMODE_NVRAM) default_cmode = nvram_read_byte(NV_CMODE); +#endif if (default_cmode < CMODE_8 || default_cmode > CMODE_32) default_cmode = CMODE_8; if (!mac_vmode_to_var(default_vmode, default_cmode, &var)) { var.accel_flags = vesafb_defined.accel_flags; var.xoffset = var.yoffset = 0; - vesafb_defined = var; /* Note: mac_vmode_to_var() doesnot set all parameters */ + /* Note: mac_vmode_to_var() does not set all parameters */ + vesafb_defined = var; } } -#endif /* CONFIG_PPC */ +#endif /* !MODULE */ +#endif /* CONFIG_ALL_PPC */ vesafb_defined.xres_virtual = vesafb_defined.xres; if (nopan) { vesafb_defined.yres_virtual = vesafb_defined.yres; @@ -2005,6 +2005,7 @@ static int matroxfb_probe(struct pci_dev* pdev, const struct pci_device_id* dumm u_int32_t cmd; #ifndef CONFIG_FB_MATROX_MULTIHEAD static int registered = 0; + static struct display global_disp; #endif DBG("matroxfb_probe") @@ -2502,8 +2503,8 @@ int __init matroxfb_init(void) /* *************************** init module code **************************** */ -MODULE_AUTHOR("(c) 1998,1999 Petr Vandrovec <vandrove@vc.cvut.cz>"); -MODULE_DESCRIPTION("Accelerated FBDev driver for Matrox Millennium/Mystique/G100/G200/G400"); +MODULE_AUTHOR("(c) 1998-2001 Petr Vandrovec <vandrove@vc.cvut.cz>"); +MODULE_DESCRIPTION("Accelerated FBDev driver for Matrox Millennium/Mystique/G100/G200/G400/G450"); MODULE_PARM(mem, "i"); MODULE_PARM_DESC(mem, "Size of available memory in MB, KB or B (2,4,8,12,16MB, default=autodetect)"); MODULE_PARM(disabled, "i"); diff --git a/drivers/video/matrox/matroxfb_base.h b/drivers/video/matrox/matroxfb_base.h index 68a8ab883..20c627905 100644 --- a/drivers/video/matrox/matroxfb_base.h +++ b/drivers/video/matrox/matroxfb_base.h @@ -32,7 +32,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/console.h> @@ -589,7 +589,6 @@ static inline struct matrox_fb_info* mxinfo(const struct display* p) { #else extern struct matrox_fb_info matroxfb_global_mxinfo; -struct display global_disp; #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x) #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x) @@ -787,11 +786,7 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv); #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0) #endif -#ifdef __LITTLE_ENDIAN -#define mga_fifo(n) do {} while (mga_inb(M_FIFOSTATUS) < (n)) -#else #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) -#endif #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000) diff --git a/drivers/video/mdacon.c b/drivers/video/mdacon.c index 98e58b46c..bbb046178 100644 --- a/drivers/video/mdacon.c +++ b/drivers/video/mdacon.c @@ -33,7 +33,7 @@ #include <linux/console_struct.h> #include <linux/string.h> #include <linux/kd.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vt_kern.h> #include <linux/vt_buffer.h> #include <linux/selection.h> diff --git a/drivers/video/offb.c b/drivers/video/offb.c index 1a1b7a3db..b0397b1f8 100644 --- a/drivers/video/offb.c +++ b/drivers/video/offb.c @@ -19,7 +19,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/p9100fb.c b/drivers/video/p9100fb.c index f8687d7a7..59d8791c9 100644 --- a/drivers/video/p9100fb.c +++ b/drivers/video/p9100fb.c @@ -11,7 +11,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/platinumfb.c b/drivers/video/platinumfb.c index 20ab5c4e5..34ef08881 100644 --- a/drivers/video/platinumfb.c +++ b/drivers/video/platinumfb.c @@ -24,7 +24,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c index a3ee01ea1..8eee8643c 100644 --- a/drivers/video/pm2fb.c +++ b/drivers/video/pm2fb.c @@ -20,7 +20,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/promcon.c b/drivers/video/promcon.c index 9c7277b70..cc2cac9f1 100644 --- a/drivers/video/promcon.c +++ b/drivers/video/promcon.c @@ -12,7 +12,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/console.h> #include <linux/console_struct.h> diff --git a/drivers/video/q40fb.c b/drivers/video/q40fb.c index a5c68f070..e76d6e979 100644 --- a/drivers/video/q40fb.c +++ b/drivers/video/q40fb.c @@ -3,7 +3,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/retz3fb.c b/drivers/video/retz3fb.c index 9f1be5adc..73d3d4895 100644 --- a/drivers/video/retz3fb.c +++ b/drivers/video/retz3fb.c @@ -26,7 +26,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/zorro.h> diff --git a/drivers/video/riva/Makefile b/drivers/video/riva/Makefile index 07d87e752..a80e814cc 100644 --- a/drivers/video/riva/Makefile +++ b/drivers/video/riva/Makefile @@ -9,7 +9,7 @@ O_TARGET := rivafb.o -obj-y := fbdev.o riva_hw.o +obj-y := fbdev.o riva_hw.o accel.o obj-m := $(O_TARGET) include $(TOPDIR)/Rules.make diff --git a/drivers/video/riva/accel.c b/drivers/video/riva/accel.c new file mode 100644 index 000000000..f3e061923 --- /dev/null +++ b/drivers/video/riva/accel.c @@ -0,0 +1,424 @@ +/* + * linux/drivers/video/accel.c - nVidia RIVA 128/TNT/TNT2 fb driver + * + * Copyright 2000 Jindrich Makovicka, Ani Joshi + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include "rivafb.h" + +/* acceleration routines */ + +inline void wait_for_idle(struct rivafb_info *rinfo) +{ + while (rinfo->riva.Busy(&rinfo->riva)); +} + +/* set copy ROP, no mask */ +static void riva_setup_ROP(struct rivafb_info *rinfo) +{ + RIVA_FIFO_FREE(rinfo->riva, Patt, 5); + rinfo->riva.Patt->Shape = 0; + rinfo->riva.Patt->Color0 = 0xffffffff; + rinfo->riva.Patt->Color1 = 0xffffffff; + rinfo->riva.Patt->Monochrome[0] = 0xffffffff; + rinfo->riva.Patt->Monochrome[1] = 0xffffffff; + + RIVA_FIFO_FREE(rinfo->riva, Rop, 1); + rinfo->riva.Rop->Rop3 = 0xCC; +} + +void riva_setup_accel(struct rivafb_info *rinfo) +{ + RIVA_FIFO_FREE(rinfo->riva, Clip, 2); + rinfo->riva.Clip->TopLeft = 0x0; + rinfo->riva.Clip->WidthHeight = 0x80008000; + riva_setup_ROP(rinfo); + wait_for_idle(rinfo); +} + +static void riva_rectfill(struct rivafb_info *rinfo, int sy, + int sx, int height, int width, u_int color) +{ + RIVA_FIFO_FREE(rinfo->riva, Bitmap, 1); + rinfo->riva.Bitmap->Color1A = color; + + RIVA_FIFO_FREE(rinfo->riva, Bitmap, 2); + rinfo->riva.Bitmap->UnclippedRectangle[0].TopLeft = (sx << 16) | sy; + rinfo->riva.Bitmap->UnclippedRectangle[0].WidthHeight = (width << 16) | height; +} + +static void fbcon_riva_bmove(struct display *p, int sy, int sx, int dy, int dx, + int height, int width) +{ + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + + sx *= fontwidth(p); + sy *= fontheight(p); + dx *= fontwidth(p); + dy *= fontheight(p); + width *= fontwidth(p); + height *= fontheight(p); + + RIVA_FIFO_FREE(rinfo->riva, Blt, 3); + rinfo->riva.Blt->TopLeftSrc = (sy << 16) | sx; + rinfo->riva.Blt->TopLeftDst = (dy << 16) | dx; + rinfo->riva.Blt->WidthHeight = (height << 16) | width; +} + +static void riva_clear_margins(struct vc_data *conp, struct display *p, + int bottom_only, u32 bgx) +{ + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + + unsigned int right_start = conp->vc_cols*fontwidth(p); + unsigned int bottom_start = conp->vc_rows*fontheight(p); + unsigned int right_width, bottom_width; + + if (!bottom_only && (right_width = p->var.xres - right_start)) + riva_rectfill(rinfo, 0, right_start, p->var.yres_virtual, + right_width, bgx); + if ((bottom_width = p->var.yres - bottom_start)) + riva_rectfill(rinfo, p->var.yoffset + bottom_start, 0, + bottom_width, right_start, bgx); +} + +static u8 byte_rev[256] = { + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff, +}; + +static inline void fbcon_reverse_order(u32 *l) +{ + u8 *a = (u8 *)l; + *a++ = byte_rev[*a]; +/* *a++ = byte_rev[*a]; + *a++ = byte_rev[*a];*/ + *a = byte_rev[*a]; +} + +static void fbcon_riva_writechr(struct vc_data *conp, struct display *p, + int c, int fgx, int bgx, int yy, int xx) +{ + u8 *cdat; + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + int w, h; + volatile u32 *d; + u32 cdat2; + int i, j, cnt; + + w = fontwidth(p); + h = fontheight(p); + + if (w <= 8) + cdat = p->fontdata + (c & p->charmask) * h; + else + cdat = p->fontdata + ((c & p->charmask) * h << 1); + + RIVA_FIFO_FREE(rinfo->riva, Bitmap, 7); + rinfo->riva.Bitmap->ClipE.TopLeft = (yy << 16) | (xx & 0xFFFF); + rinfo->riva.Bitmap->ClipE.BottomRight = ((yy+h) << 16) | ((xx+w) & 0xffff); + rinfo->riva.Bitmap->Color0E = bgx; + rinfo->riva.Bitmap->Color1E = fgx; + rinfo->riva.Bitmap->WidthHeightInE = (h << 16) | 32; + rinfo->riva.Bitmap->WidthHeightOutE = (h << 16) | 32; + rinfo->riva.Bitmap->PointE = (yy << 16) | (xx & 0xFFFF); + + d = &rinfo->riva.Bitmap->MonochromeData01E; + for (i = h; i > 0; i-=16) { + if (i >= 16) + cnt = 16; + else + cnt = i; + RIVA_FIFO_FREE(rinfo->riva, Bitmap, cnt); + for (j = 0; j < cnt; j++) { + if (w <= 8) + cdat2 = *cdat++; + else + cdat2 = *((u16*)cdat)++; + fbcon_reverse_order(&cdat2); + d[j] = cdat2; + } + } +} + +#ifdef FBCON_HAS_CFB8 +void fbcon_riva8_setup(struct display *p) +{ + p->next_line = p->line_length ? p->line_length : p->var.xres_virtual; + p->next_plane = 0; +} + +static void fbcon_riva8_clear(struct vc_data *conp, struct display *p, int sy, + int sx, int height, int width) +{ + u32 bgx; + + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + + bgx = attr_bgcol_ec(p, conp); + + sx *= fontwidth(p); + sy *= fontheight(p); + width *= fontwidth(p); + height *= fontheight(p); + + riva_rectfill(rinfo, sy, sx, height, width, bgx); +} + +static void fbcon_riva8_putc(struct vc_data *conp, struct display *p, int c, + int yy, int xx) +{ + u32 fgx,bgx; + + fgx = attr_fgcol(p,c); + bgx = attr_bgcol(p,c); + + xx *= fontwidth(p); + yy *= fontheight(p); + + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); +} + +static void fbcon_riva8_putcs(struct vc_data *conp, struct display *p, + const unsigned short *s, int count, int yy, + int xx) +{ + u16 c; + u32 fgx,bgx; + + xx *= fontwidth(p); + yy *= fontheight(p); + + while (count--) { + c = scr_readw(s++); + fgx = attr_fgcol(p,c); + bgx = attr_bgcol(p,c); + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); + xx += fontwidth(p); + } +} + +static void fbcon_riva8_revc(struct display *p, int xx, int yy) +{ + struct rivafb_info *rinfo = (struct rivafb_info *) (p->fb_info); + + xx *= fontwidth(p); + yy *= fontheight(p); + + RIVA_FIFO_FREE(rinfo->riva, Rop, 1); + rinfo->riva.Rop->Rop3 = 0x66; // XOR + riva_rectfill(rinfo, yy, xx, fontheight(p), fontwidth(p), 0x0f); + RIVA_FIFO_FREE(rinfo->riva, Rop, 1); + rinfo->riva.Rop->Rop3 = 0xCC; // back to COPY +} + +static void fbcon_riva8_clear_margins(struct vc_data *conp, struct display *p, + int bottom_only) +{ + riva_clear_margins(conp, p, bottom_only, attr_bgcol_ec(p, conp)); +} + +struct display_switch fbcon_riva8 = { + setup: fbcon_riva8_setup, + bmove: fbcon_riva_bmove, + clear: fbcon_riva8_clear, + putc: fbcon_riva8_putc, + putcs: fbcon_riva8_putcs, + revc: fbcon_riva8_revc, + clear_margins: fbcon_riva8_clear_margins, + fontwidthmask: FONTWIDTHRANGE(4, 16) +}; +#endif + +#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) +static void fbcon_riva1632_revc(struct display *p, int xx, int yy) +{ + struct rivafb_info *rinfo = (struct rivafb_info *) (p->fb_info); + + xx *= fontwidth(p); + yy *= fontheight(p); + + RIVA_FIFO_FREE(rinfo->riva, Rop, 1); + rinfo->riva.Rop->Rop3 = 0x66; // XOR + riva_rectfill(rinfo, yy, xx, fontheight(p), fontwidth(p), 0xffffffff); + RIVA_FIFO_FREE(rinfo->riva, Rop, 1); + rinfo->riva.Rop->Rop3 = 0xCC; // back to COPY +} +#endif + +#ifdef FBCON_HAS_CFB16 +void fbcon_riva16_setup(struct display *p) +{ + p->next_line = p->line_length ? p->line_length : p->var.xres_virtual<<1; + p->next_plane = 0; +} + +static void fbcon_riva16_clear(struct vc_data *conp, struct display *p, int sy, + int sx, int height, int width) +{ + u32 bgx; + + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + + bgx = ((u_int16_t*)p->dispsw_data)[attr_bgcol_ec(p, conp)]; + + sx *= fontwidth(p); + sy *= fontheight(p); + width *= fontwidth(p); + height *= fontheight(p); + + riva_rectfill(rinfo, sy, sx, height, width, bgx); +} + +static inline void convert_bgcolor_16(u32 *col) +{ + *col = ((*col & 0x00007C00) << 9) + | ((*col & 0x000003E0) << 6) + | ((*col & 0x0000001F) << 3) + | 0xFF000000; +} + +static void fbcon_riva16_putc(struct vc_data *conp, struct display *p, int c, + int yy, int xx) +{ + u32 fgx,bgx; + + fgx = ((u16 *)p->dispsw_data)[attr_fgcol(p,c)]; + bgx = ((u16 *)p->dispsw_data)[attr_bgcol(p,c)]; + if (p->var.green.length == 6) + convert_bgcolor_16(&bgx); + xx *= fontwidth(p); + yy *= fontheight(p); + + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); +} + +static void fbcon_riva16_putcs(struct vc_data *conp, struct display *p, + const unsigned short *s, int count, int yy, + int xx) +{ + u16 c; + u32 fgx,bgx; + + xx *= fontwidth(p); + yy *= fontheight(p); + + while (count--) { + c = scr_readw(s++); + fgx = ((u16 *)p->dispsw_data)[attr_fgcol(p,c)]; + bgx = ((u16 *)p->dispsw_data)[attr_bgcol(p,c)]; + if (p->var.green.length == 6) + convert_bgcolor_16(&bgx); + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); + xx += fontwidth(p); + } +} + +static void fbcon_riva16_clear_margins(struct vc_data *conp, struct display *p, + int bottom_only) +{ + riva_clear_margins(conp, p, bottom_only, ((u16 *)p->dispsw_data)[attr_bgcol_ec(p, conp)]); +} + +struct display_switch fbcon_riva16 = { + setup: fbcon_riva16_setup, + bmove: fbcon_riva_bmove, + clear: fbcon_riva16_clear, + putc: fbcon_riva16_putc, + putcs: fbcon_riva16_putcs, + revc: fbcon_riva1632_revc, + clear_margins: fbcon_riva16_clear_margins, + fontwidthmask: FONTWIDTHRANGE(4, 16) +}; +#endif + +#ifdef FBCON_HAS_CFB32 +void fbcon_riva32_setup(struct display *p) +{ + p->next_line = p->line_length ? p->line_length : p->var.xres_virtual<<2; + p->next_plane = 0; +} + +static void fbcon_riva32_clear(struct vc_data *conp, struct display *p, int sy, + int sx, int height, int width) +{ + u32 bgx; + + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + + bgx = ((u_int32_t*)p->dispsw_data)[attr_bgcol_ec(p, conp)]; + + sx *= fontwidth(p); + sy *= fontheight(p); + width *= fontwidth(p); + height *= fontheight(p); + + riva_rectfill(rinfo, sy, sx, height, width, bgx); +} + +static void fbcon_riva32_putc(struct vc_data *conp, struct display *p, int c, + int yy, int xx) +{ + u32 fgx,bgx; + + fgx = ((u32 *)p->dispsw_data)[attr_fgcol(p,c)]; + bgx = ((u32 *)p->dispsw_data)[attr_bgcol(p,c)]; + xx *= fontwidth(p); + yy *= fontheight(p); + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); +} + +static void fbcon_riva32_putcs(struct vc_data *conp, struct display *p, + const unsigned short *s, int count, int yy, + int xx) +{ + u16 c; + u32 fgx,bgx; + + xx *= fontwidth(p); + yy *= fontheight(p); + + while (count--) { + c = scr_readw(s++); + fgx = ((u32 *)p->dispsw_data)[attr_fgcol(p,c)]; + bgx = ((u32 *)p->dispsw_data)[attr_bgcol(p,c)]; + fbcon_riva_writechr(conp, p, c, fgx, bgx, yy, xx); + xx += fontwidth(p); + } +} + +static void fbcon_riva32_clear_margins(struct vc_data *conp, struct display *p, + int bottom_only) +{ + riva_clear_margins(conp, p, bottom_only, ((u32 *)p->dispsw_data)[attr_bgcol_ec(p, conp)]); +} + +struct display_switch fbcon_riva32 = { + setup: fbcon_riva32_setup, + bmove: fbcon_riva_bmove, + clear: fbcon_riva32_clear, + putc: fbcon_riva32_putc, + putcs: fbcon_riva32_putcs, + revc: fbcon_riva1632_revc, + clear_margins: fbcon_riva32_clear_margins, + fontwidthmask: FONTWIDTHRANGE(4, 16) +}; +#endif diff --git a/drivers/video/riva/fbdev.c b/drivers/video/riva/fbdev.c index fcb662e8e..caebc1917 100644 --- a/drivers/video/riva/fbdev.c +++ b/drivers/video/riva/fbdev.c @@ -12,6 +12,8 @@ * * Ferenc Bakonyi: Bug fixes, cleanup, modularization * + * Jindrich Makovicka: Accel code help, hw cursor, mtrr + * * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven * Includes riva_hw.c from nVidia, see copyright below. * KGI code provided the basis for state storage, init, and mode switching. @@ -19,11 +21,13 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. + * + * Known bugs and issues: + * restoring text mode fails + * doublescan modes are broken + * option 'noaccel' has no effect */ -/* version number of this driver */ -#define RIVAFB_VERSION "0.7.3" - #include <linux/config.h> #include <linux/module.h> #include <linux/kernel.h> @@ -32,34 +36,36 @@ #include <linux/mm.h> #include <linux/selection.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> #include <linux/pci.h> - -#include <video/fbcon.h> - -#include "riva_hw.h" -#include "nv4ref.h" +#include <linux/console.h> +#ifdef CONFIG_MTRR +#include <asm/mtrr.h> +#endif +#include "rivafb.h" #include "nvreg.h" -#include "../vga.h" -#include <video/fbcon-cfb4.h> -#include <video/fbcon-cfb8.h> -#include <video/fbcon-cfb16.h> -#include <video/fbcon-cfb32.h> #ifndef CONFIG_PCI /* sanity check */ #error This driver requires PCI support. #endif -/***************************************************************** + + +/* version number of this driver */ +#define RIVAFB_VERSION "0.9.2a" + + + +/* ------------------------------------------------------------------------- * * * various helpful macros and constants * - */ + * ------------------------------------------------------------------------- */ -/* #define RIVAFBDEBUG */ +#undef RIVAFBDEBUG #ifdef RIVAFBDEBUG #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args) #else @@ -69,31 +75,50 @@ #ifndef RIVA_NDEBUG #define assert(expr) \ if(!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n",\ - #expr,__FILE__,__FUNCTION__,__LINE__); \ + printk( "Assertion failed! %s,%s,%s,line=%d\n",\ + #expr,__FILE__,__FUNCTION__,__LINE__); \ BUG(); \ - } + } #else #define assert(expr) #endif -/* GGI compatibility macros */ -#define io_out8 outb -#define io_in8 inb -#define NUM_SEQ_REGS 0x05 -#define NUM_CRT_REGS 0x41 -#define NUM_GRC_REGS 0x09 -#define NUM_ATC_REGS 0x15 - #define PFX "rivafb: " -#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) - /* macro that allows you to set overflow bits */ #define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) #define SetBit(n) (1<<(n)) #define Set8Bits(value) ((value)&0xff) +/* HW cursor parameters */ +#define DEFAULT_CURSOR_BLINK_RATE (40) +#define CURSOR_HIDE_DELAY (20) +#define CURSOR_SHOW_DELAY (3) + +#define CURSOR_COLOR 0x7fff +#define TRANSPARENT_COLOR 0x0000 +#define MAX_CURS 32 + + + +/* ------------------------------------------------------------------------- * + * + * prototypes + * + * ------------------------------------------------------------------------- */ + +static void rivafb_blank(int blank, struct fb_info *info); + +extern void riva_setup_accel(struct rivafb_info *rinfo); +extern inline void wait_for_idle(struct rivafb_info *rinfo); + + + +/* ------------------------------------------------------------------------- * + * + * card identification + * + * ------------------------------------------------------------------------- */ enum riva_chips { CH_RIVA_128 = 0, @@ -103,187 +128,170 @@ enum riva_chips { CH_RIVA_VTNT2, /* VTNT2 */ CH_RIVA_UVTNT2, /* VTNT2 */ CH_RIVA_ITNT2, /* ITNT2 */ + CH_GEFORCE_SDR, + CH_GEFORCE_DDR, + CH_QUADRO, + CH_GEFORCE2_MX, + CH_QUADRO2_MXR, + CH_GEFORCE2_GTS, + CH_GEFORCE2_ULTRA, + CH_QUADRO2_PRO, }; - /* directly indexed by riva_chips enum, above */ static struct riva_chip_info { const char *name; unsigned arch_rev; } riva_chip_info[] __devinitdata = { - { "RIVA-128", 3 }, - { "RIVA-TNT", 4 }, - { "RIVA-TNT2", 5 }, - { "RIVA-UTNT2", 5 }, - { "RIVA-VTNT2", 5 }, - { "RIVA-UVTNT2", 5 }, - { "RIVA-ITNT2", 5 }, + { "RIVA-128", NV_ARCH_03 }, + { "RIVA-TNT", NV_ARCH_04 }, + { "RIVA-TNT2", NV_ARCH_04 }, + { "RIVA-UTNT2", NV_ARCH_04 }, + { "RIVA-VTNT2", NV_ARCH_04 }, + { "RIVA-UVTNT2", NV_ARCH_04 }, + { "RIVA-ITNT2", NV_ARCH_04 }, + { "GeForce-SDR", NV_ARCH_10}, + { "GeForce-DDR", NV_ARCH_10}, + { "Quadro", NV_ARCH_10}, + { "GeForce2-MX", NV_ARCH_10}, + { "Quadro2-MXR", NV_ARCH_10}, + { "GeForce2-GTS", NV_ARCH_10}, + { "GeForce2-ULTRA", NV_ARCH_10}, + { "Quadro2-PRO", NV_ARCH_10}, }; - static struct pci_device_id rivafb_pci_tbl[] __devinitdata = { - { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, - { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 }, + { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS }, + { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO }, { 0, } /* terminate list */ }; MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); -/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. - * From KGI originally. */ -struct riva_regs { - u8 attr[NUM_ATC_REGS]; - u8 crtc[NUM_CRT_REGS]; - u8 gra[NUM_GRC_REGS]; - u8 seq[NUM_SEQ_REGS]; - u8 misc_output; - RIVA_HW_STATE ext; -}; +/* ------------------------------------------------------------------------- * + * + * framebuffer related structures + * + * ------------------------------------------------------------------------- */ -/* - * describes the state of a Riva board - */ +#ifdef FBCON_HAS_CFB8 +extern struct display_switch fbcon_riva8; +#endif +#ifdef FBCON_HAS_CFB16 +extern struct display_switch fbcon_riva16; +#endif +#ifdef FBCON_HAS_CFB32 +extern struct display_switch fbcon_riva32; +#endif + +#if 0 +/* describes the state of a Riva board */ struct rivafb_par { struct riva_regs state; /* state of hw board */ __u32 visual; /* FB_VISUAL_xxx */ unsigned depth; /* bpp of current mode */ }; - -typedef struct { - unsigned char red, green, blue, transp; -} riva_cfb8_cmap_t; - - - -struct rivafb_info; -struct rivafb_info { - struct fb_info info; /* kernel framebuffer info */ - - RIVA_HW_INST riva; /* interface to riva_hw.c */ - - const char *drvr_name; /* Riva hardware board type */ - - unsigned long ctrl_base_phys; /* physical control register base addr */ - unsigned long fb_base_phys; /* physical framebuffer base addr */ - - caddr_t ctrl_base; /* virtual control register base addr */ - caddr_t fb_base; /* virtual framebuffer base addr */ - - unsigned ram_amount; /* amount of RAM on card, in bytes */ - unsigned dclk_max; /* max DCLK */ - - struct riva_regs initial_state; /* initial startup video mode */ - - struct display disp; - int currcon; - struct display *currcon_display; - - struct rivafb_info *next; - - struct pci_dev *pd; /* pointer to board's pci info */ - unsigned base0_region_size; /* size of control register region */ - unsigned base1_region_size; /* size of framebuffer region */ - - riva_cfb8_cmap_t palette[256]; /* VGA DAC palette cache */ - -#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) - union { -#ifdef FBCON_HAS_CFB16 - u_int16_t cfb16[16]; #endif -#ifdef FBCON_HAS_CFB32 - u_int32_t cfb32[16]; -#endif - } con_cmap; -#endif /* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */ + +struct riva_cursor { + int enable; + int on; + int vbl_cnt; + int last_move_delay; + int blink_rate; + struct { + u16 x, y; + } pos, size; + unsigned short image[MAX_CURS*MAX_CURS]; + struct timer_list *timer; }; -/* ------------------- global variables ------------------------ */ -static struct rivafb_info *riva_boards = NULL; +/* ------------------------------------------------------------------------- * + * + * global variables + * + * ------------------------------------------------------------------------- */ + +struct rivafb_info *riva_boards = NULL; /* command line data, set in rivafb_setup() */ static char fontname[40] __initdata = { 0 }; +static char noaccel __initdata = 0; +static char nomove = 0; +static char nohwcursor __initdata = 0; +static char noblink = 0; +#ifdef CONFIG_MTRR +static char nomtrr __initdata = 0; +#endif + #ifndef MODULE -static char noaccel __initdata = 0; /* unused */ static const char *mode_option __initdata = NULL; +#else +static char *font = NULL; #endif static struct fb_var_screeninfo rivafb_default_var = { - /* 640x480-8@60, yres_virtual=2400 (fits for all Riva cards */ - 640, 480, 640, 2400, 0, 0, 8, 0, - {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, - 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2, - 0, FB_VMODE_NONINTERLACED + xres: 640, + yres: 480, + xres_virtual: 640, + yres_virtual: 480, + xoffset: 0, + yoffset: 0, + bits_per_pixel: 8, + grayscale: 0, + red: {0, 6, 0}, + green: {0, 6, 0}, + blue: {0, 6, 0}, + transp: {0, 0, 0}, + nonstd: 0, + activate: 0, + height: -1, + width: -1, + accel_flags: 0, + pixclock: 39721, + left_margin: 40, + right_margin: 24, + upper_margin: 32, + lower_margin: 11, + hsync_len: 96, + vsync_len: 2, + sync: 0, + vmode: FB_VMODE_NONINTERLACED }; - -/* ------------------- prototypes ------------------------------ */ - -static int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, - struct fb_info *info); -static int rivafb_get_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int rivafb_set_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -static int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info); -static int rivafb_pan_display (struct fb_var_screeninfo *var, int con, - struct fb_info *info); -static int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg, int con, struct fb_info *info); -static int rivafb_switch (int con, struct fb_info *info); -static int rivafb_updatevar (int con, struct fb_info *info); -static void rivafb_blank (int blank, struct fb_info *info); - -static void riva_load_video_mode (struct rivafb_info *rivainfo, - struct fb_var_screeninfo *video_mode); -static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info); -static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info); -static int riva_get_cmap_len (const struct fb_var_screeninfo *var); - -static int riva_set_fbinfo (struct rivafb_info *rinfo); - -static void riva_save_state (struct rivafb_info *rinfo, struct riva_regs *regs); -static void riva_load_state (struct rivafb_info *rinfo, struct riva_regs *regs); -static struct rivafb_info *riva_board_list_add (struct rivafb_info *board_list, - struct rivafb_info *new_node); -static struct rivafb_info *riva_board_list_del (struct rivafb_info *board_list, - struct rivafb_info *del_node); -static void riva_wclut (unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue); - - - - -/* kernel interface */ -static struct fb_ops riva_fb_ops = { - owner: THIS_MODULE, - fb_get_fix: rivafb_get_fix, - fb_get_var: rivafb_get_var, - fb_set_var: rivafb_set_var, - fb_get_cmap: rivafb_get_cmap, - fb_set_cmap: rivafb_set_cmap, - fb_pan_display: rivafb_pan_display, - fb_ioctl: rivafb_ioctl, -}; - - - - /* from GGI */ static const struct riva_regs reg_template = { {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ @@ -297,425 +305,985 @@ static const struct riva_regs reg_template = { 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, /* 0x40 */ + 0x00, /* 0x40 */ }, {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 0xFF}, - {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ - 0xEB /* MISC */ + {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ + 0xEB /* MISC */ }; -/* ------------------- general utility functions -------------------------- */ - -/** - * riva_set_dispsw - * @rinfo: pointer to internal driver struct for a given Riva card +/* ------------------------------------------------------------------------- * * - * DESCRIPTION: - * Sets up console Low level operations depending on the current? color depth - * of the display - */ + * MMIO access macros + * + * ------------------------------------------------------------------------- */ -static void riva_set_dispsw (struct rivafb_info *rinfo) +static inline void CRTCout(struct rivafb_info *rinfo, unsigned char index, + unsigned char val) { - struct display *disp = &rinfo->disp; + VGA_WR08(rinfo->riva.PCIO, 0x3d4, index); + VGA_WR08(rinfo->riva.PCIO, 0x3d5, val); +} - DPRINTK ("ENTER\n"); +static inline unsigned char CRTCin(struct rivafb_info *rinfo, + unsigned char index) +{ + VGA_WR08(rinfo->riva.PCIO, 0x3d4, index); + return (VGA_RD08(rinfo->riva.PCIO, 0x3d5)); +} - assert (rinfo != NULL); +static inline void GRAout(struct rivafb_info *rinfo, unsigned char index, + unsigned char val) +{ + VGA_WR08(rinfo->riva.PVIO, 0x3ce, index); + VGA_WR08(rinfo->riva.PVIO, 0x3cf, val); +} - disp->dispsw_data = NULL; +static inline unsigned char GRAin(struct rivafb_info *rinfo, + unsigned char index) +{ + VGA_WR08(rinfo->riva.PVIO, 0x3ce, index); + return (VGA_RD08(rinfo->riva.PVIO, 0x3cf)); +} - switch (disp->var.bits_per_pixel) { -#ifdef FBCON_HAS_MFB - case 1: - disp->dispsw = &fbcon_mfb; - break; -#endif -#ifdef FBCON_HAS_CFB4 - case 4: - disp->dispsw = &fbcon_cfb4; - break; -#endif -#ifdef FBCON_HAS_CFB8 - case 8: - disp->dispsw = &fbcon_cfb8; - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 15: - case 16: - disp->dispsw = &fbcon_cfb16; - disp->dispsw_data = &rinfo->con_cmap.cfb16; - break; -#endif -#ifdef FBCON_HAS_CFB24 - case 24: - disp->dispsw = &fbcon_cfb24; - disp->dispsw_data = rinfo->con_cmap.cfb24; - break; -#endif -#ifdef FBCON_HAS_CFB32 - case 32: - disp->dispsw = &fbcon_cfb32; - disp->dispsw_data = rinfo->con_cmap.cfb32; - break; -#endif - default: - DPRINTK ("Setting fbcon_dummy renderer\n"); - disp->dispsw = &fbcon_dummy; - } +static inline void SEQout(struct rivafb_info *rinfo, unsigned char index, + unsigned char val) +{ + VGA_WR08(rinfo->riva.PVIO, 0x3c4, index); + VGA_WR08(rinfo->riva.PVIO, 0x3c5, val); +} - DPRINTK ("EXIT\n"); +static inline unsigned char SEQin(struct rivafb_info *rinfo, + unsigned char index) +{ + VGA_WR08(rinfo->riva.PVIO, 0x3c4, index); + return (VGA_RD08(rinfo->riva.PVIO, 0x3c5)); } +static inline void ATTRout(struct rivafb_info *rinfo, unsigned char index, + unsigned char val) +{ + VGA_WR08(rinfo->riva.PCIO, 0x3c0, index); + VGA_WR08(rinfo->riva.PCIO, 0x3c0, val); +} +static inline unsigned char ATTRin(struct rivafb_info *rinfo, + unsigned char index) +{ + VGA_WR08(rinfo->riva.PCIO, 0x3c0, index); + return (VGA_RD08(rinfo->riva.PCIO, 0x3c1)); +} +static inline void MISCout(struct rivafb_info *rinfo, unsigned char val) +{ + VGA_WR08(rinfo->riva.PVIO, 0x3c2, val); +} -static int riva_init_disp_var (struct rivafb_info *rinfo) +static inline unsigned char MISCin(struct rivafb_info *rinfo) { -#ifndef MODULE - if (mode_option) - fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option, - NULL, 0, NULL, 8); -#endif /* !MODULE */ - return 0; + return (VGA_RD08(rinfo->riva.PVIO, 0x3cc)); } +/* ------------------------------------------------------------------------- * + * + * cursor stuff + * + * ------------------------------------------------------------------------- */ -static int __devinit riva_init_disp (struct rivafb_info *rinfo) +/** + * riva_cursor_timer_handler - blink timer + * @dev_addr: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Cursor blink timer. + */ +static void riva_cursor_timer_handler(unsigned long dev_addr) { - struct fb_info *info; - struct display *disp; + struct rivafb_info *rinfo = (struct rivafb_info *)dev_addr; - DPRINTK ("ENTER\n"); + if (!rinfo->cursor) return; - assert (rinfo != NULL); + if (!rinfo->cursor->enable) goto out; - info = &rinfo->info; - disp = &rinfo->disp; + if (rinfo->cursor->last_move_delay < 1000) + rinfo->cursor->last_move_delay++; - disp->var = rivafb_default_var; - info->disp = disp; + if (rinfo->cursor->vbl_cnt && --rinfo->cursor->vbl_cnt == 0) { + rinfo->cursor->on ^= 1; + if (rinfo->cursor->on) + *(rinfo->riva.CURSORPOS) = (rinfo->cursor->pos.x & 0xFFFF) + | (rinfo->cursor->pos.y << 16); + rinfo->riva.ShowHideCursor(&rinfo->riva, rinfo->cursor->on); + if (!noblink) + rinfo->cursor->vbl_cnt = rinfo->cursor->blink_rate; + } +out: + rinfo->cursor->timer->expires = jiffies + (HZ / 100); + add_timer(rinfo->cursor->timer); +} - /* FIXME: assure that disp->cmap is completely filled out */ +/** + * rivafb_init_cursor - allocates cursor structure and starts blink timer + * @rinfo: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Allocates cursor structure and starts blink timer. + * + * RETURNS: + * Pointer to allocated cursor structure. + * + * CALLED FROM: + * rivafb_init_one() + */ +static struct riva_cursor * __init rivafb_init_cursor(struct rivafb_info *rinfo) +{ + struct riva_cursor *cursor; - disp->screen_base = rinfo->fb_base; - disp->visual = FB_VISUAL_PSEUDOCOLOR; - disp->type = FB_TYPE_PACKED_PIXELS; - disp->type_aux = 0; - disp->ypanstep = 1; - disp->ywrapstep = 0; - disp->next_line = disp->line_length = - (disp->var.xres_virtual * disp->var.bits_per_pixel) >> 3; - disp->can_soft_blank = 1; - disp->inverse = 0; + cursor = kmalloc(sizeof(struct riva_cursor), GFP_KERNEL); + if (!cursor) return 0; + memset(cursor, 0, sizeof(*cursor)); - riva_set_dispsw (rinfo); + cursor->timer = kmalloc(sizeof(*cursor->timer), GFP_KERNEL); + if (!cursor->timer) { + kfree(cursor); + return 0; + } + memset(cursor->timer, 0, sizeof(*cursor->timer)); - disp->scrollmode = 0; + cursor->blink_rate = DEFAULT_CURSOR_BLINK_RATE; - rinfo->currcon_display = disp; + init_timer(cursor->timer); + cursor->timer->expires = jiffies + (HZ / 100); + cursor->timer->data = (unsigned long)rinfo; + cursor->timer->function = riva_cursor_timer_handler; + add_timer(cursor->timer); - if ((riva_init_disp_var (rinfo)) < 0) { /* must be done last */ - DPRINTK ("EXIT, returning -1\n"); - return -1; - } + return cursor; +} - DPRINTK ("EXIT, returning 0\n"); - return 0; +/** + * rivafb_exit_cursor - stops blink timer and releases cursor structure + * @rinfo: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Stops blink timer and releases cursor structure. + * + * CALLED FROM: + * rivafb_init_one() + * rivafb_remove_one() + */ +static void rivafb_exit_cursor(struct rivafb_info *rinfo) +{ + struct riva_cursor *cursor = rinfo->cursor; + if (cursor) { + if (cursor->timer) { + del_timer_sync(cursor->timer); + kfree(cursor->timer); + } + kfree(cursor); + rinfo->cursor = 0; + } } +/** + * rivafb_download_cursor - writes cursor shape into card registers + * @rinfo: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Writes cursor shape into card registers. + * + * CALLED FROM: + * riva_load_video_mode() + */ +static void rivafb_download_cursor(struct rivafb_info *rinfo) +{ + int i, save; + int *image; + + if (!rinfo->cursor) return; + + image = (int *)rinfo->cursor->image; + save = rinfo->riva.ShowHideCursor(&rinfo->riva, 0); + for (i = 0; i < (MAX_CURS*MAX_CURS*2)/sizeof(int); i++) + writel(image[i], rinfo->riva.CURSOR + i); + rinfo->riva.ShowHideCursor(&rinfo->riva, save); +} -static int __devinit riva_set_fbinfo (struct rivafb_info *rinfo) +/** + * rivafb_create_cursor - sets rectangular cursor + * @rinfo: pointer to rivafb_info object containing info for current riva board + * @width: cursor width in pixels + * @height: cursor height in pixels + * + * DESCRIPTION: + * Sets rectangular cursor. + * + * CALLED FROM: + * rivafb_set_font() + * rivafb_set_var() + */ +static void rivafb_create_cursor(struct rivafb_info *rinfo, int width, int height) { - struct fb_info *info; + struct riva_cursor *c = rinfo->cursor; + int i, j, idx; - assert (rinfo != NULL); + if (c) { + if (width <= 0 || height <= 0) { + width = 8; + height = 16; + } + if (width > MAX_CURS) width = MAX_CURS; + if (height > MAX_CURS) height = MAX_CURS; - info = &rinfo->info; + c->size.x = width; + c->size.y = height; + + idx = 0; - strcpy (info->modename, rinfo->drvr_name); - info->node = -1; - info->flags = FBINFO_FLAG_DEFAULT; - info->fbops = &riva_fb_ops; + for (i = 0; i < height; i++) { + for (j = 0; j < width; j++,idx++) + c->image[idx] = CURSOR_COLOR; + for (j = width; j < MAX_CURS; j++,idx++) + c->image[idx] = TRANSPARENT_COLOR; + } + for (i = height; i < MAX_CURS; i++) + for (j = 0; j < MAX_CURS; j++,idx++) + c->image[idx] = TRANSPARENT_COLOR; + } +} - /* FIXME: set monspecs to what??? */ +/** + * rivafb_set_font - change font size + * @p: pointer to display object + * @width: font width in pixels + * @height: font height in pixels + * + * DESCRIPTION: + * Callback function called if font settings changed. + * + * RETURNS: + * 1 (Always succeeds.) + */ +static int rivafb_set_font(struct display *p, int width, int height) +{ + struct rivafb_info *fb = (struct rivafb_info *)(p->fb_info); - info->display_fg = NULL; - strncpy (info->fontname, fontname, sizeof (info->fontname)); - info->fontname[sizeof (info->fontname) - 1] = 0; + rivafb_create_cursor(fb, width, height); + return 1; +} - info->changevar = NULL; - info->switch_con = rivafb_switch; - info->updatevar = rivafb_updatevar; - info->blank = rivafb_blank; +/** + * rivafb_cursor - cursor handler + * @p: pointer to display object + * @mode: cursor mode (see CM_*) + * @x: cursor x coordinate in characters + * @y: cursor y coordinate in characters + * + * DESCRIPTION: + * Cursor handler. + */ +static void rivafb_cursor(struct display *p, int mode, int x, int y) +{ + struct rivafb_info *rinfo = (struct rivafb_info *)(p->fb_info); + struct riva_cursor *c = rinfo->cursor; - if (riva_init_disp (rinfo) < 0) /* must be done last */ - return -1; + if (!c) return; - return 0; + x = x * fontwidth(p) - p->var.xoffset; + y = y * fontheight(p) - p->var.yoffset; + + if (c->pos.x == x && c->pos.y == y && (mode == CM_ERASE) == !c->enable) + return; + + c->enable = 0; + if (c->on) rinfo->riva.ShowHideCursor(&rinfo->riva, 0); + + c->pos.x = x; + c->pos.y = y; + + switch (mode) { + case CM_ERASE: + c->on = 0; + break; + case CM_DRAW: + case CM_MOVE: + if (c->last_move_delay <= 1) { /* rapid cursor movement */ + c->vbl_cnt = CURSOR_SHOW_DELAY; + } else { + *(rinfo->riva.CURSORPOS) = (x & 0xFFFF) | (y << 16); + rinfo->riva.ShowHideCursor(&rinfo->riva, 1); + if (!noblink) c->vbl_cnt = CURSOR_HIDE_DELAY; + c->on = 1; + } + c->last_move_delay = 0; + c->enable = 1; + break; + } } +/* ------------------------------------------------------------------------- * + * + * general utility functions + * + * ------------------------------------------------------------------------- */ + +/** + * riva_set_dispsw - sets dispsw + * @rinfo: pointer to internal driver struct for a given Riva card + * @disp: pointer to display object + * + * DESCRIPTION: + * Sets up console low level operations depending on the current? color depth + * of the display. + * + * CALLED FROM: + * rivafb_set_var() + * rivafb_switch() + * riva_init_disp() + */ +static void riva_set_dispsw(struct rivafb_info *rinfo, struct display *disp) +{ + int accel = disp->var.accel_flags & FB_ACCELF_TEXT; + + DPRINTK("ENTER\n"); + + assert(rinfo != NULL); + + disp->dispsw_data = NULL; -/* ----------------------------- PCI bus ----------------------------- */ + disp->screen_base = rinfo->fb_base; + disp->type = FB_TYPE_PACKED_PIXELS; + disp->type_aux = 0; + disp->ypanstep = 1; + disp->ywrapstep = 0; + disp->can_soft_blank = 1; + disp->inverse = 0; + + switch (disp->var.bits_per_pixel) { +#ifdef FBCON_HAS_CFB8 + case 8: + rinfo->dispsw = accel ? fbcon_riva8 : fbcon_cfb8; + disp->dispsw = &rinfo->dispsw; + disp->line_length = disp->var.xres_virtual; + disp->visual = FB_VISUAL_PSEUDOCOLOR; + break; +#endif +#ifdef FBCON_HAS_CFB16 + case 16: + rinfo->dispsw = accel ? fbcon_riva16 : fbcon_cfb16; + disp->dispsw_data = &rinfo->con_cmap.cfb16; + disp->dispsw = &rinfo->dispsw; + disp->line_length = disp->var.xres_virtual * 2; + disp->visual = FB_VISUAL_DIRECTCOLOR; + break; +#endif +#ifdef FBCON_HAS_CFB32 + case 32: + rinfo->dispsw = accel ? fbcon_riva32 : fbcon_cfb32; + disp->dispsw_data = rinfo->con_cmap.cfb32; + disp->dispsw = &rinfo->dispsw; + disp->line_length = disp->var.xres_virtual * 4; + disp->visual = FB_VISUAL_DIRECTCOLOR; + break; +#endif + default: + DPRINTK("Setting fbcon_dummy renderer\n"); + rinfo->dispsw = fbcon_dummy; + disp->dispsw = &rinfo->dispsw; + } + /* FIXME: verify that the above code sets dsp->* fields correctly */ + if (rinfo->cursor) { + rinfo->dispsw.cursor = rivafb_cursor; + rinfo->dispsw.set_font = rivafb_set_font; + } + DPRINTK("EXIT\n"); +} -static int __devinit rivafb_init_one (struct pci_dev *pd, - const struct pci_device_id *ent) +/** + * riva_wclut - set CLUT entry + * @chip: pointer to RIVA_HW_INST object + * @regnum: register number + * @red: red component + * @green: green component + * @blue: blue component + * + * DESCRIPTION: + * Sets color register @regnum. + * + * CALLED FROM: + * riva_setcolreg() + */ +static void riva_wclut(RIVA_HW_INST *chip, + unsigned char regnum, unsigned char red, + unsigned char green, unsigned char blue) { - struct rivafb_info *rinfo; - struct riva_chip_info *rci = &riva_chip_info[ent->driver_data]; + VGA_WR08(chip->PDIO, 0x3c8, regnum); + VGA_WR08(chip->PDIO, 0x3c9, red); + VGA_WR08(chip->PDIO, 0x3c9, green); + VGA_WR08(chip->PDIO, 0x3c9, blue); +} - assert (pd != NULL); - assert (rci != NULL); +/** + * riva_save_state - saves current chip state + * @rinfo: pointer to rivafb_info object containing info for current riva board + * @regs: pointer to riva_regs object + * + * DESCRIPTION: + * Saves current chip state to @regs. + * + * CALLED FROM: + * rivafb_init_one() + */ +/* from GGI */ +static void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs) +{ + int i; - rinfo = kmalloc (sizeof (struct rivafb_info), GFP_KERNEL); - if (!rinfo) - goto err_out; + rinfo->riva.LockUnlock(&rinfo->riva, 0); - memset (rinfo, 0, sizeof (struct rivafb_info)); + rinfo->riva.UnloadStateExt(&rinfo->riva, ®s->ext); - rinfo->drvr_name = rci->name; - rinfo->riva.Architecture = rci->arch_rev; + regs->misc_output = MISCin(rinfo); - rinfo->pd = pd; - rinfo->base0_region_size = pci_resource_len (pd, 0); - rinfo->base1_region_size = pci_resource_len (pd, 1); + for (i = 0; i < NUM_CRT_REGS; i++) { + regs->crtc[i] = CRTCin(rinfo, i); + } - assert (rinfo->base0_region_size >= 0x00800000); /* from GGI */ - assert (rinfo->base1_region_size >= 0x01000000); /* from GGI */ + for (i = 0; i < NUM_ATC_REGS; i++) { + regs->attr[i] = ATTRin(rinfo, i); + } - rinfo->ctrl_base_phys = pci_resource_start (rinfo->pd, 0); - rinfo->fb_base_phys = pci_resource_start (rinfo->pd, 1); + for (i = 0; i < NUM_GRC_REGS; i++) { + regs->gra[i] = GRAin(rinfo, i); + } - if (!request_mem_region (rinfo->ctrl_base_phys, - rinfo->base0_region_size, "rivafb")) { - printk (KERN_ERR PFX "cannot reserve MMIO region\n"); - goto err_out_kfree; + for (i = 0; i < NUM_SEQ_REGS; i++) { + regs->seq[i] = SEQin(rinfo, i); } +} - if (!request_mem_region (rinfo->fb_base_phys, - rinfo->base1_region_size, "rivafb")) { - printk (KERN_ERR PFX "cannot reserve FB region\n"); - goto err_out_free_base0; +/** + * riva_load_state - loads current chip state + * @rinfo: pointer to rivafb_info object containing info for current riva board + * @regs: pointer to riva_regs object + * + * DESCRIPTION: + * Loads chip state from @regs. + * + * CALLED FROM: + * riva_load_video_mode() + * rivafb_init_one() + * rivafb_remove_one() + */ +/* from GGI */ +static void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs) +{ + int i; + RIVA_HW_STATE *state = ®s->ext; + + CRTCout(rinfo, 0x11, 0x00); + + rinfo->riva.LockUnlock(&rinfo->riva, 0); + + rinfo->riva.LoadStateExt(&rinfo->riva, state); + + MISCout(rinfo, regs->misc_output); + + for (i = 0; i < NUM_CRT_REGS; i++) { + switch (i) { + case 0x19: + case 0x20 ... 0x40: + break; + default: + CRTCout(rinfo, i, regs->crtc[i]); + } } - rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, - rinfo->base0_region_size); - if (!rinfo->ctrl_base) { - printk (KERN_ERR PFX "cannot ioremap MMIO base\n"); - goto err_out_free_base1; + for (i = 0; i < NUM_ATC_REGS; i++) { + ATTRout(rinfo, i, regs->attr[i]); } - - rinfo->fb_base = ioremap (rinfo->fb_base_phys, - rinfo->base1_region_size); - if (!rinfo->fb_base) { - printk (KERN_ERR PFX "cannot ioremap FB base\n"); - goto err_out_iounmap_ctrl; + + for (i = 0; i < NUM_GRC_REGS; i++) { + GRAout(rinfo, i, regs->gra[i]); } - - rinfo->riva.EnableIRQ = 0; - rinfo->riva.IO = (inb (0x3CC) & 0x01) ? 0x3D0 : 0x3B0; - rinfo->riva.PRAMDAC = (unsigned *) (rinfo->ctrl_base + 0x00680000); - rinfo->riva.PFB = (unsigned *) (rinfo->ctrl_base + 0x00100000); - rinfo->riva.PFIFO = (unsigned *) (rinfo->ctrl_base + 0x00002000); - rinfo->riva.PGRAPH = (unsigned *) (rinfo->ctrl_base + 0x00400000); - rinfo->riva.PEXTDEV = (unsigned *) (rinfo->ctrl_base + 0x00101000); - rinfo->riva.PTIMER = (unsigned *) (rinfo->ctrl_base + 0x00009000); - rinfo->riva.PMC = (unsigned *) (rinfo->ctrl_base + 0x00000000); - rinfo->riva.FIFO = (unsigned *) (rinfo->ctrl_base + 0x00800000); - switch (rinfo->riva.Architecture) { - case 3: - rinfo->riva.PRAMIN = - (unsigned *) (rinfo->fb_base + 0x00C00000); - break; - case 4: - case 5: - rinfo->riva.PCRTC = - (unsigned *) (rinfo->ctrl_base + 0x00600000); - rinfo->riva.PRAMIN = - (unsigned *) (rinfo->ctrl_base + 0x00710000); - break; + for (i = 0; i < NUM_SEQ_REGS; i++) { + SEQout(rinfo, i, regs->seq[i]); } +} - RivaGetConfig (&rinfo->riva); +/** + * riva_load_video_mode - calculate timings + * @rinfo: pointer to rivafb_info object containing info for current riva board + * @video_mode: video mode to set + * + * DESCRIPTION: + * Calculate some timings and then send em off to riva_load_state(). + * + * CALLED FROM: + * rivafb_set_var() + */ +static void riva_load_video_mode(struct rivafb_info *rinfo, + struct fb_var_screeninfo *video_mode) +{ + struct riva_regs newmode; + int bpp, width, hDisplaySize, hDisplay, hStart, + hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; - /* back to normal */ + /* time to calculate */ - assert (rinfo->pd != NULL); + rivafb_blank(1, (struct fb_info *)rinfo); - /* unlock io */ - vga_io_wcrt (0x11, 0xFF); /* vgaHWunlock() + riva unlock (0x7F) */ - outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO); - outb (0x57, rinfo->riva.LockUnlockIO + 1); + bpp = video_mode->bits_per_pixel; + if (bpp == 16 && video_mode->green.length == 5) + bpp = 15; + width = video_mode->xres_virtual; + hDisplaySize = video_mode->xres; + hDisplay = (hDisplaySize / 8) - 1; + hStart = (hDisplaySize + video_mode->right_margin) / 8 + 2; + hEnd = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len) / 8 - 1; + hTotal = (hDisplaySize + video_mode->right_margin + + video_mode->hsync_len + video_mode->left_margin) / 8 - 1; + height = video_mode->yres_virtual; + vDisplay = video_mode->yres - 1; + vStart = video_mode->yres + video_mode->lower_margin - 1; + vEnd = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len - 1; + vTotal = video_mode->yres + video_mode->lower_margin + + video_mode->vsync_len + video_mode->upper_margin + 2; + dotClock = 1000000000 / video_mode->pixclock; - memcpy (&rinfo->initial_state, ®_template, - sizeof (reg_template)); - riva_save_state (rinfo, &rinfo->initial_state); + memcpy(&newmode, ®_template, sizeof(struct riva_regs)); - rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024; - rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000; + newmode.crtc[0x0] = Set8Bits (hTotal - 4); + newmode.crtc[0x1] = Set8Bits (hDisplay); + newmode.crtc[0x2] = Set8Bits (hDisplay); + newmode.crtc[0x3] = SetBitField (hTotal, 4: 0, 4:0) | SetBit (7); + newmode.crtc[0x4] = Set8Bits (hStart); + newmode.crtc[0x5] = SetBitField (hTotal, 5: 5, 7:7) + | SetBitField (hEnd, 4: 0, 4:0); + newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); + newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) + | SetBitField (vDisplay, 8: 8, 1:1) + | SetBitField (vStart, 8: 8, 2:2) + | SetBitField (vDisplay, 8: 8, 3:3) + | SetBit (4) + | SetBitField (vTotal, 9: 9, 5:5) + | SetBitField (vDisplay, 9: 9, 6:6) + | SetBitField (vStart, 9: 9, 7:7); + newmode.crtc[0x9] = SetBitField (vDisplay, 9: 9, 5:5) + | SetBit (6); + newmode.crtc[0x10] = Set8Bits (vStart); + newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) + | SetBit (5); + newmode.crtc[0x12] = Set8Bits (vDisplay); + newmode.crtc[0x13] = ((width / 8) * ((bpp + 1) / 8)) & 0xFF; + newmode.crtc[0x15] = Set8Bits (vDisplay); + newmode.crtc[0x16] = Set8Bits (vTotal + 1); - riva_set_fbinfo (rinfo); + newmode.ext.bpp = bpp; + newmode.ext.width = width; + newmode.ext.height = height; - fb_memset (rinfo->fb_base, 0, rinfo->ram_amount); + rinfo->riva.CalcStateExt(&rinfo->riva, &newmode.ext, bpp, width, + hDisplaySize, hDisplay, hStart, hEnd, + hTotal, height, vDisplay, vStart, vEnd, + vTotal, dotClock); - riva_load_video_mode (rinfo, &rinfo->disp.var); + rinfo->current_state = newmode; + riva_load_state(rinfo, &rinfo->current_state); - if (register_framebuffer ((struct fb_info *) rinfo) < 0) { - printk (KERN_ERR PFX - "error registering riva framebuffer\n"); - goto err_out_iounmap_fb; - } + rinfo->riva.LockUnlock(&rinfo->riva, 0); /* important for HW cursor */ + rivafb_download_cursor(rinfo); +} - riva_boards = riva_board_list_add(riva_boards, rinfo); +/** + * riva_board_list_add - maintains board list + * @board_list: root node of list of boards + * @new_node: new node to be added + * + * DESCRIPTION: + * Adds @new_node to the list referenced by @board_list. + * + * RETURNS: + * New root node + * + * CALLED FROM: + * rivafb_init_one() + */ +static struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list, + struct rivafb_info *new_node) +{ + struct rivafb_info *i_p = board_list; - pci_set_drvdata (pd, rinfo); + new_node->next = NULL; - printk (KERN_INFO PFX - "PCI Riva NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n", - rinfo->riva.Architecture, - RIVAFB_VERSION, - rinfo->drvr_name, - rinfo->ram_amount / (1024 * 1024) + 1, - rinfo->fb_base_phys); + if (board_list == NULL) + return new_node; - return 0; + while (i_p->next != NULL) + i_p = i_p->next; + i_p->next = new_node; -err_out_iounmap_fb: - iounmap (rinfo->fb_base); -err_out_iounmap_ctrl: - iounmap (rinfo->ctrl_base); -err_out_free_base1: - release_mem_region (rinfo->fb_base_phys, rinfo->base1_region_size); -err_out_free_base0: - release_mem_region (rinfo->ctrl_base_phys, rinfo->base0_region_size); -err_out_kfree: - kfree (rinfo); -err_out: - return -ENODEV; + return board_list; } - -static void __devexit rivafb_remove_one (struct pci_dev *pd) +/** + * riva_board_list_del - maintains board list + * @board_list: root node of list of boards + * @del_node: node to be removed + * + * DESCRIPTION: + * Removes @del_node from the list referenced by @board_list. + * + * RETURNS: + * New root node + * + * CALLED FROM: + * rivafb_remove_one() + */ +static struct rivafb_info *riva_board_list_del(struct rivafb_info *board_list, + struct rivafb_info *del_node) { - struct rivafb_info *board = pci_get_drvdata (pd); - - if (!board) - return; - - riva_boards = riva_board_list_del(riva_boards, board); + struct rivafb_info *i_p = board_list; - riva_load_state (board, &board->initial_state); + if (board_list == del_node) + return del_node->next; - unregister_framebuffer ((struct fb_info *) board); + while (i_p->next != del_node) + i_p = i_p->next; + i_p->next = del_node->next; - iounmap (board->ctrl_base); - iounmap (board->fb_base); + return board_list; +} - release_mem_region (board->ctrl_base_phys, - board->base0_region_size); - release_mem_region (board->fb_base_phys, - board->base1_region_size); +/** + * rivafb_do_maximize - + * @rinfo: pointer to rivafb_info object containing info for current riva board + * @var: + * @v: + * @nom: + * @den: + * + * DESCRIPTION: + * . + * + * RETURNS: + * -EINVAL on failure, 0 on success + * + * + * CALLED FROM: + * rivafb_set_var() + */ +static int rivafb_do_maximize(struct rivafb_info *rinfo, + struct fb_var_screeninfo *var, + struct fb_var_screeninfo *v, + int nom, int den) +{ + static struct { + int xres, yres; + } modes[] = { + {1600, 1280}, + {1280, 1024}, + {1024, 768}, + {800, 600}, + {640, 480}, + {-1, -1} + }; + int i; - kfree (board); + /* use highest possible virtual resolution */ + if (v->xres_virtual == -1 && v->yres_virtual == -1) { + printk(KERN_WARNING PFX + "using maximum available virtual resolution\n"); + for (i = 0; modes[i].xres != -1; i++) { + if (modes[i].xres * nom / den * modes[i].yres < + rinfo->ram_amount / 2) + break; + } + if (modes[i].xres == -1) { + printk(KERN_ERR PFX + "could not find a virtual resolution that fits into video memory!!\n"); + DPRINTK("EXIT - EINVAL error\n"); + return -EINVAL; + } + v->xres_virtual = modes[i].xres; + v->yres_virtual = modes[i].yres; + + printk(KERN_INFO PFX + "virtual resolution set to maximum of %dx%d\n", + v->xres_virtual, v->yres_virtual); + } else if (v->xres_virtual == -1) { + v->xres_virtual = (rinfo->ram_amount * den / + (nom * v->yres_virtual * 2)) & ~15; + printk(KERN_WARNING PFX + "setting virtual X resolution to %d\n", v->xres_virtual); + } else if (v->yres_virtual == -1) { + v->xres_virtual = (v->xres_virtual + 15) & ~15; + v->yres_virtual = rinfo->ram_amount * den / + (nom * v->xres_virtual * 2); + printk(KERN_WARNING PFX + "setting virtual Y resolution to %d\n", v->yres_virtual); + } else { + v->xres_virtual = (v->xres_virtual + 15) & ~15; + if (v->xres_virtual * nom / den * v->yres_virtual > rinfo->ram_amount) { + printk(KERN_ERR PFX + "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", + var->xres, var->yres, var->bits_per_pixel); + DPRINTK("EXIT - EINVAL error\n"); + return -EINVAL; + } + } + + if (v->xres_virtual * nom / den >= 8192) { + printk(KERN_WARNING PFX + "virtual X resolution (%d) is too high, lowering to %d\n", + v->xres_virtual, 8192 * den / nom - 16); + v->xres_virtual = 8192 * den / nom - 16; + } + + if (v->xres_virtual < v->xres) { + printk(KERN_ERR PFX + "virtual X resolution (%d) is smaller than real\n", v->xres_virtual); + return -EINVAL; + } - pci_set_drvdata (pd, NULL); + if (v->yres_virtual < v->yres) { + printk(KERN_ERR PFX + "virtual Y resolution (%d) is smaller than real\n", v->yres_virtual); + return -EINVAL; + } + + return 0; } -/*** riva_wclut - set CLUT entry ***/ -static void riva_wclut (unsigned char regnum, unsigned char red, - unsigned char green, unsigned char blue) + +/* ------------------------------------------------------------------------- * + * + * internal fb_ops helper functions + * + * ------------------------------------------------------------------------- */ + +/** + * riva_get_cmap_len - query current color map length + * @var: standard kernel fb changeable data + * + * DESCRIPTION: + * Get current color map length. + * + * RETURNS: + * Length of color map + * + * CALLED FROM: + * riva_getcolreg() + * riva_setcolreg() + * rivafb_get_cmap() + * rivafb_set_cmap() + */ +static int riva_get_cmap_len(const struct fb_var_screeninfo *var) { - unsigned int data = VGA_PEL_D; + int rc = 16; /* reasonable default */ + + assert(var != NULL); - /* address write mode register is not translated.. */ - vga_io_w (VGA_PEL_IW, regnum); + switch (var->bits_per_pixel) { +#ifdef FBCON_HAS_CFB8 + case 8: + rc = 256; /* pseudocolor... 256 entries HW palette */ + break; +#endif +#ifdef FBCON_HAS_CFB16 + case 16: + rc = 16; /* directcolor... 16 entries SW palette */ + break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ +#endif +#ifdef FBCON_HAS_CFB32 + case 32: + rc = 16; /* directcolor... 16 entries SW palette */ + break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ +#endif + default: + assert(0); + /* should not occur */ + break; + } - vga_io_w (data, red); - vga_io_w (data, green); - vga_io_w (data, blue); + return rc; } +/** + * riva_getcolreg + * @regno: register index + * @red: red component + * @green: green component + * @blue: blue component + * @transp: transparency + * @info: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Read a single color register and split it into colors/transparent. + * The return values must have a 16 bit magnitude. + * + * RETURNS: + * Return != 0 for invalid regno. + * + * CALLED FROM: + * rivafb_get_cmap() + * rivafb_switch() + * fbcmap.c:fb_get_cmap() + * fbgen.c:fbgen_get_cmap() + * fbgen.c:fbgen_switch() + */ +static int riva_getcolreg(unsigned regno, unsigned *red, unsigned *green, + unsigned *blue, unsigned *transp, + struct fb_info *info) +{ + struct rivafb_info *rivainfo = (struct rivafb_info *)info; + if (regno >= riva_get_cmap_len(&rivainfo->currcon_display->var)) + return 1; -/* ------------ Hardware Independent Functions ------------ */ + *red = rivainfo->palette[regno].red; + *green = rivainfo->palette[regno].green; + *blue = rivainfo->palette[regno].blue; + *transp = 0; -#ifndef MODULE -int __init rivafb_setup (char *options) + return 0; +} + +/** + * riva_setcolreg + * @regno: register index + * @red: red component + * @green: green component + * @blue: blue component + * @transp: transparency + * @info: pointer to rivafb_info object containing info for current riva board + * + * DESCRIPTION: + * Set a single color register. The values supplied have a 16 bit + * magnitude. + * + * RETURNS: + * Return != 0 for invalid regno. + * + * CALLED FROM: + * rivafb_set_cmap() + * fbcmap.c:fb_set_cmap() + * fbgen.c:fbgen_get_cmap() + * fbgen.c:fbgen_install_cmap() + * fbgen.c:fbgen_set_var() + * fbgen.c:fbgen_switch() + * fbgen.c:fbgen_blank() + * fbgen.c:fbgen_blank() + */ +static int riva_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) { - char *this_opt; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; + RIVA_HW_INST *chip = &rivainfo->riva; + struct display *p; - if (!options || !*options) - return 0; + DPRINTK("ENTER\n"); - for (this_opt = strtok (options, ","); this_opt; - this_opt = strtok (NULL, ",")) { - if (!strncmp (this_opt, "font:", 5)) { - char *p; - int i; + assert(rivainfo != NULL); + assert(rivainfo->currcon_display != NULL); - p = this_opt + 5; - for (i = 0; i < sizeof (fontname) - 1; i++) - if (!*p || *p == ' ' || *p == ',') - break; - memcpy (fontname, this_opt + 5, i); - fontname[i] = 0; - } + p = rivainfo->currcon_display; - else if (!strncmp (this_opt, "noaccel", 7)) { - noaccel = 1; - } + if (regno >= riva_get_cmap_len(&p->var)) + return -EINVAL; - else - mode_option = this_opt; + rivainfo->palette[regno].red = red; + rivainfo->palette[regno].green = green; + rivainfo->palette[regno].blue = blue; + + if (p->var.grayscale) { + /* gray = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = + (red * 77 + green * 151 + blue * 28) >> 8; } + + switch (p->var.bits_per_pixel) { +#ifdef FBCON_HAS_CFB8 + case 8: + /* "transparent" stuff is completely ignored. */ + riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); + break; +#endif /* FBCON_HAS_CFB8 */ +#ifdef FBCON_HAS_CFB16 + case 16: + assert(regno < 16); + if (p->var.green.length == 5) { + /* 0rrrrrgg gggbbbbb */ + rivainfo->con_cmap.cfb16[regno] = + ((red & 0xf800) >> 1) | + ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); + } else { + /* rrrrrggg gggbbbbb */ + rivainfo->con_cmap.cfb16[regno] = + ((red & 0xf800) >> 0) | + ((green & 0xf800) >> 5) | ((blue & 0xf800) >> 11); + } + break; +#endif /* FBCON_HAS_CFB16 */ +#ifdef FBCON_HAS_CFB32 + case 32: + assert(regno < 16); + rivainfo->con_cmap.cfb32[regno] = + ((red & 0xff00) << 8) | + ((green & 0xff00)) | ((blue & 0xff00) >> 8); + break; +#endif /* FBCON_HAS_CFB32 */ + default: + /* do nothing */ + break; + } + return 0; } -#endif /* !MODULE */ - /* - * Initialization - */ -/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- * + * + * framebuffer operations + * + * ------------------------------------------------------------------------- */ - /* - * Frame buffer operations - */ - -static int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, - struct fb_info *info) +static int rivafb_get_fix(struct fb_fix_screeninfo *fix, int con, + struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; struct display *p; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (fix != NULL); - assert (info != NULL); - assert (rivainfo->drvr_name && rivainfo->drvr_name[0]); - assert (rivainfo->fb_base_phys > 0); - assert (rivainfo->ram_amount > 0); + assert(fix != NULL); + assert(info != NULL); + assert(rivainfo->drvr_name && rivainfo->drvr_name[0]); + assert(rivainfo->fb_base_phys > 0); + assert(rivainfo->ram_amount > 0); p = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - memset (fix, 0, sizeof (struct fb_fix_screeninfo)); - sprintf (fix->id, "Riva %s", rivainfo->drvr_name); + memset(fix, 0, sizeof(struct fb_fix_screeninfo)); + sprintf(fix->id, "nVidia %s", rivainfo->drvr_name); fix->smem_start = rivainfo->fb_base_phys; fix->smem_len = rivainfo->ram_amount; @@ -730,71 +1298,70 @@ static int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con, fix->line_length = p->line_length; - /* FIXME: set up MMIO region, export via FB_ACCEL_xxx */ - fix->mmio_start = 0; - fix->mmio_len = 0; - fix->accel = FB_ACCEL_NONE; + fix->mmio_start = rivainfo->ctrl_base_phys; + fix->mmio_len = rivainfo->base0_region_size; + fix->smem_start = rivainfo->fb_base_phys; + fix->smem_len = rivainfo->base1_region_size; - DPRINTK ("EXIT, returning 0\n"); + switch (rivainfo->riva.Architecture) { + case NV_ARCH_03: + fix->accel = FB_ACCEL_NV3; + break; + case NV_ARCH_04: /* riva_hw.c now doesn't distinguish between TNT & TNT2 */ + fix->accel = FB_ACCEL_NV4; + break; + case NV_ARCH_10: /* FIXME: ID for GeForce */ + fix->accel = FB_ACCEL_NV4; + break; + + } + + DPRINTK("EXIT, returning 0\n"); return 0; } - -static int rivafb_get_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info) +static int rivafb_get_var(struct fb_var_screeninfo *var, int con, + struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (info != NULL); - assert (var != NULL); + assert(info != NULL); + assert(var != NULL); *var = (con < 0) ? rivainfo->disp.var : fb_display[con].var; - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } - - -static int rivafb_set_var (struct fb_var_screeninfo *var, int con, - struct fb_info *info) +static int rivafb_set_var(struct fb_var_screeninfo *var, int con, + struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; struct display *dsp; struct fb_var_screeninfo v; int nom, den; /* translating from pixels->bytes */ - int i; + int accel; unsigned chgvar = 0; - static struct { - int xres, yres; - } modes[] = { - { - 1600, 1280}, { - 1280, 1024}, { - 1024, 768}, { - 800, 600}, { - 640, 480}, { - -1, -1} - }; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (info != NULL); - assert (var != NULL); + assert(info != NULL); + assert(var != NULL); - DPRINTK ("Requested: %dx%dx%d\n", var->xres, var->yres, - var->bits_per_pixel); - DPRINTK (" virtual: %dx%d\n", var->xres_virtual, - var->yres_virtual); - DPRINTK (" offset: (%d,%d)\n", var->xoffset, var->yoffset); - DPRINTK ("grayscale: %d\n", var->grayscale); + DPRINTK("Requested: %dx%dx%d\n", var->xres, var->yres, + var->bits_per_pixel); + DPRINTK(" virtual: %dx%d\n", var->xres_virtual, + var->yres_virtual); + DPRINTK(" offset: (%d,%d)\n", var->xoffset, var->yoffset); + DPRINTK("grayscale: %d\n", var->grayscale); dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - assert (dsp != NULL); + assert(dsp != NULL); /* if var has changed, we should call changevar() later */ if (con >= 0) { @@ -802,135 +1369,84 @@ static int rivafb_set_var (struct fb_var_screeninfo *var, int con, (dsp->var.yres != var->yres) || (dsp->var.xres_virtual != var->xres_virtual) || (dsp->var.yres_virtual != var->yres_virtual) || + (dsp->var.accel_flags != var->accel_flags) || (dsp->var.bits_per_pixel != var->bits_per_pixel) - || memcmp (&dsp->var.red, &var->red, - sizeof (var->red)) - || memcmp (&dsp->var.green, &var->green, - sizeof (var->green)) - || memcmp (&dsp->var.blue, &var->blue, - sizeof (var->blue))); + || memcmp(&dsp->var.red, &var->red, + sizeof(var->red)) + || memcmp(&dsp->var.green, &var->green, + sizeof(var->green)) + || memcmp(&dsp->var.blue, &var->blue, + sizeof(var->blue))); } - memcpy (&v, var, sizeof (v)); + memcpy(&v, var, sizeof(v)); - switch (v.bits_per_pixel) { -#ifdef FBCON_HAS_MFB - case 1: - dsp->dispsw = &fbcon_mfb; - dsp->line_length = v.xres_virtual / 8; - dsp->visual = FB_VISUAL_MONO10; - nom = 4; - den = 8; - break; -#endif + accel = v.accel_flags & FB_ACCELF_TEXT; + switch (v.bits_per_pixel) { #ifdef FBCON_HAS_CFB8 - case 2 ... 8: + case 1 ... 8: v.bits_per_pixel = 8; - dsp->dispsw = &fbcon_cfb8; nom = 1; den = 1; - dsp->line_length = v.xres_virtual; - dsp->visual = FB_VISUAL_PSEUDOCOLOR; v.red.offset = 0; - v.red.length = 6; + v.red.length = 8; v.green.offset = 0; - v.green.length = 6; + v.green.length = 8; v.blue.offset = 0; - v.blue.length = 6; + v.blue.length = 8; break; #endif - #ifdef FBCON_HAS_CFB16 - case 9 ... 16: + case 9 ... 15: + v.green.length = 5; + /* fall through */ + case 16: v.bits_per_pixel = 16; - dsp->dispsw = &fbcon_cfb16; - dsp->dispsw_data = &rivainfo->con_cmap.cfb16; nom = 2; den = 1; - dsp->line_length = v.xres_virtual * 2; - dsp->visual = FB_VISUAL_DIRECTCOLOR; -#ifdef CONFIG_PREP - v.red.offset = 2; - v.green.offset = -3; - v.blue.offset = 8; -#else - v.red.offset = 10; - v.green.offset = 5; - v.blue.offset = 0; -#endif - v.red.length = 5; - v.green.length = 5; - v.blue.length = 5; + if (v.green.length == 5) { + /* 0rrrrrgg gggbbbbb */ + v.red.offset = 10; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = 5; + v.green.length = 5; + v.blue.length = 5; + } else { + /* rrrrrggg gggbbbbb */ + v.red.offset = 11; + v.green.offset = 5; + v.blue.offset = 0; + v.red.length = 5; + v.green.length = 6; + v.blue.length = 5; + } break; #endif - #ifdef FBCON_HAS_CFB32 case 17 ... 32: v.bits_per_pixel = 32; - dsp->dispsw = &fbcon_cfb32; - dsp->dispsw_data = rivainfo->con_cmap.cfb32; nom = 4; den = 1; - dsp->line_length = v.xres_virtual * 4; - dsp->visual = FB_VISUAL_DIRECTCOLOR; -#ifdef CONFIG_PREP - v.red.offset = 8; - v.green.offset = 16; - v.blue.offset = 24; -#else v.red.offset = 16; v.green.offset = 8; v.blue.offset = 0; -#endif v.red.length = 8; v.green.length = 8; v.blue.length = 8; break; #endif - default: - printk (KERN_ERR PFX - "mode %dx%dx%d rejected...color depth not supported.\n", - var->xres, var->yres, var->bits_per_pixel); - DPRINTK ("EXIT, returning -EINVAL\n"); + printk(KERN_ERR PFX + "mode %dx%dx%d rejected...color depth not supported.\n", + var->xres, var->yres, var->bits_per_pixel); + DPRINTK("EXIT, returning -EINVAL\n"); return -EINVAL; } - if (v.xres * nom / den * v.yres > rivainfo->ram_amount) { - printk (KERN_ERR PFX - "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", - var->xres, var->yres, var->bits_per_pixel); - DPRINTK ("EXIT - EINVAL error\n"); + if (rivafb_do_maximize(rivainfo, var, &v, nom, den) < 0) return -EINVAL; - } - - /* use highest possible virtual resolution */ - if (v.xres_virtual == -1 && v.yres_virtual == -1) { - printk (KERN_WARNING PFX - "using maximum available virtual resolution\n"); - for (i = 0; modes[i].xres != -1; i++) { - if (modes[i].xres * nom / den * modes[i].yres < - rivainfo->ram_amount / 2) - break; - } - if (modes[i].xres == -1) { - printk (KERN_ERR PFX - "could not find a virtual resolution that fits into video memory!!\n"); - DPRINTK ("EXIT - EINVAL error\n"); - return -EINVAL; - } - v.xres_virtual = modes[i].xres; - v.yres_virtual = modes[i].yres; - - printk (KERN_INFO PFX - "virtual resolution set to maximum of %dx%d\n", - v.xres_virtual, v.yres_virtual); - } else if (v.xres_virtual == -1) { - /* FIXME: maximize X virtual resolution only */ - } else if (v.yres_virtual == -1) { - /* FIXME: maximize Y virtual resolution only */ - } if (v.xoffset < 0) v.xoffset = 0; @@ -951,103 +1467,107 @@ static int rivafb_set_var (struct fb_var_screeninfo *var, int con, switch (v.activate & FB_ACTIVATE_MASK) { case FB_ACTIVATE_TEST: - DPRINTK ("EXIT - FB_ACTIVATE_TEST\n"); + DPRINTK("EXIT - FB_ACTIVATE_TEST\n"); return 0; case FB_ACTIVATE_NXTOPEN: /* ?? */ case FB_ACTIVATE_NOW: break; /* continue */ default: - DPRINTK ("EXIT - unknown activation type\n"); + DPRINTK("EXIT - unknown activation type\n"); return -EINVAL; /* unknown */ } - dsp->type = FB_TYPE_PACKED_PIXELS; + memcpy(&dsp->var, &v, sizeof(v)); + if (chgvar) { + riva_set_dispsw(rivainfo, dsp); - /* FIXME: verify that the above code sets dsp->* fields correctly */ - - memcpy (&dsp->var, &v, sizeof (v)); + if (accel) { + if (nomove) + dsp->scrollmode = SCROLL_YNOMOVE; + else + dsp->scrollmode = 0; + } else + dsp->scrollmode = SCROLL_YREDRAW; - riva_load_video_mode (rivainfo, &v); + if (info && info->changevar) + info->changevar(con); + } - if (chgvar && info && info->changevar) - info->changevar (con); + rivafb_create_cursor(rivainfo, fontwidth(dsp), fontheight(dsp)); + riva_load_video_mode(rivainfo, &v); + if (accel) riva_setup_accel(rivainfo); - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } - - -static int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info) +static int rivafb_get_cmap(struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; struct display *dsp; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (rivainfo != NULL); - assert (cmap != NULL); + assert(rivainfo != NULL); + assert(cmap != NULL); dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; if (con == rivainfo->currcon) { /* current console? */ - int rc = fb_get_cmap (cmap, kspc, riva_getcolreg, info); - DPRINTK ("EXIT - returning %d\n", rc); + int rc = fb_get_cmap(cmap, kspc, riva_getcolreg, info); + DPRINTK("EXIT - returning %d\n", rc); return rc; } else if (dsp->cmap.len) /* non default colormap? */ - fb_copy_cmap (&dsp->cmap, cmap, kspc ? 0 : 2); + fb_copy_cmap(&dsp->cmap, cmap, kspc ? 0 : 2); else - fb_copy_cmap (fb_default_cmap - (riva_get_cmap_len (&dsp->var)), cmap, - kspc ? 0 : 2); + fb_copy_cmap(fb_default_cmap + (riva_get_cmap_len(&dsp->var)), cmap, + kspc ? 0 : 2); - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } - -static int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, - struct fb_info *info) +static int rivafb_set_cmap(struct fb_cmap *cmap, int kspc, int con, + struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; struct display *dsp; unsigned int cmap_len; - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - assert (cmap != NULL); + DPRINTK("ENTER\n"); + + assert(rivainfo != NULL); + assert(cmap != NULL); dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; - cmap_len = riva_get_cmap_len (&dsp->var); + cmap_len = riva_get_cmap_len(&dsp->var); if (dsp->cmap.len != cmap_len) { - int err = fb_alloc_cmap (&dsp->cmap, cmap_len, 0); + int err = fb_alloc_cmap(&dsp->cmap, cmap_len, 0); if (err) { - DPRINTK ("EXIT - returning %d\n", err); + DPRINTK("EXIT - returning %d\n", err); return err; } } if (con == rivainfo->currcon) { /* current console? */ - int rc = fb_set_cmap (cmap, kspc, riva_setcolreg, info); - DPRINTK ("EXIT - returning %d\n", rc); + int rc = fb_set_cmap(cmap, kspc, riva_setcolreg, info); + DPRINTK("EXIT - returning %d\n", rc); return rc; } else - fb_copy_cmap (cmap, &dsp->cmap, kspc ? 0 : 1); + fb_copy_cmap(cmap, &dsp->cmap, kspc ? 0 : 1); - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } - - /** * rivafb_pan_display * @var: standard kernel fb changeable data - * @con: + * @con: TODO * @info: pointer to rivafb_info object containing info for current riva board * * DESCRIPTION: @@ -1057,17 +1577,16 @@ static int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con, * * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag */ - -static int rivafb_pan_display (struct fb_var_screeninfo *var, int con, - struct fb_info *info) +static int rivafb_pan_display(struct fb_var_screeninfo *var, int con, + struct fb_info *info) { unsigned int base; struct display *dsp; - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (rivainfo != NULL); + assert(rivainfo != NULL); if (var->xoffset > (var->xres_virtual - var->xres)) return -EINVAL; @@ -1089,7 +1608,7 @@ static int rivafb_pan_display (struct fb_var_screeninfo *var, int con, base = var->yoffset * dsp->line_length + var->xoffset; if (con == rivainfo->currcon) { - rivainfo->riva.SetStartAddress (&rivainfo->riva, base); + rivainfo->riva.SetStartAddress(&rivainfo->riva, base); } dsp->var.xoffset = var->xoffset; @@ -1100,606 +1619,512 @@ static int rivafb_pan_display (struct fb_var_screeninfo *var, int con, else dsp->var.vmode &= ~FB_VMODE_YWRAP; - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } - -static int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg, int con, struct fb_info *info) +static int rivafb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, + unsigned long arg, int con, struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - assert (rivainfo != NULL); + assert(rivainfo != NULL); /* no rivafb-specific ioctls */ - DPRINTK ("EXIT, returning -EINVAL\n"); + DPRINTK("EXIT, returning -EINVAL\n"); return -EINVAL; } +static int rivafb_rasterimg(struct fb_info *info, int start) +{ + struct rivafb_info *rinfo = (struct rivafb_info *)info; + + wait_for_idle(rinfo); + + return 0; +} -static int rivafb_switch (int con, struct fb_info *info) +static int rivafb_switch(int con, struct fb_info *info) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct rivafb_info *rivainfo = (struct rivafb_info *)info; struct fb_cmap *cmap; struct display *dsp; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); + + DPRINTK("ENTER\n"); + + assert(rivainfo != NULL); dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con]; if (rivainfo->currcon >= 0) { /* Do we have to save the colormap? */ cmap = &(rivainfo->currcon_display->cmap); - DPRINTK ("switch1: con = %d, cmap.len = %d\n", + DPRINTK("switch1: con = %d, cmap.len = %d\n", rivainfo->currcon, cmap->len); if (cmap->len) { - DPRINTK ("switch1a: %p %p %p %p\n", cmap->red, + DPRINTK("switch1a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp); - fb_get_cmap (cmap, 1, riva_getcolreg, info); -#ifdef DEBUG - if (cmap->red) { - DPRINTK ("switch1r: %X\n", cmap->red[0]); - } -#endif + fb_get_cmap(cmap, 1, riva_getcolreg, info); } } rivainfo->currcon = con; rivainfo->currcon_display = dsp; - dsp->var.activate = FB_ACTIVATE_NOW; - -#ifdef riva_DEBUG - cmap = &dsp->cmap; - DPRINTK ("switch2: con = %d, cmap.len = %d\n", con, cmap->len); - DPRINTK ("switch2a: %p %p %p %p\n", cmap->red, cmap->green, - cmap->blue, cmap->transp); - if (dsp->cmap.red) { - DPRINTK ("switch2r: %X\n", cmap->red[0]); - } -#endif - rivafb_set_var (&dsp->var, con, info); + rivafb_set_var(&dsp->var, con, info); + riva_set_dispsw(rivainfo, dsp); -#ifdef riva_DEBUG - DPRINTK ("switch3: con = %d, cmap.len = %d\n", con, cmap->len); - DPRINTK ("switch3a: %p %p %p %p\n", cmap->red, cmap->green, - cmap->blue, cmap->transp); - if (dsp->cmap.red) { - DPRINTK ("switch3r: %X\n", cmap->red[0]); - } -#endif - - DPRINTK ("EXIT, returning 0\n"); + DPRINTK("EXIT, returning 0\n"); return 0; } -static int rivafb_updatevar (int con, struct fb_info *info) +static int rivafb_updatevar(int con, struct fb_info *info) { int rc; - DPRINTK ("ENTER\n"); + DPRINTK("ENTER\n"); - rc = (con < - 0) ? -EINVAL : rivafb_pan_display (&fb_display[con].var, - con, info); - DPRINTK ("EXIT, returning %d\n", rc); + rc = (con < 0) ? -EINVAL : rivafb_pan_display(&fb_display[con].var, + con, info); + DPRINTK("EXIT, returning %d\n", rc); return rc; } - -static void rivafb_blank (int blank, struct fb_info *info) +static void rivafb_blank(int blank, struct fb_info *info) { - unsigned char tmp; - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - - DPRINTK ("ENTER\n"); - - assert (rivainfo != NULL); - - tmp = vga_io_rseq (VGA_SEQ_CLOCK_MODE) & ~VGA_SR01_SCREEN_OFF; - - if (blank) - tmp |= VGA_SR01_SCREEN_OFF; + unsigned char tmp, vesa; + struct rivafb_info *rinfo = (struct rivafb_info *)info; + + DPRINTK("ENTER\n"); + + assert(rinfo != NULL); + + tmp = SEQin(rinfo, 0x01) & ~0x20; /* screen on/off */ + vesa = CRTCin(rinfo, 0x1a) & ~0xc0; /* sync on/off */ + + if (blank) { + tmp |= 0x20; + switch (blank - 1) { + case VESA_NO_BLANKING: + break; + case VESA_VSYNC_SUSPEND: + vesa |= 0x80; + break; + case VESA_HSYNC_SUSPEND: + vesa |= 0x40; + break; + case VESA_POWERDOWN: + vesa |= 0xc0; + break; + } + } - vga_io_wseq (VGA_SEQ_CLOCK_MODE, tmp); + SEQout(rinfo, 0x01, tmp); + CRTCout(rinfo, 0x1a, vesa); - DPRINTK ("EXIT\n"); + DPRINTK("EXIT\n"); } -/* ------------------------------------------------------------------------- + +/* ------------------------------------------------------------------------- * * - * internal fb_ops helper functions + * initialization helper functions * - * ------------------------------------------------------------------------- - */ + * ------------------------------------------------------------------------- */ +/* kernel interface */ +static struct fb_ops riva_fb_ops = { + owner: THIS_MODULE, + fb_get_fix: rivafb_get_fix, + fb_get_var: rivafb_get_var, + fb_set_var: rivafb_set_var, + fb_get_cmap: rivafb_get_cmap, + fb_set_cmap: rivafb_set_cmap, + fb_pan_display: rivafb_pan_display, + fb_ioctl: rivafb_ioctl, + fb_rasterimg: rivafb_rasterimg, +}; -/** - * riva_get_cmap_len - * @var: - * - * DESCRIPTION: - */ - -static int riva_get_cmap_len (const struct fb_var_screeninfo *var) +static int __devinit riva_init_disp_var(struct rivafb_info *rinfo) { - int rc = 16; /* reasonable default */ - - assert (var != NULL); - - switch (var->bits_per_pixel) { -#ifdef FBCON_HAS_CFB4 - case 4: - rc = 16; /* pseudocolor... 16 entries HW palette */ - break; -#endif -#ifdef FBCON_HAS_CFB8 - case 8: - rc = 256; /* pseudocolor... 256 entries HW palette */ - break; -#endif -#ifdef FBCON_HAS_CFB16 - case 16: - rc = 16; /* directcolor... 16 entries SW palette */ - break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ -#endif -#ifdef FBCON_HAS_CFB32 - case 32: - rc = 16; /* directcolor... 16 entries SW palette */ - break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */ +#ifndef MODULE + if (mode_option) + fb_find_mode(&rinfo->disp.var, &rinfo->info, mode_option, + NULL, 0, NULL, 8); #endif - default: - assert (0); - /* should not occur */ - break; - } - - return rc; + return 0; } - -/** - * riva_getcolreg - * @regno: - * @red: - * @green: - * @blue: - * @transp: - * @info: pointer to rivafb_info object containing info for current riva board - * - * DESCRIPTION: - * Read a single color register and split it into colors/transparent. - * The return values must have a 16 bit magnitude. - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_get_cmap() - * fbgen.c:fbgen_get_cmap() - * fbgen.c:fbgen_switch() - */ - -static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green, - unsigned *blue, unsigned *transp, - struct fb_info *info) +static int __devinit riva_init_disp(struct rivafb_info *rinfo) { - struct rivafb_info *rivainfo = (struct rivafb_info *) info; + struct fb_info *info; + struct display *disp; - if (regno >= riva_get_cmap_len(&rivainfo->currcon_display->var)) - return 1; + DPRINTK("ENTER\n"); - *red = rivainfo->palette[regno].red; - *green = rivainfo->palette[regno].green; - *blue = rivainfo->palette[regno].blue; - *transp = 0; + assert(rinfo != NULL); - return 0; -} + info = &rinfo->info; + disp = &rinfo->disp; + disp->var = rivafb_default_var; + + if (noaccel) + disp->var.accel_flags &= ~FB_ACCELF_TEXT; + else + disp->var.accel_flags |= FB_ACCELF_TEXT; + + info->disp = disp; -/** - * riva_setcolreg - * @regno: - * @red: - * @green: - * @blue: - * @transp: - * @info: pointer to rivafb_info object containing info for current riva board - * - * DESCRIPTION: - * Set a single color register. The values supplied have a 16 bit - * magnitude. - * Return != 0 for invalid regno. - * - * CALLED FROM: - * fbcmap.c:fb_set_cmap() - * fbgen.c:fbgen_get_cmap() - * fbgen.c:fbgen_install_cmap() - * fbgen.c:fbgen_set_var() - * fbgen.c:fbgen_switch() - * fbgen.c:fbgen_blank() - * fbgen.c:fbgen_blank() - */ + /* FIXME: assure that disp->cmap is completely filled out */ -static int riva_setcolreg (unsigned regno, unsigned red, unsigned green, - unsigned blue, unsigned transp, - struct fb_info *info) -{ - struct rivafb_info *rivainfo = (struct rivafb_info *) info; - struct display *p; - unsigned shift = 8; + rinfo->currcon_display = disp; - DPRINTK ("ENTER\n"); + if ((riva_init_disp_var(rinfo)) < 0) { + DPRINTK("EXIT, returning -1\n"); + return -1; + } - assert (rivainfo != NULL); - assert (rivainfo->currcon_display != NULL); + riva_set_dispsw(rinfo, disp); - p = rivainfo->currcon_display; + DPRINTK("EXIT, returning 0\n"); + return 0; - if (regno >= riva_get_cmap_len(&p->var)) - return -EINVAL; +} - rivainfo->palette[regno].red = red; - rivainfo->palette[regno].green = green; - rivainfo->palette[regno].blue = blue; +static int __devinit riva_set_fbinfo(struct rivafb_info *rinfo) +{ + struct fb_info *info; - if (p->var.grayscale) { - /* gray = 0.30*R + 0.59*G + 0.11*B */ - red = green = blue = - (red * 77 + green * 151 + blue * 28) >> 8; - } + assert(rinfo != NULL); - switch (rivainfo->riva.Architecture) { - case 3: - shift = 10; - break; - case 4: - case 5: - shift = 8; - break; - } + info = &rinfo->info; - switch (p->var.bits_per_pixel) { -#ifdef FBCON_HAS_CFB8 - case 8: - /* "transparent" stuff is completely ignored. */ - riva_wclut (regno, red >> shift, green >> shift, blue >> shift); - break; -#endif /* FBCON_HAS_CFB8 */ + strcpy(info->modename, rinfo->drvr_name); + info->node = -1; + info->flags = FBINFO_FLAG_DEFAULT; + info->fbops = &riva_fb_ops; -#ifdef FBCON_HAS_CFB16 - case 16: - assert (regno < 16); -#ifdef CONFIG_PREP - rivainfo->con_cmap.cfb16[regno] = - ((red & 0xf800) >> 9) | - ((green & 0xf800) >> 14) | - ((green & 0xf800) << 2) | ((blue & 0xf800) >> 3); -#else - rivainfo->con_cmap.cfb16[regno] = - ((red & 0xf800) >> 1) | - ((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11); -#endif - break; -#endif /* FBCON_HAS_CFB16 */ + /* FIXME: set monspecs to what??? */ -#ifdef FBCON_HAS_CFB32 - case 32: - assert (regno < 16); -#ifdef CONFIG_PREP - rivainfo->con_cmap.cfb32[regno] = - ((red & 0xff00)) | - ((green & 0xff00) << 8) | ((blue & 0xff00) << 16); -#else - rivainfo->con_cmap.cfb32[regno] = - ((red & 0xff00) << 8) | - ((green & 0xff00)) | ((blue & 0xff00) >> 8); -#endif - break; -#endif /* FBCON_HAS_CFB32 */ + info->display_fg = NULL; + strncpy(info->fontname, fontname, sizeof(info->fontname)); + info->fontname[sizeof(info->fontname) - 1] = 0; - default: - /* do nothing */ - break; - } + info->changevar = NULL; + info->switch_con = rivafb_switch; + info->updatevar = rivafb_updatevar; + info->blank = rivafb_blank; + + if (riva_init_disp(rinfo) < 0) /* must be done last */ + return -1; return 0; } -/* - * riva_load_video_mode() +/* ------------------------------------------------------------------------- * * - * calculate some timings and then send em off to riva_load_state() - */ + * PCI bus + * + * ------------------------------------------------------------------------- */ -static void riva_load_video_mode (struct rivafb_info *rinfo, - struct fb_var_screeninfo *video_mode) +static int __devinit rivafb_init_one(struct pci_dev *pd, + const struct pci_device_id *ent) { - struct riva_regs newmode; - int bpp, width, hDisplaySize, hDisplay, hStart, - hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; - - /* time to calculate */ - - bpp = video_mode->bits_per_pixel; - width = hDisplaySize = video_mode->xres; - hDisplay = (hDisplaySize / 8) - 1; - hStart = (hDisplaySize + video_mode->right_margin) / 8 + 2; - hEnd = (hDisplaySize + video_mode->right_margin + - video_mode->hsync_len) / 8 - 1; - hTotal = (hDisplaySize + video_mode->right_margin + - video_mode->hsync_len + video_mode->left_margin) / 8 - 1; - height = video_mode->yres; - vDisplay = video_mode->yres - 1; - vStart = video_mode->yres + video_mode->lower_margin - 1; - vEnd = video_mode->yres + video_mode->lower_margin + - video_mode->vsync_len - 1; - vTotal = video_mode->yres + video_mode->lower_margin + - video_mode->vsync_len + video_mode->upper_margin + 2; - dotClock = 1000000000 / video_mode->pixclock; - - memcpy (&newmode, ®_template, sizeof (struct riva_regs)); - - newmode.crtc[0x0] = Set8Bits (hTotal - 4); - newmode.crtc[0x1] = Set8Bits (hDisplay); - newmode.crtc[0x2] = Set8Bits (hDisplay); - newmode.crtc[0x3] = SetBitField (hTotal, 4: 0, 4:0) | SetBit (7); - newmode.crtc[0x4] = Set8Bits (hStart); - newmode.crtc[0x5] = SetBitField (hTotal, 5: 5, 7:7) - | SetBitField (hEnd, 4: 0, 4:0); - newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); - newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) - | SetBitField (vDisplay, 8: 8, 1:1) - | SetBitField (vStart, 8: 8, 2:2) - | SetBitField (vDisplay, 8: 8, 3:3) - | SetBit (4) - | SetBitField (vTotal, 9: 9, 5:5) - | SetBitField (vDisplay, 9: 9, 6:6) - | SetBitField (vStart, 9: 9, 7:7); - newmode.crtc[0x9] = SetBitField (vDisplay, 9: 9, 5:5) - | SetBit (6); - newmode.crtc[0x10] = Set8Bits (vStart); - newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) - | SetBit (5); - newmode.crtc[0x12] = Set8Bits (vDisplay); - newmode.crtc[0x13] = ((width / 8) * (bpp / 8)) & 0xFF; - newmode.crtc[0x15] = Set8Bits (vDisplay); - newmode.crtc[0x16] = Set8Bits (vTotal + 1); + struct rivafb_info *rinfo; + struct riva_chip_info *rci = &riva_chip_info[ent->driver_data]; - newmode.ext.bpp = bpp; - newmode.ext.width = width; - newmode.ext.height = height; + assert(pd != NULL); + assert(rci != NULL); - rinfo->riva.CalcStateExt (&rinfo->riva, &newmode.ext, bpp, width, - hDisplaySize, hDisplay, hStart, hEnd, - hTotal, height, vDisplay, vStart, vEnd, - vTotal, dotClock); + rinfo = kmalloc(sizeof(struct rivafb_info), GFP_KERNEL); + if (!rinfo) + goto err_out; - rinfo->initial_state = newmode; - riva_load_state (rinfo, &newmode); -} + memset(rinfo, 0, sizeof(struct rivafb_info)); + rinfo->drvr_name = rci->name; + rinfo->riva.Architecture = rci->arch_rev; -/* ------------------------------------------------------------------------- */ + rinfo->pd = pd; + rinfo->base0_region_size = pci_resource_len(pd, 0); + rinfo->base1_region_size = pci_resource_len(pd, 1); + assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */ + assert(rinfo->base1_region_size >= 0x01000000); /* from GGI */ - /* - * Modularization - */ + rinfo->ctrl_base_phys = pci_resource_start(rinfo->pd, 0); + rinfo->fb_base_phys = pci_resource_start(rinfo->pd, 1); -static struct pci_driver rivafb_driver = { - name: "rivafb", - id_table: rivafb_pci_tbl, - probe: rivafb_init_one, - remove: rivafb_remove_one, -}; + if (!request_mem_region(rinfo->ctrl_base_phys, + rinfo->base0_region_size, "rivafb")) { + printk(KERN_ERR PFX "cannot reserve MMIO region\n"); + goto err_out_kfree; + } + if (!request_mem_region(rinfo->fb_base_phys, + rinfo->base1_region_size, "rivafb")) { + printk(KERN_ERR PFX "cannot reserve FB region\n"); + goto err_out_free_base0; + } + + rinfo->ctrl_base = ioremap(rinfo->ctrl_base_phys, + rinfo->base0_region_size); + if (!rinfo->ctrl_base) { + printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); + goto err_out_free_base1; + } + + rinfo->fb_base = ioremap(rinfo->fb_base_phys, + rinfo->base1_region_size); + if (!rinfo->fb_base) { + printk(KERN_ERR PFX "cannot ioremap FB base\n"); + goto err_out_iounmap_ctrl; + } + +#ifdef CONFIG_MTRR + if (!nomtrr) { + rinfo->mtrr.vram = mtrr_add(rinfo->fb_base_phys, + rinfo->base1_region_size, MTRR_TYPE_WRCOMB, 1); + if (rinfo->mtrr.vram < 0) { + printk(KERN_ERR PFX "unable to setup MTRR\n"); + } else { + rinfo->mtrr.vram_valid = 1; + /* let there be speed */ + printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); + } + } +#endif /* CONFIG_MTRR */ -int __init rivafb_init (void) -{ - return pci_module_init (&rivafb_driver); -} + rinfo->riva.EnableIRQ = 0; + rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base + 0x00680000); + rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base + 0x00100000); + rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base + 0x00002000); + rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base + 0x00400000); + rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base + 0x00101000); + rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base + 0x00009000); + rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base + 0x00000000); + rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base + 0x00800000); + rinfo->riva.PCIO = (U008 *)(rinfo->ctrl_base + 0x00601000); + rinfo->riva.PDIO = (U008 *)(rinfo->ctrl_base + 0x00681000); + rinfo->riva.PVIO = (U008 *)(rinfo->ctrl_base + 0x000C0000); -static void __exit rivafb_exit (void) -{ - pci_unregister_driver (&rivafb_driver); -} + rinfo->riva.IO = (MISCin(rinfo) & 0x01) ? 0x3D0 : 0x3B0; + switch (rinfo->riva.Architecture) { + case NV_ARCH_03: + rinfo->riva.PRAMIN = (unsigned *)(rinfo->fb_base + 0x00C00000); + break; + case NV_ARCH_04: + case NV_ARCH_10: + rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base + 0x00600000); + rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base + 0x00710000); + break; + } -#ifdef MODULE -module_init(rivafb_init); -#endif /* MODULE */ -module_exit(rivafb_exit); + RivaGetConfig(&rinfo->riva); -MODULE_AUTHOR("Ani Joshi, maintainer"); -MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2"); + /* back to normal */ + assert(rinfo->pd != NULL); -/* from GGI */ -static void riva_save_state (struct rivafb_info *rinfo, struct riva_regs *regs) -{ - int i; + /* unlock io */ + CRTCout(rinfo, 0x11, 0xFF); /* vgaHWunlock() + riva unlock (0x7F) */ + rinfo->riva.LockUnlock(&rinfo->riva, 0); - outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO); - outb (0x57, rinfo->riva.LockUnlockIO + 1); + riva_save_state(rinfo, &rinfo->initial_state); - rinfo->riva.UnloadStateExt (&rinfo->riva, ®s->ext); + rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024; + rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000; - regs->misc_output = io_in8 (0x3CC); + if (!nohwcursor) rinfo->cursor = rivafb_init_cursor(rinfo); - for (i = 0; i < NUM_CRT_REGS; i++) { - io_out8 (i, 0x3D4); - regs->crtc[i] = io_in8 (0x3D5); + if (riva_set_fbinfo(rinfo) < 0) { + printk(KERN_ERR PFX "error setting initial video mode\n"); + goto err_out_cursor; } - for (i = 0; i < NUM_ATC_REGS; i++) { - io_out8 (i, 0x3C0); - regs->attr[i] = io_in8 (0x3C1); + if (register_framebuffer((struct fb_info *)rinfo) < 0) { + printk(KERN_ERR PFX + "error registering riva framebuffer\n"); + goto err_out_load_state; } - for (i = 0; i < NUM_GRC_REGS; i++) { - io_out8 (i, 0x3CE); - regs->gra[i] = io_in8 (0x3CF); - } + riva_boards = riva_board_list_add(riva_boards, rinfo); + pci_set_drvdata(pd, rinfo); - for (i = 0; i < NUM_SEQ_REGS; i++) { - io_out8 (i, 0x3C4); - regs->seq[i] = io_in8 (0x3C5); - } -} + printk(KERN_INFO PFX + "PCI nVidia NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n", + rinfo->riva.Architecture, + RIVAFB_VERSION, + rinfo->drvr_name, + rinfo->ram_amount / (1024 * 1024), + rinfo->fb_base_phys); + return 0; -/* from GGI */ -static -void riva_load_state (struct rivafb_info *rinfo, struct riva_regs *regs) +err_out_load_state: + riva_load_state(rinfo, &rinfo->initial_state); +err_out_cursor: + rivafb_exit_cursor(rinfo); +/* err_out_iounmap_fb: */ + iounmap(rinfo->fb_base); +err_out_iounmap_ctrl: + iounmap(rinfo->ctrl_base); +err_out_free_base1: + release_mem_region(rinfo->fb_base_phys, rinfo->base1_region_size); +err_out_free_base0: + release_mem_region(rinfo->ctrl_base_phys, rinfo->base0_region_size); +err_out_kfree: + kfree(rinfo); +err_out: + return -ENODEV; +} + +static void __devexit rivafb_remove_one(struct pci_dev *pd) { - int i; - RIVA_HW_STATE *state = ®s->ext; + struct rivafb_info *board = pci_get_drvdata(pd); + + if (!board) + return; - io_out8 (0x11, 0x3D4); - io_out8 (0x00, 0x3D5); + riva_boards = riva_board_list_del(riva_boards, board); - outb (rinfo->riva.LockUnlockIndex, rinfo->riva.LockUnlockIO); - outb (0x57, rinfo->riva.LockUnlockIO + 1); + riva_load_state(board, &board->initial_state); - rinfo->riva.LoadStateExt (&rinfo->riva, state); + unregister_framebuffer((struct fb_info *)board); - io_out8 (regs->misc_output, 0x3C2); + rivafb_exit_cursor(board); - for (i = 0; i < NUM_CRT_REGS; i++) { - if (i < 0x19) { - io_out8 (i, 0x3D4); - io_out8 (regs->crtc[i], 0x3D5); - } else { - switch (i) { - case 0x19: - case 0x20: - case 0x21: - case 0x22: - case 0x23: - case 0x24: - case 0x25: - case 0x26: - case 0x27: - case 0x28: - case 0x29: - case 0x2a: - case 0x2b: - case 0x2c: - case 0x2d: - case 0x2e: - case 0x2f: - case 0x30: - case 0x31: - case 0x32: - case 0x33: - case 0x34: - case 0x35: - case 0x36: - case 0x37: - case 0x38: - case 0x39: - case 0x3a: - case 0x3b: - case 0x3c: - case 0x3d: - case 0x3e: - case 0x3f: - case 0x40: - break; - default: - io_out8 (i, 0x3D4); - io_out8 (regs->crtc[i], 0x3D5); - } - } - } +#ifdef CONFIG_MTRR + if (board->mtrr.vram_valid) + mtrr_del(board->mtrr.vram, board->fb_base_phys, + board->base1_region_size); +#endif /* CONFIG_MTRR */ - for (i = 0; i < NUM_ATC_REGS; i++) { - io_out8 (i, 0x3C0); - io_out8 (regs->attr[i], 0x3C0); - } + iounmap(board->ctrl_base); + iounmap(board->fb_base); - for (i = 0; i < NUM_GRC_REGS; i++) { - io_out8 (i, 0x3CE); - io_out8 (regs->gra[i], 0x3CF); - } + release_mem_region(board->ctrl_base_phys, + board->base0_region_size); + release_mem_region(board->fb_base_phys, + board->base1_region_size); - for (i = 0; i < NUM_SEQ_REGS; i++) { - io_out8 (i, 0x3C4); - io_out8 (regs->seq[i], 0x3C5); - } -} + kfree(board); + pci_set_drvdata(pd, NULL); +} -/** - * riva_board_list_add - * @board_list: Root node of list of boards - * @new_node: New node to be added +/* ------------------------------------------------------------------------- * * - * DESCRIPTION: - * Adds @new_node to the list referenced by @board_list + * initialization * - * RETURNS: - * New root node - */ -static -struct rivafb_info *riva_board_list_add (struct rivafb_info *board_list, - struct rivafb_info *new_node) + * ------------------------------------------------------------------------- */ + +#ifndef MODULE +int __init rivafb_setup(char *options) { - struct rivafb_info *i_p = board_list; + char *this_opt; - new_node->next = NULL; + if (!options || !*options) + return 0; - if (board_list == NULL) - return new_node; + for (this_opt = strtok(options, ","); this_opt; + this_opt = strtok(NULL, ",")) { + if (!strncmp(this_opt, "font:", 5)) { + char *p; + int i; - while (i_p->next != NULL) - i_p = i_p->next; - i_p->next = new_node; + p = this_opt + 5; + for (i = 0; i < sizeof(fontname) - 1; i++) + if (!*p || *p == ' ' || *p == ',') + break; + memcpy(fontname, this_opt + 5, i); + fontname[i] = 0; - return board_list; + } else if (!strncmp(this_opt, "noblink", 7)) { + noblink = 1; + } else if (!strncmp(this_opt, "noaccel", 7)) { + noaccel = 1; + } else if (!strncmp(this_opt, "nomove", 6)) { + nomove = 1; +#ifdef CONFIG_MTRR + } else if (!strncmp(this_opt, "nomtrr", 6)) { + nomtrr = 1; +#endif + } else if (!strncmp(this_opt, "nohwcursor", 10)) { + nohwcursor = 1; + } else + mode_option = this_opt; + } + return 0; } +#endif /* !MODULE */ +static struct pci_driver rivafb_driver = { + name: "rivafb", + id_table: rivafb_pci_tbl, + probe: rivafb_init_one, + remove: rivafb_remove_one, +}; -/** - * riva_board_list_del - * @board_list: Root node of list of boards - * @del_node: Node to be removed + +/* ------------------------------------------------------------------------- * * - * DESCRIPTION: - * Removes @del_node from the list referenced by @board_list + * modularization * - * RETURNS: - * New root node - */ -static -struct rivafb_info *riva_board_list_del (struct rivafb_info *board_list, - struct rivafb_info *del_node) -{ - struct rivafb_info *i_p = board_list; + * ------------------------------------------------------------------------- */ - if (board_list == del_node) - return del_node->next; +int __init rivafb_init(void) +{ + int err; +#ifdef MODULE + if (font) strncpy(fontname, font, sizeof(fontname)-1); +#endif + err = pci_module_init(&rivafb_driver); + if (err) + return err; + return 0; +} - while (i_p->next != del_node) - i_p = i_p->next; - i_p->next = del_node->next; - return board_list; +#ifdef MODULE +static void __exit rivafb_exit(void) +{ + pci_unregister_driver(&rivafb_driver); } +module_init(rivafb_init); +module_exit(rivafb_exit); + +MODULE_PARM(font, "s"); +MODULE_PARM_DESC(font, "Specifies one of the compiled-in fonts (default=none)"); +MODULE_PARM(noaccel, "i"); +MODULE_PARM_DESC(noaccel, "Disables hardware acceleration (0 or 1=disabled) (default=0)"); +MODULE_PARM(nomove, "i"); +MODULE_PARM_DESC(nomove, "Enables YSCROLL_NOMOVE (0 or 1=enabled) (default=0)"); +MODULE_PARM(nohwcursor, "i"); +MODULE_PARM_DESC(nohwcursor, "Disables hardware cursor (0 or 1=disabled) (default=0)"); +MODULE_PARM(noblink, "i"); +MODULE_PARM_DESC(noblink, "Disables hardware cursor blinking (0 or 1=disabled) (default=0)"); +#ifdef CONFIG_MTRR +MODULE_PARM(nomtrr, "i"); +MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); +#endif +#endif /* MODULE */ + +MODULE_AUTHOR("Ani Joshi, maintainer"); +MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2"); diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c index 532f8c017..f6f0f785b 100644 --- a/drivers/video/riva/riva_hw.c +++ b/drivers/video/riva/riva_hw.c @@ -1,6 +1,6 @@ /***************************************************************************\ |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |* international laws. Users and possessors of this source code are *| @@ -11,7 +11,7 @@ |* tion and internal comments to the code, notices to the end user *| |* as follows: *| |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| @@ -36,52 +36,84 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of + +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c,v 1.1.2.3 1998/12/26 00:12:39 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.8 2000/02/08 17:19:11 dawes Exp $ */ -#include <linux/kernel.h> -#include <asm/io.h> #include "riva_hw.h" #include "riva_tbl.h" - - /* * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT * operate identically (except TNT has more memory and better 3D quality. */ - static int nv3Busy ( RIVA_HW_INST *chip ) { - return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x000006B0/4] & 0x01)); + return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01)); } static int nv4Busy ( RIVA_HW_INST *chip ) { - return ((!(chip->PFIFO[0x00001214/4] & 0x10)) | (chip->PGRAPH[0x00000700/4] & 0x01)); + return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01)); } +static int nv10Busy +( + RIVA_HW_INST *chip +) +{ + return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01)); +} +static void nv3LockUnlock +( + RIVA_HW_INST *chip, + int LockUnlock +) +{ + VGA_WR08(chip->PVIO, 0x3C4, 0x06); + VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); +} +static void nv4LockUnlock +( + RIVA_HW_INST *chip, + int LockUnlock +) +{ + VGA_WR08(chip->PCIO, 0x3D4, 0x1F); + VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); +} +static void nv10LockUnlock +( + RIVA_HW_INST *chip, + int LockUnlock +) +{ + VGA_WR08(chip->PCIO, 0x3D4, 0x1F); + VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); +} + static int ShowHideCursor ( RIVA_HW_INST *chip, int ShowHide ) { - int xcurrent; - xcurrent = chip->CurrentState->cursor1; - chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | (ShowHide & 0x01); - outb(0x31, 0x3D4); - outb(chip->CurrentState->cursor1, 0x3D5); - return (xcurrent & 0x01); + int current; + current = chip->CurrentState->cursor1; + chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | + (ShowHide & 0x01); + VGA_WR08(chip->PCIO, 0x3D4, 0x31); + VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); + return (current & 0x01); } /****************************************************************************\ @@ -171,6 +203,27 @@ typedef struct { char mem_aligned; char enable_mp; } nv4_sim_state; +typedef struct { + int graphics_lwm; + int video_lwm; + int graphics_burst_size; + int video_burst_size; + int valid; +} nv10_fifo_info; +typedef struct { + int pclk_khz; + int mclk_khz; + int nvclk_khz; + char mem_page_miss; + char mem_latency; + int memory_type; + int memory_width; + char enable_video; + char gr_during_vid; + char pix_bpp; + char mem_aligned; + char enable_mp; +} nv10_sim_state; static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) { int iter = 0; @@ -215,7 +268,7 @@ static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_i if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; - gfsize = ns *ainfo->gdrain_rate/1000000; + gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; } mfsize = 0; @@ -312,7 +365,7 @@ static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_i } ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; tmp = ns * ainfo->gdrain_rate/1000000; - if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) + if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) { ainfo->converged = 0; return (1); @@ -468,32 +521,27 @@ static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_ar int done, g,v, p; done = 0; - if (state->gr_during_vid && ainfo->vid_en) - ainfo->priority = MPORT; - else - ainfo->priority = ainfo->gdrain_rate < ainfo->vdrain_rate ? VIDEO: GRAPHICS; - for (p=0; p < 2 && done != 1; p++) + for (p=0; p < 2; p++) { - for (g=128 ; (g > 32) && (done != 1); g= g>> 1) + for (g=128 ; g > 32; g= g>> 1) { - for (v=128; (v >=32) && (done !=1); v = v>> 1) + for (v=128; v >=32; v = v>> 1) { ainfo->priority = p; ainfo->gburst_size = g; ainfo->vburst_size = v; done = nv3_arb(res_info, state,ainfo); - if (g==128) - { + if (done && (g==128)) if ((res_info->graphics_lwm + g) > 256) done = 0; - } + if (done) + goto Done; } } } - if (!done) - return (0); - else - return (1); + + Done: + return done; } static void nv3CalcArbitration ( @@ -509,7 +557,7 @@ static void nv3CalcArbitration ainfo.vid_en = state->enable_video; ainfo.vid_only_once = 0; ainfo.gr_only_once = 0; - ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; + ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); ainfo.vdrain_rate = (int) state->pclk_khz * 2; if (state->video_scale != 0) ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; @@ -527,7 +575,7 @@ static void nv3CalcArbitration ainfo.vid_en = 1; ainfo.vid_only_once = 1; ainfo.gr_en = 1; - ainfo.gdrain_rate = (int) state->pclk_khz * state -> pix_bpp/8; + ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); ainfo.vdrain_rate = 0; res_gr = nv3_get_param(res_info, state, &ainfo); res_gr = ainfo.converged; @@ -543,7 +591,7 @@ static void nv3CalcArbitration res_info->valid = ainfo.converged; } } -void nv3UpdateArbitrationSettings +static void nv3UpdateArbitrationSettings ( unsigned VClk, unsigned pixelDepth, @@ -565,9 +613,10 @@ void nv3UpdateArbitrationSettings sim_data.video_scale = 1; sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; sim_data.memory_width = 128; - sim_data.mem_latency = 11; + + sim_data.mem_latency = 9; sim_data.mem_aligned = 1; - sim_data.mem_page_miss = 9; + sim_data.mem_page_miss = 11; sim_data.gr_during_vid = 0; sim_data.pclk_khz = VClk; sim_data.mclk_khz = MClk; @@ -582,7 +631,7 @@ void nv3UpdateArbitrationSettings else { *lwm = 0x24; - *burst = 0x02; + *burst = 0x2; } } static void nv4CalcArbitration @@ -592,7 +641,7 @@ static void nv4CalcArbitration ) { int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; - int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs=0; + int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; int found, mclk_extra, mclk_loop, cbs, m1, p1; int mclk_freq, pclk_freq, nvclk_freq, mp_enable; int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; @@ -636,6 +685,7 @@ static void nv4CalcArbitration nvclks += 0; pclks += 0; found = 0; + vbs = 0; while (found != 1) { fifo->valid = 1; @@ -768,6 +818,268 @@ static void nv4UpdateArbitrationSettings *lwm = fifo_data.graphics_lwm >> 3; } } +static void nv10CalcArbitration +( + nv10_fifo_info *fifo, + nv10_sim_state *arb +) +{ + int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; + int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; + int nvclk_fill, us_extra; + int found, mclk_extra, mclk_loop, cbs, m1; + int mclk_freq, pclk_freq, nvclk_freq, mp_enable; + int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; + int vus_m, vus_n, vus_p; + int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; + int clwm_rnd_down; + int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; + int pclks_2_top_fifo, min_mclk_extra; + int us_min_mclk_extra; + + fifo->valid = 1; + pclk_freq = arb->pclk_khz; /* freq in KHz */ + mclk_freq = arb->mclk_khz; + nvclk_freq = arb->nvclk_khz; + pagemiss = arb->mem_page_miss; + cas = arb->mem_latency; + width = arb->memory_width/64; + video_enable = arb->enable_video; + color_key_enable = arb->gr_during_vid; + bpp = arb->pix_bpp; + align = arb->mem_aligned; + mp_enable = arb->enable_mp; + clwm = 0; + vlwm = 1024; + + cbs = 512; + vbs = 512; + + pclks = 4; /* lwm detect. */ + + nvclks = 3; /* lwm -> sync. */ + nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ + + mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ + + mclks += 1; /* arb_hp_req */ + mclks += 5; /* ap_hp_req tiling pipeline */ + + mclks += 2; /* tc_req latency fifo */ + mclks += 2; /* fb_cas_n_ memory request to fbio block */ + mclks += 7; /* sm_d_rdv data returned from fbio block */ + + /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ + if (arb->memory_type == 0) + if (arb->memory_width == 64) /* 64 bit bus */ + mclks += 4; + else + mclks += 2; + else + if (arb->memory_width == 64) /* 64 bit bus */ + mclks += 2; + else + mclks += 1; + + if ((!video_enable) && (arb->memory_width == 128)) + { + mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ + min_mclk_extra = 17; + } + else + { + mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ + /* mclk_extra = 4; */ /* Margin of error */ + min_mclk_extra = 18; + } + + nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ + nvclks += 1; /* fbi_d_rdv_n */ + nvclks += 1; /* Fbi_d_rdata */ + nvclks += 1; /* crtfifo load */ + + if(mp_enable) + mclks+=4; /* Mp can get in with a burst of 8. */ + /* Extra clocks determined by heuristics */ + + nvclks += 0; + pclks += 0; + found = 0; + while(found != 1) { + fifo->valid = 1; + found = 1; + mclk_loop = mclks+mclk_extra; + us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ + us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ + us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; + us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ + us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ + us_pipe = us_m + us_n + us_p; + us_pipe_min = us_m_min + us_n + us_p; + us_extra = 0; + + vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ + vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ + vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ + vus_pipe = vus_m + vus_n + vus_p; + + if(video_enable) { + video_drain_rate = pclk_freq * 4; /* MB/s */ + crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ + + vpagemiss = 1; /* self generating page miss */ + vpagemiss += 1; /* One higher priority before */ + + crtpagemiss = 2; /* self generating page miss */ + if(mp_enable) + crtpagemiss += 1; /* if MA0 conflict */ + + vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; + + us_video = vpm_us + vus_m; /* Video has separate read return path */ + + cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; + us_crt = + us_video /* Wait for video */ + +cpm_us /* CRT Page miss */ + +us_m + us_n +us_p /* other latency */ + ; + + clwm = us_crt * crtc_drain_rate/(1000*1000); + clwm++; /* fixed point <= float_point - 1. Fixes that */ + } else { + crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ + + crtpagemiss = 1; /* self generating page miss */ + crtpagemiss += 1; /* MA0 page miss */ + if(mp_enable) + crtpagemiss += 1; /* if MA0 conflict */ + cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; + us_crt = cpm_us + us_m + us_n + us_p ; + clwm = us_crt * crtc_drain_rate/(1000*1000); + clwm++; /* fixed point <= float_point - 1. Fixes that */ + + /* + // + // Another concern, only for high pclks so don't do this + // with video: + // What happens if the latency to fetch the cbs is so large that + // fifo empties. In that case we need to have an alternate clwm value + // based off the total burst fetch + // + us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; + us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; + clwm_mt = us_crt * crtc_drain_rate/(1000*1000); + clwm_mt ++; + if(clwm_mt > clwm) + clwm = clwm_mt; + */ + /* Finally, a heuristic check when width == 64 bits */ + if(width == 1){ + nvclk_fill = nvclk_freq * 8; + if(crtc_drain_rate * 100 >= nvclk_fill * 102) + clwm = 0xfff; /*Large number to fail */ + + else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { + clwm = 1024; + cbs = 512; + us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; + } + } + } + + + /* + Overfill check: + + */ + + clwm_rnd_down = ((int)clwm/8)*8; + if (clwm_rnd_down < clwm) + clwm += 8; + + m1 = clwm + cbs - 1024; /* Amount of overfill */ + m2us = us_pipe_min + us_min_mclk_extra; + pclks_2_top_fifo = (1024-clwm)/(8*width); + + /* pclk cycles to drain */ + p1clk = m2us * pclk_freq/(1000*1000); + p2 = p1clk * bpp / 8; /* bytes drained. */ + + if((p2 < m1) && (m1 > 0)) { + fifo->valid = 0; + found = 0; + if(min_mclk_extra == 0) { + if(cbs <= 32) { + found = 1; /* Can't adjust anymore! */ + } else { + cbs = cbs/2; /* reduce the burst size */ + } + } else { + min_mclk_extra--; + } + } else { + if (clwm > 1023){ /* Have some margin */ + fifo->valid = 0; + found = 0; + if(min_mclk_extra == 0) + found = 1; /* Can't adjust anymore! */ + else + min_mclk_extra--; + } + } + craw = clwm; + + if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; + data = (int)(clwm); + /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ + fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; + + /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ + fifo->video_lwm = 1024; fifo->video_burst_size = 512; + } +} +static void nv10UpdateArbitrationSettings +( + unsigned VClk, + unsigned pixelDepth, + unsigned *burst, + unsigned *lwm, + RIVA_HW_INST *chip +) +{ + nv10_fifo_info fifo_data; + nv10_sim_state sim_data; + unsigned int M, N, P, pll, MClk, NVClk, cfg1; + + pll = chip->PRAMDAC[0x00000504/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + MClk = (N * chip->CrystalFreqKHz / M) >> P; + pll = chip->PRAMDAC[0x00000500/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + NVClk = (N * chip->CrystalFreqKHz / M) >> P; + cfg1 = chip->PFB[0x00000204/4]; + sim_data.pix_bpp = (char)pixelDepth; + sim_data.enable_video = 0; + sim_data.enable_mp = 0; + sim_data.memory_type = (chip->PFB[0x00000200/4] & 0x01) ? 1 : 0; + sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64; + sim_data.mem_latency = (char)cfg1 & 0x0F; + sim_data.mem_aligned = 1; + sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); + sim_data.gr_during_vid = 0; + sim_data.pclk_khz = VClk; + sim_data.mclk_khz = MClk; + sim_data.nvclk_khz = NVClk; + nv10CalcArbitration(&fifo_data, &sim_data); + if (fifo_data.valid) + { + int b = fifo_data.graphics_burst_size >> 4; + *burst = 0; + while (b >>= 1) (*burst)++; + *lwm = fifo_data.graphics_lwm >> 3; + } +} /****************************************************************************\ * * @@ -781,6 +1093,7 @@ static void nv4UpdateArbitrationSettings static int CalcVClock ( int clockIn, + int double_scan, int *clockOut, int *mOut, int *nOut, @@ -794,18 +1107,23 @@ static int CalcVClock unsigned M, N, P; DeltaOld = 0xFFFFFFFF; + VClk = (unsigned)clockIn; + if (double_scan) + VClk *= 2; + if (chip->CrystalFreqKHz == 14318) { lowM = 8; - highM = 14 - (chip->Architecture == 3); + highM = 14 - (chip->Architecture == NV_ARCH_03); } else { lowM = 7; - highM = 13 - (chip->Architecture == 3); + highM = 13 - (chip->Architecture == NV_ARCH_03); } - highP = 4 - (chip->Architecture == 3); + + highP = 4 - (chip->Architecture == NV_ARCH_03); for (P = 0; P <= highP; P ++) { Freq = VClk << P; @@ -866,10 +1184,12 @@ static void CalcStateExt * Extended RIVA registers. */ pixelDepth = (bpp + 1)/8; - CalcVClock(dotClock, &VClk, &m, &n, &p, chip); + CalcVClock(dotClock, hDisplaySize < 512, /* double scan? */ + &VClk, &m, &n, &p, chip); + switch (chip->Architecture) { - case 3: + case NV_ARCH_03: nv3UpdateArbitrationSettings(VClk, pixelDepth * 8, &(state->arbitration0), @@ -882,11 +1202,10 @@ static void CalcStateExt state->config = ((width + 31)/32) | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) | 0x1000; - state->general = 0x00000100; + state->general = 0x00100100; state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; break; - case 4: - case 5: + case NV_ARCH_04: nv4UpdateArbitrationSettings(VClk, pixelDepth * 8, &(state->arbitration0), @@ -900,6 +1219,20 @@ static void CalcStateExt state->general = bpp == 16 ? 0x00101100 : 0x00100100; state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; break; + case NV_ARCH_10: + nv10UpdateArbitrationSettings(VClk, + pixelDepth * 8, + &(state->arbitration0), + &(state->arbitration1), + chip); + state->cursor0 = 0x00; + state->cursor1 = 0xFC; + state->cursor2 = 0x00000000; + state->pllsel = 0x10000700; + state->config = chip->PFB[0x00000200/4]; + state->general = bpp == 16 ? 0x00101100 : 0x00100100; + state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; + break; } state->vpll = (p << 16) | (n << 8) | m; state->screen = ((hTotal & 0x040) >> 2) @@ -909,7 +1242,7 @@ static void CalcStateExt | ((vTotal & 0x400) >> 10); state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; state->horiz = hTotal < 260 ? 0x00 : 0x01; - state->pixel = (pixelDepth > 2 ? 3 : pixelDepth) | 0x40; + state->pixel = pixelDepth > 2 ? 3 : pixelDepth; state->offset0 = state->offset1 = state->offset2 = @@ -937,6 +1270,31 @@ static void CalcStateExt #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1] +static void UpdateFifoState +( + RIVA_HW_INST *chip +) +{ + int i; + + switch (chip->Architecture) + { + case NV_ARCH_04: + LOAD_FIXED_STATE(nv4,FIFO); + chip->Tri03 = 0L; + chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]); + break; + case NV_ARCH_10: + /* + * Initialize state for the RivaTriangle3D05 routines. + */ + LOAD_FIXED_STATE(nv10tri05,PGRAPH); + LOAD_FIXED_STATE(nv10,FIFO); + chip->Tri03 = 0L; + chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]); + break; + } +} static void LoadStateExt ( RIVA_HW_INST *chip, @@ -944,18 +1302,19 @@ static void LoadStateExt ) { int i; + /* * Load HW fixed function state. */ LOAD_FIXED_STATE(Riva,PMC); LOAD_FIXED_STATE(Riva,PTIMER); - /* - * Make sure frame buffer config gets set before loading PRAMIN. - */ - chip->PFB[0x00000200/4] = state->config; switch (chip->Architecture) { - case 3: + case NV_ARCH_03: + /* + * Make sure frame buffer config gets set before loading PRAMIN. + */ + chip->PFB[0x00000200/4] = state->config; LOAD_FIXED_STATE(nv3,PFIFO); LOAD_FIXED_STATE(nv3,PRAMIN); LOAD_FIXED_STATE(nv3,PGRAPH); @@ -991,8 +1350,11 @@ static void LoadStateExt chip->PGRAPH[0x00000658/4] = state->pitch2; chip->PGRAPH[0x0000065C/4] = state->pitch3; break; - case 4: - case 5: + case NV_ARCH_04: + /* + * Make sure frame buffer config gets set before loading PRAMIN. + */ + chip->PFB[0x00000200/4] = state->config; LOAD_FIXED_STATE(nv4,PFIFO); LOAD_FIXED_STATE(nv4,PRAMIN); LOAD_FIXED_STATE(nv4,PGRAPH); @@ -1030,22 +1392,142 @@ static void LoadStateExt chip->PGRAPH[0x00000678/4] = state->pitch2; chip->PGRAPH[0x0000067C/4] = state->pitch3; break; + case NV_ARCH_10: + LOAD_FIXED_STATE(nv10,PFIFO); + LOAD_FIXED_STATE(nv10,PRAMIN); + LOAD_FIXED_STATE(nv10,PGRAPH); + switch (state->bpp) + { + case 15: + LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); + LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + break; + case 16: + LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); + LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); + chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); + break; + case 24: + case 32: + LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); + LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); + chip->Tri03 = 0L; + break; + case 8: + default: + LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); + LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); + chip->Tri03 = 0L; + break; + } + chip->PGRAPH[0x00000640/4] = state->offset0; + chip->PGRAPH[0x00000644/4] = state->offset1; + chip->PGRAPH[0x00000648/4] = state->offset2; + chip->PGRAPH[0x0000064C/4] = state->offset3; + chip->PGRAPH[0x00000670/4] = state->pitch0; + chip->PGRAPH[0x00000674/4] = state->pitch1; + chip->PGRAPH[0x00000678/4] = state->pitch2; + chip->PGRAPH[0x0000067C/4] = state->pitch3; + chip->PGRAPH[0x00000680/4] = state->pitch3; + chip->PGRAPH[0x00000B00/4] = chip->PFB[0x00000240/4]; + chip->PGRAPH[0x00000B04/4] = chip->PFB[0x00000244/4]; + chip->PGRAPH[0x00000B08/4] = chip->PFB[0x00000248/4]; + chip->PGRAPH[0x00000B0C/4] = chip->PFB[0x0000024C/4]; + chip->PGRAPH[0x00000B10/4] = chip->PFB[0x00000250/4]; + chip->PGRAPH[0x00000B14/4] = chip->PFB[0x00000254/4]; + chip->PGRAPH[0x00000B18/4] = chip->PFB[0x00000258/4]; + chip->PGRAPH[0x00000B1C/4] = chip->PFB[0x0000025C/4]; + chip->PGRAPH[0x00000B20/4] = chip->PFB[0x00000260/4]; + chip->PGRAPH[0x00000B24/4] = chip->PFB[0x00000264/4]; + chip->PGRAPH[0x00000B28/4] = chip->PFB[0x00000268/4]; + chip->PGRAPH[0x00000B2C/4] = chip->PFB[0x0000026C/4]; + chip->PGRAPH[0x00000B30/4] = chip->PFB[0x00000270/4]; + chip->PGRAPH[0x00000B34/4] = chip->PFB[0x00000274/4]; + chip->PGRAPH[0x00000B38/4] = chip->PFB[0x00000278/4]; + chip->PGRAPH[0x00000B3C/4] = chip->PFB[0x0000027C/4]; + chip->PGRAPH[0x00000B40/4] = chip->PFB[0x00000280/4]; + chip->PGRAPH[0x00000B44/4] = chip->PFB[0x00000284/4]; + chip->PGRAPH[0x00000B48/4] = chip->PFB[0x00000288/4]; + chip->PGRAPH[0x00000B4C/4] = chip->PFB[0x0000028C/4]; + chip->PGRAPH[0x00000B50/4] = chip->PFB[0x00000290/4]; + chip->PGRAPH[0x00000B54/4] = chip->PFB[0x00000294/4]; + chip->PGRAPH[0x00000B58/4] = chip->PFB[0x00000298/4]; + chip->PGRAPH[0x00000B5C/4] = chip->PFB[0x0000029C/4]; + chip->PGRAPH[0x00000B60/4] = chip->PFB[0x000002A0/4]; + chip->PGRAPH[0x00000B64/4] = chip->PFB[0x000002A4/4]; + chip->PGRAPH[0x00000B68/4] = chip->PFB[0x000002A8/4]; + chip->PGRAPH[0x00000B6C/4] = chip->PFB[0x000002AC/4]; + chip->PGRAPH[0x00000B70/4] = chip->PFB[0x000002B0/4]; + chip->PGRAPH[0x00000B74/4] = chip->PFB[0x000002B4/4]; + chip->PGRAPH[0x00000B78/4] = chip->PFB[0x000002B8/4]; + chip->PGRAPH[0x00000B7C/4] = chip->PFB[0x000002BC/4]; + chip->PGRAPH[0x00000F40/4] = 0x10000000; + chip->PGRAPH[0x00000F44/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00000040; + chip->PGRAPH[0x00000F54/4] = 0x00000008; + chip->PGRAPH[0x00000F50/4] = 0x00000200; + for (i = 0; i < (3*16); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00000040; + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00000800; + for (i = 0; i < (16*16); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F40/4] = 0x30000000; + chip->PGRAPH[0x00000F44/4] = 0x00000004; + chip->PGRAPH[0x00000F50/4] = 0x00006400; + for (i = 0; i < (59*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00006800; + for (i = 0; i < (47*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00006C00; + for (i = 0; i < (3*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00007000; + for (i = 0; i < (19*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00007400; + for (i = 0; i < (12*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00007800; + for (i = 0; i < (12*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00004400; + for (i = 0; i < (8*4); i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00000000; + for (i = 0; i < 16; i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + chip->PGRAPH[0x00000F50/4] = 0x00000040; + for (i = 0; i < 4; i++) + chip->PGRAPH[0x00000F54/4] = 0x00000000; + break; } -//NOTICE("8"); -// LOAD_FIXED_STATE(Riva,FIFO); /* FIX ME*/ -//NOTICE("9"); + LOAD_FIXED_STATE(Riva,FIFO); + UpdateFifoState(chip); /* * Load HW mode state. */ - outb(0x19, 0x3D4); outb(state->repaint0, 0x3D5); - outb(0x1A, 0x3D4); outb(state->repaint1, 0x3D5); - outb(0x25, 0x3D4); outb(state->screen, 0x3D5); - outb(0x28, 0x3D4); outb(state->pixel, 0x3D5); - outb(0x2D, 0x3D4); outb(state->horiz, 0x3D5); - outb(0x1B, 0x3D4); outb(state->arbitration0, 0x3D5); - outb(0x20, 0x3D4); outb(state->arbitration1, 0x3D5); - outb(0x30, 0x3D4); outb(state->cursor0, 0x3D5); - outb(0x31, 0x3D4); outb(state->cursor1, 0x3D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x19); + VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); + VGA_WR08(chip->PCIO, 0x03D4, 0x1A); + VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); + VGA_WR08(chip->PCIO, 0x03D4, 0x25); + VGA_WR08(chip->PCIO, 0x03D5, state->screen); + VGA_WR08(chip->PCIO, 0x03D4, 0x28); + VGA_WR08(chip->PCIO, 0x03D5, state->pixel); + VGA_WR08(chip->PCIO, 0x03D4, 0x2D); + VGA_WR08(chip->PCIO, 0x03D5, state->horiz); + VGA_WR08(chip->PCIO, 0x03D4, 0x1B); + VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); + VGA_WR08(chip->PCIO, 0x03D4, 0x20); + VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); + VGA_WR08(chip->PCIO, 0x03D4, 0x30); + VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); + VGA_WR08(chip->PCIO, 0x03D4, 0x31); + VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); chip->PRAMDAC[0x00000300/4] = state->cursor2; chip->PRAMDAC[0x00000508/4] = state->vpll; chip->PRAMDAC[0x0000050C/4] = state->pllsel; @@ -1053,8 +1535,8 @@ static void LoadStateExt /* * Turn off VBlank enable and reset. */ -// *(chip->VBLANKENABLE) = 0; /* FIXME*/ -// *(chip->VBLANK) = chip->VBlankBit; /*FIXME*/ + *(chip->VBLANKENABLE) = 0; + *(chip->VBLANK) = chip->VBlankBit; /* * Set interrupt enable. */ @@ -1064,9 +1546,11 @@ static void LoadStateExt */ chip->CurrentState = state; /* - * Reset FIFO free count. + * Reset FIFO free and empty counts. */ - chip->FifoFreeCount = 0; + chip->FifoFreeCount = 0; + /* Free count from first subchannel */ + chip->FifoEmptyCount = chip->Rop->FifoFree; } static void UnloadStateExt ( @@ -1077,44 +1561,62 @@ static void UnloadStateExt /* * Save current HW state. */ - outb(0x19, 0x3D4); state->repaint0 = inb(0x3D5); - outb(0x1A, 0x3D4); state->repaint1 = inb(0x3D5); - outb(0x25, 0x3D4); state->screen = inb(0x3D5); - outb(0x28, 0x3D4); state->pixel = inb(0x3D5); - outb(0x2D, 0x3D4); state->horiz = inb(0x3D5); - outb(0x1B, 0x3D4); state->arbitration0 = inb(0x3D5); - outb(0x20, 0x3D4); state->arbitration1 = inb(0x3D5); - outb(0x30, 0x3D4); state->cursor0 = inb(0x3D5); - outb(0x31, 0x3D4); state->cursor1 = inb(0x3D5); - state->cursor2 = chip->PRAMDAC[0x00000300/4]; - state->vpll = chip->PRAMDAC[0x00000508/4]; - state->pllsel = chip->PRAMDAC[0x0000050C/4]; - state->general = chip->PRAMDAC[0x00000600/4]; - state->config = chip->PFB[0x00000200/4]; - switch (chip->Architecture) - { - case 3: - state->offset0 = chip->PGRAPH[0x00000630/4]; - state->offset1 = chip->PGRAPH[0x00000634/4]; - state->offset2 = chip->PGRAPH[0x00000638/4]; - state->offset3 = chip->PGRAPH[0x0000063C/4]; - state->pitch0 = chip->PGRAPH[0x00000650/4]; - state->pitch1 = chip->PGRAPH[0x00000654/4]; - state->pitch2 = chip->PGRAPH[0x00000658/4]; - state->pitch3 = chip->PGRAPH[0x0000065C/4]; - break; - case 4: - case 5: - state->offset0 = chip->PGRAPH[0x00000640/4]; - state->offset1 = chip->PGRAPH[0x00000644/4]; - state->offset2 = chip->PGRAPH[0x00000648/4]; - state->offset3 = chip->PGRAPH[0x0000064C/4]; - state->pitch0 = chip->PGRAPH[0x00000670/4]; - state->pitch1 = chip->PGRAPH[0x00000674/4]; - state->pitch2 = chip->PGRAPH[0x00000678/4]; - state->pitch3 = chip->PGRAPH[0x0000067C/4]; - break; - } + VGA_WR08(chip->PCIO, 0x03D4, 0x19); + state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x1A); + state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x25); + state->screen = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x28); + state->pixel = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x2D); + state->horiz = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x1B); + state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x20); + state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x30); + state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); + VGA_WR08(chip->PCIO, 0x03D4, 0x31); + state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); + state->cursor2 = chip->PRAMDAC[0x00000300/4]; + state->vpll = chip->PRAMDAC[0x00000508/4]; + state->pllsel = chip->PRAMDAC[0x0000050C/4]; + state->general = chip->PRAMDAC[0x00000600/4]; + state->config = chip->PFB[0x00000200/4]; + switch (chip->Architecture) + { + case NV_ARCH_03: + state->offset0 = chip->PGRAPH[0x00000630/4]; + state->offset1 = chip->PGRAPH[0x00000634/4]; + state->offset2 = chip->PGRAPH[0x00000638/4]; + state->offset3 = chip->PGRAPH[0x0000063C/4]; + state->pitch0 = chip->PGRAPH[0x00000650/4]; + state->pitch1 = chip->PGRAPH[0x00000654/4]; + state->pitch2 = chip->PGRAPH[0x00000658/4]; + state->pitch3 = chip->PGRAPH[0x0000065C/4]; + break; + case NV_ARCH_04: + state->offset0 = chip->PGRAPH[0x00000640/4]; + state->offset1 = chip->PGRAPH[0x00000644/4]; + state->offset2 = chip->PGRAPH[0x00000648/4]; + state->offset3 = chip->PGRAPH[0x0000064C/4]; + state->pitch0 = chip->PGRAPH[0x00000670/4]; + state->pitch1 = chip->PGRAPH[0x00000674/4]; + state->pitch2 = chip->PGRAPH[0x00000678/4]; + state->pitch3 = chip->PGRAPH[0x0000067C/4]; + break; + case NV_ARCH_10: + state->offset0 = chip->PGRAPH[0x00000640/4]; + state->offset1 = chip->PGRAPH[0x00000644/4]; + state->offset2 = chip->PGRAPH[0x00000648/4]; + state->offset3 = chip->PGRAPH[0x0000064C/4]; + state->pitch0 = chip->PGRAPH[0x00000670/4]; + state->pitch1 = chip->PGRAPH[0x00000674/4]; + state->pitch2 = chip->PGRAPH[0x00000678/4]; + state->pitch3 = chip->PGRAPH[0x0000067C/4]; + break; + } } static void SetStartAddress ( @@ -1129,24 +1631,24 @@ static void SetStartAddress /* * Unlock extended registers. */ - outb(chip->LockUnlockIndex, chip->LockUnlockIO); - outb(0x57, chip->LockUnlockIO + 1); + chip->LockUnlock(chip, 0); /* * Set start address. */ - outb(0x0D, 0x3D4); - outb(offset, 0x3D5); - outb(0x0C, 0x3D4); - outb(offset >> 8, 0x3D5); - outb(0x19, 0x3D4); - tmp = inb(0x3D5); - outb(((offset >> 16) & 0x0F) | (tmp & 0xF0), 0x3D5); + VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); + offset >>= 8; + VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); + offset >>= 8; + VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); + VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); + VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); + VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); /* * 4 pixel pan register. */ - offset = inb(chip->IO + 0x0A); - outb(0x13, 0x3C0); - outb(pan, 0x3C0); + offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); + VGA_WR08(chip->PCIO, 0x3C0, 0x13); + VGA_WR08(chip->PCIO, 0x3C0, pan); } static void nv3SetSurfaces2D ( @@ -1155,9 +1657,14 @@ static void nv3SetSurfaces2D unsigned surf1 ) { - while (nv3Busy(chip)); - chip->PGRAPH[0x00000630/4] = surf0; - chip->PGRAPH[0x00000634/4] = surf1; + RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); + + RIVA_FIFO_FREE(*chip,Tri03,5); + chip->FIFO[0x00003800] = 0x80000003; + Surface->Offset = surf0; + chip->FIFO[0x00003800] = 0x80000004; + Surface->Offset = surf1; + chip->FIFO[0x00003800] = 0x80000013; } static void nv4SetSurfaces2D ( @@ -1166,9 +1673,28 @@ static void nv4SetSurfaces2D unsigned surf1 ) { - while (nv4Busy(chip)); - chip->PGRAPH[0x00000640/4] = surf0; - chip->PGRAPH[0x00000644/4] = surf1; + RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); + + chip->FIFO[0x00003800] = 0x80000003; + Surface->Offset = surf0; + chip->FIFO[0x00003800] = 0x80000004; + Surface->Offset = surf1; + chip->FIFO[0x00003800] = 0x80000014; +} +static void nv10SetSurfaces2D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); + + chip->FIFO[0x00003800] = 0x80000003; + Surface->Offset = surf0; + chip->FIFO[0x00003800] = 0x80000004; + Surface->Offset = surf1; + chip->FIFO[0x00003800] = 0x80000014; } static void nv3SetSurfaces3D ( @@ -1177,9 +1703,14 @@ static void nv3SetSurfaces3D unsigned surf1 ) { - while (nv3Busy(chip)); - chip->PGRAPH[0x00000638/4] = surf0; - chip->PGRAPH[0x0000063C/4] = surf1; + RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); + + RIVA_FIFO_FREE(*chip,Tri03,5); + chip->FIFO[0x00003800] = 0x80000005; + Surface->Offset = surf0; + chip->FIFO[0x00003800] = 0x80000006; + Surface->Offset = surf1; + chip->FIFO[0x00003800] = 0x80000013; } static void nv4SetSurfaces3D ( @@ -1188,9 +1719,28 @@ static void nv4SetSurfaces3D unsigned surf1 ) { - while (nv4Busy(chip)); - chip->PGRAPH[0x00000648/4] = surf0; - chip->PGRAPH[0x0000064C/4] = surf1; + RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); + + chip->FIFO[0x00003800] = 0x80000005; + Surface->Offset = surf0; + chip->FIFO[0x00003800] = 0x80000006; + Surface->Offset = surf1; + chip->FIFO[0x00003800] = 0x80000014; +} +static void nv10SetSurfaces3D +( + RIVA_HW_INST *chip, + unsigned surf0, + unsigned surf1 +) +{ + RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]); + + RIVA_FIFO_FREE(*chip,Tri03,4); + chip->FIFO[0x00003800] = 0x80000007; + Surfaces3D->RenderBufferOffset = surf0; + Surfaces3D->ZBufferOffset = surf1; + chip->FIFO[0x00003800] = 0x80000014; } /****************************************************************************\ @@ -1199,7 +1749,7 @@ static void nv4SetSurfaces3D * * \****************************************************************************/ -void nv3GetConfig +static void nv3GetConfig ( RIVA_HW_INST *chip ) @@ -1219,20 +1769,20 @@ void nv3GetConfig switch (chip->PFB[0x00000000/4] & 0x03) { case 2: - chip->RamAmountKBytes = 1024 * 4 - 32; + chip->RamAmountKBytes = 1024 * 4; break; case 1: - chip->RamAmountKBytes = 1024 * 2 - 32; + chip->RamAmountKBytes = 1024 * 2; break; default: - chip->RamAmountKBytes = 1024 * 8 - 32; + chip->RamAmountKBytes = 1024 * 8; break; } } else { chip->RamBandwidthKBytesPerSec = 1000000; - chip->RamAmountKBytes = 1024 * 8 - 32; + chip->RamAmountKBytes = 1024 * 8; } } else @@ -1244,13 +1794,13 @@ void nv3GetConfig switch (chip->PFB[0x00000000/4] & 0x00000003) { case 0: - chip->RamAmountKBytes = 1024 * 8 - 32; + chip->RamAmountKBytes = 1024 * 8; break; case 2: - chip->RamAmountKBytes = 1024 * 4 - 32; + chip->RamAmountKBytes = 1024 * 4; break; default: - chip->RamAmountKBytes = 1024 * 2 - 32; + chip->RamAmountKBytes = 1024 * 2; break; } } @@ -1260,9 +1810,7 @@ void nv3GetConfig chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]); chip->VBLANK = &(chip->PGRAPH[0x0100/4]); chip->VBlankBit = 0x00000100; - chip->MaxVClockFreqKHz = 230000; - chip->LockUnlockIO = 0x3C4; - chip->LockUnlockIndex = 0x06; + chip->MaxVClockFreqKHz = 256000; /* * Set chip functions. */ @@ -1274,9 +1822,9 @@ void nv3GetConfig chip->SetStartAddress = SetStartAddress; chip->SetSurfaces2D = nv3SetSurfaces2D; chip->SetSurfaces3D = nv3SetSurfaces3D; + chip->LockUnlock = nv3LockUnlock; } - -void nv4GetConfig +static void nv4GetConfig ( RIVA_HW_INST *chip ) @@ -1284,21 +1832,29 @@ void nv4GetConfig /* * Fill in chip configuration. */ - switch (chip->PFB[0x00000000/4] & 0x00000003) + if (chip->PFB[0x00000000/4] & 0x00000100) { - case 0: - chip->RamAmountKBytes = 1024 * 32 - 128; - break; - case 1: - chip->RamAmountKBytes = 1024 * 4 - 128; - break; - case 2: - chip->RamAmountKBytes = 1024 * 8 - 128; - break; - case 3: - default: - chip->RamAmountKBytes = 1024 * 16 - 128; - break; + chip->RamAmountKBytes = ((chip->PFB[0x00000000/4] >> 12) & 0x0F) * 1024 * 2 + + 1024 * 2; + } + else + { + switch (chip->PFB[0x00000000/4] & 0x00000003) + { + case 0: + chip->RamAmountKBytes = 1024 * 32; + break; + case 1: + chip->RamAmountKBytes = 1024 * 4; + break; + case 2: + chip->RamAmountKBytes = 1024 * 8; + break; + case 3: + default: + chip->RamAmountKBytes = 1024 * 16; + break; + } } switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) { @@ -1315,9 +1871,7 @@ void nv4GetConfig chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); chip->VBLANK = &(chip->PCRTC[0x0100/4]); chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 250000; - chip->LockUnlockIO = 0x3D4; - chip->LockUnlockIndex = 0x1F; + chip->MaxVClockFreqKHz = 350000; /* * Set chip functions. */ @@ -1329,9 +1883,9 @@ void nv4GetConfig chip->SetStartAddress = SetStartAddress; chip->SetSurfaces2D = nv4SetSurfaces2D; chip->SetSurfaces3D = nv4SetSurfaces3D; + chip->LockUnlock = nv4LockUnlock; } - -void nv5GetConfig +static void nv10GetConfig ( RIVA_HW_INST *chip ) @@ -1339,20 +1893,31 @@ void nv5GetConfig /* * Fill in chip configuration. */ - switch (chip->PFB[0x00000000/4] & 0x00000003) + switch ((chip->PFB[0x0000020C/4] >> 20) & 0x000000FF) { - case 0: - chip->RamAmountKBytes = 1024 * 32 - 128; + case 0x02: + chip->RamAmountKBytes = 1024 * 2; break; - case 1: - chip->RamAmountKBytes = 1024 * 4 - 128; + case 0x04: + chip->RamAmountKBytes = 1024 * 4; break; - case 2: - chip->RamAmountKBytes = 1024 * 8 - 128; + case 0x08: + chip->RamAmountKBytes = 1024 * 8; + break; + case 0x10: + chip->RamAmountKBytes = 1024 * 16; + break; + case 0x20: + chip->RamAmountKBytes = 1024 * 32; + break; + case 0x40: + chip->RamAmountKBytes = 1024 * 64; + break; + case 0x80: + chip->RamAmountKBytes = 1024 * 128; break; - case 3: default: - chip->RamAmountKBytes = 1024 * 16 - 128; + chip->RamAmountKBytes = 1024 * 16; break; } switch ((chip->PFB[0x00000000/4] >> 3) & 0x00000003) @@ -1370,22 +1935,20 @@ void nv5GetConfig chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); chip->VBLANK = &(chip->PCRTC[0x0100/4]); chip->VBlankBit = 0x00000001; - chip->MaxVClockFreqKHz = 250000; - chip->LockUnlockIO = 0x3D4; - chip->LockUnlockIndex = 0x1F; + chip->MaxVClockFreqKHz = 350000; /* * Set chip functions. */ - chip->Busy = nv4Busy; + chip->Busy = nv10Busy; chip->ShowHideCursor = ShowHideCursor; chip->CalcStateExt = CalcStateExt; chip->LoadStateExt = LoadStateExt; chip->UnloadStateExt = UnloadStateExt; chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; + chip->SetSurfaces2D = nv10SetSurfaces2D; + chip->SetSurfaces3D = nv10SetSurfaces3D; + chip->LockUnlock = nv10LockUnlock; } - int RivaGetConfig ( RIVA_HW_INST *chip @@ -1400,14 +1963,15 @@ int RivaGetConfig */ switch (chip->Architecture) { - case 3: + case NV_ARCH_03: nv3GetConfig(chip); break; - case 4: + case NV_ARCH_04: nv4GetConfig(chip); break; - case 5: - nv5GetConfig(chip); + case NV_ARCH_10: + nv10GetConfig(chip); + break; default: return (-1); } @@ -1420,6 +1984,7 @@ int RivaGetConfig chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]); chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]); chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]); + chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]); chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); return (0); } diff --git a/drivers/video/riva/riva_hw.h b/drivers/video/riva/riva_hw.h index 6ab8395e5..da27e20a3 100644 --- a/drivers/video/riva/riva_hw.h +++ b/drivers/video/riva/riva_hw.h @@ -1,6 +1,6 @@ /***************************************************************************\ |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |* international laws. Users and possessors of this source code are *| @@ -11,7 +11,7 @@ |* tion and internal comments to the code, notices to the end user *| |* as follows: *| |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| @@ -36,18 +36,44 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of + +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.h,v 1.1.2.2 1998/12/22 16:33:19 hohndel Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.6 2000/02/08 17:19:12 dawes Exp $ */ #ifndef __RIVA_HW_H__ #define __RIVA_HW_H__ -#define RIVA_SW_VERSION 0x00010000 +#define RIVA_SW_VERSION 0x00010003 +/* + * Typedefs to force certain sized values. + */ +typedef unsigned char U008; +typedef unsigned short U016; +typedef unsigned int U032; + +/* + * HW access macros. + */ +#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d)) +#define NV_RD08(p,i) (((U008 *)(p))[i]) +#define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d)) +#define NV_RD16(p,i) (((U016 *)(p))[(i)/2]) +#define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d)) +#define NV_RD32(p,i) (((U032 *)(p))[(i)/4]) +#define VGA_WR08(p,i,d) NV_WR08(p,i,d) +#define VGA_RD08(p,i) NV_RD08(p,i) + +/* + * Define supported architectures. + */ +#define NV_ARCH_03 0x03 +#define NV_ARCH_04 0x04 +#define NV_ARCH_10 0x10 /***************************************************************************\ * * * FIFO registers. * @@ -59,161 +85,165 @@ */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned Rop3; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BB]; + U032 Rop3; } RivaRop; /* * 8X8 Monochrome pattern. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BD]; - unsigned Shape; - unsigned reserved03[0x001]; - unsigned Color0; - unsigned Color1; - unsigned Monochrome[2]; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BD]; + U032 Shape; + U032 reserved03[0x001]; + U032 Color0; + U032 Color1; + U032 Monochrome[2]; } RivaPattern; /* * Scissor clip rectangle. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned TopLeft; - unsigned WidthHeight; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BB]; + U032 TopLeft; + U032 WidthHeight; } RivaClip; /* * 2D filled rectangle. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop[1]; - unsigned reserved01[0x0BC]; - unsigned Color; - unsigned reserved03[0x03E]; - unsigned TopLeft; - unsigned WidthHeight; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop[1]; + U032 reserved01[0x0BC]; + U032 Color; + U032 reserved03[0x03E]; + U032 TopLeft; + U032 WidthHeight; } RivaRectangle; /* * 2D screen-screen BLT. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned TopLeftSrc; - unsigned TopLeftDst; - unsigned WidthHeight; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BB]; + U032 TopLeftSrc; + U032 TopLeftDst; + U032 WidthHeight; } RivaScreenBlt; /* * 2D pixel BLT. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop[1]; - unsigned reserved01[0x0BC]; - unsigned TopLeft; - unsigned WidthHeight; - unsigned WidthHeightIn; - unsigned reserved02[0x03C]; - unsigned Pixels; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop[1]; + U032 reserved01[0x0BC]; + U032 TopLeft; + U032 WidthHeight; + U032 WidthHeightIn; + U032 reserved02[0x03C]; + U032 Pixels; } RivaPixmap; /* * Filled rectangle combined with monochrome expand. Useful for glyphs. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BB]; - unsigned reserved03[(0x040)-1]; - unsigned Color1A; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BB]; + U032 reserved03[(0x040)-1]; + U032 Color1A; struct { - unsigned TopLeft; - unsigned WidthHeight; + U032 TopLeft; + U032 WidthHeight; } UnclippedRectangle[64]; - unsigned reserved04[(0x080)-3]; + U032 reserved04[(0x080)-3]; struct { - unsigned TopLeft; - unsigned BottomRight; + U032 TopLeft; + U032 BottomRight; } ClipB; - unsigned Color1B; + U032 Color1B; struct { - unsigned TopLeft; - unsigned BottomRight; + U032 TopLeft; + U032 BottomRight; } ClippedRectangle[64]; - unsigned reserved05[(0x080)-5]; + U032 reserved05[(0x080)-5]; struct { - unsigned TopLeft; - unsigned BottomRight; + U032 TopLeft; + U032 BottomRight; } ClipC; - unsigned Color1C; - unsigned WidthHeightC; - unsigned PointC; - unsigned MonochromeData1C; - unsigned reserved06[(0x080)+121]; + U032 Color1C; + U032 WidthHeightC; + U032 PointC; + U032 MonochromeData1C; + U032 reserved06[(0x080)+121]; struct { - unsigned TopLeft; - unsigned BottomRight; + U032 TopLeft; + U032 BottomRight; } ClipD; - unsigned Color1D; - unsigned WidthHeightInD; - unsigned WidthHeightOutD; - unsigned PointD; - unsigned MonochromeData1D; - unsigned reserved07[(0x080)+120]; + U032 Color1D; + U032 WidthHeightInD; + U032 WidthHeightOutD; + U032 PointD; + U032 MonochromeData1D; + U032 reserved07[(0x080)+120]; struct { - unsigned TopLeft; - unsigned BottomRight; + U032 TopLeft; + U032 BottomRight; } ClipE; - unsigned Color0E; - unsigned Color1E; - unsigned WidthHeightInE; - unsigned WidthHeightOutE; - unsigned PointE; - unsigned MonochromeData01E; + U032 Color0E; + U032 Color1E; + U032 WidthHeightInE; + U032 WidthHeightOutE; + U032 PointE; + U032 MonochromeData01E; } RivaBitmap; /* * 3D textured, Z buffered triangle. */ typedef volatile struct { - unsigned reserved00[4]; - unsigned short FifoFree; - unsigned short Nop; - unsigned reserved01[0x0BC]; - unsigned TextureOffset; - unsigned TextureFormat; - unsigned TextureFilter; - unsigned FogColor; - unsigned Control; - unsigned AlphaTest; - unsigned reserved02[0x339]; - unsigned FogAndIndex; - unsigned Color; + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BC]; + U032 TextureOffset; + U032 TextureFormat; + U032 TextureFilter; + U032 FogColor; +/* This is a problem on LynxOS */ +#ifdef Control +#undef Control +#endif + U032 Control; + U032 AlphaTest; + U032 reserved02[0x339]; + U032 FogAndIndex; + U032 Color; float ScreenX; float ScreenY; float ScreenZ; @@ -221,7 +251,90 @@ typedef volatile struct float TextureS; float TextureT; } RivaTexturedTriangle03; - +typedef volatile struct +{ + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BB]; + U032 ColorKey; + U032 TextureOffset; + U032 TextureFormat; + U032 TextureFilter; + U032 Blend; +/* This is a problem on LynxOS */ +#ifdef Control +#undef Control +#endif + U032 Control; + U032 FogColor; + U032 reserved02[0x39]; + struct + { + float ScreenX; + float ScreenY; + float ScreenZ; + float EyeM; + U032 Color; + U032 Specular; + float TextureS; + float TextureT; + } Vertex[16]; + U032 DrawTriangle3D; +} RivaTexturedTriangle05; +/* + * 2D line. + */ +typedef volatile struct +{ + U032 reserved00[4]; + U016 FifoFree; + U016 Nop[1]; + U032 reserved01[0x0BC]; + U032 Color; /* source color 0304-0307*/ + U032 Reserved02[0x03e]; + struct { /* start aliased methods in array 0400- */ + U032 point0; /* y_x S16_S16 in pixels 0- 3*/ + U032 point1; /* y_x S16_S16 in pixels 4- 7*/ + } Lin[16]; /* end of aliased methods in array -047f*/ + struct { /* start aliased methods in array 0480- */ + U032 point0X; /* in pixels, 0 at left 0- 3*/ + U032 point0Y; /* in pixels, 0 at top 4- 7*/ + U032 point1X; /* in pixels, 0 at left 8- b*/ + U032 point1Y; /* in pixels, 0 at top c- f*/ + } Lin32[8]; /* end of aliased methods in array -04ff*/ + U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/ + struct { /* start aliased methods in array 0580- */ + U032 x; /* in pixels, 0 at left 0- 3*/ + U032 y; /* in pixels, 0 at top 4- 7*/ + } PolyLin32[16]; /* end of aliased methods in array -05ff*/ + struct { /* start aliased methods in array 0600- */ + U032 color; /* source color 0- 3*/ + U032 point; /* y_x S16_S16 in pixels 4- 7*/ + } ColorPolyLin[16]; /* end of aliased methods in array -067f*/ +} RivaLine; +/* + * 2D/3D surfaces + */ +typedef volatile struct +{ + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BE]; + U032 Offset; +} RivaSurface; +typedef volatile struct +{ + U032 reserved00[4]; + U016 FifoFree; + U016 Nop; + U032 reserved01[0x0BD]; + U032 Pitch; + U032 RenderBufferOffset; + U032 ZBufferOffset; +} RivaSurface3D; + /***************************************************************************\ * * * Virtualized RIVA H/W interface. * @@ -238,35 +351,37 @@ typedef struct _riva_hw_inst /* * Chip specific settings. */ - unsigned Architecture; - unsigned Version; - unsigned CrystalFreqKHz; - unsigned RamAmountKBytes; - unsigned MaxVClockFreqKHz; - unsigned RamBandwidthKBytesPerSec; - unsigned EnableIRQ; - unsigned IO; - unsigned LockUnlockIO; - unsigned LockUnlockIndex; - unsigned VBlankBit; - unsigned FifoFreeCount; + U032 Architecture; + U032 Version; + U032 CrystalFreqKHz; + U032 RamAmountKBytes; + U032 MaxVClockFreqKHz; + U032 RamBandwidthKBytesPerSec; + U032 EnableIRQ; + U032 IO; + U032 VBlankBit; + U032 FifoFreeCount; + U032 FifoEmptyCount; /* * Non-FIFO registers. */ - volatile unsigned *PCRTC; - volatile unsigned *PRAMDAC; - volatile unsigned *PFB; - volatile unsigned *PFIFO; - volatile unsigned *PGRAPH; - volatile unsigned *PEXTDEV; - volatile unsigned *PTIMER; - volatile unsigned *PMC; - volatile unsigned *PRAMIN; - volatile unsigned *FIFO; - volatile unsigned *CURSOR; - volatile unsigned *CURSORPOS; - volatile unsigned *VBLANKENABLE; - volatile unsigned *VBLANK; + volatile U032 *PCRTC; + volatile U032 *PRAMDAC; + volatile U032 *PFB; + volatile U032 *PFIFO; + volatile U032 *PGRAPH; + volatile U032 *PEXTDEV; + volatile U032 *PTIMER; + volatile U032 *PMC; + volatile U032 *PRAMIN; + volatile U032 *FIFO; + volatile U032 *CURSOR; + volatile U032 *CURSORPOS; + volatile U032 *VBLANKENABLE; + volatile U032 *VBLANK; + volatile U008 *PCIO; + volatile U008 *PVIO; + volatile U008 *PDIO; /* * Common chip functions. */ @@ -274,10 +389,11 @@ typedef struct _riva_hw_inst void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int); void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); - void (*SetStartAddress)(struct _riva_hw_inst *,unsigned); - void (*SetSurfaces2D)(struct _riva_hw_inst *,unsigned,unsigned); - void (*SetSurfaces3D)(struct _riva_hw_inst *,unsigned,unsigned); + void (*SetStartAddress)(struct _riva_hw_inst *,U032); + void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); + void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); int (*ShowHideCursor)(struct _riva_hw_inst *,int); + void (*LockUnlock)(struct _riva_hw_inst *, int); /* * Current extended mode settings. */ @@ -291,38 +407,40 @@ typedef struct _riva_hw_inst RivaPixmap *Pixmap; RivaScreenBlt *Blt; RivaBitmap *Bitmap; + RivaLine *Line; RivaTexturedTriangle03 *Tri03; + RivaTexturedTriangle05 *Tri05; } RIVA_HW_INST; /* * Extended mode state information. */ typedef struct _riva_hw_state { - unsigned bpp; - unsigned width; - unsigned height; - unsigned repaint0; - unsigned repaint1; - unsigned screen; - unsigned pixel; - unsigned horiz; - unsigned arbitration0; - unsigned arbitration1; - unsigned vpll; - unsigned pllsel; - unsigned general; - unsigned config; - unsigned cursor0; - unsigned cursor1; - unsigned cursor2; - unsigned offset0; - unsigned offset1; - unsigned offset2; - unsigned offset3; - unsigned pitch0; - unsigned pitch1; - unsigned pitch2; - unsigned pitch3; + U032 bpp; + U032 width; + U032 height; + U032 repaint0; + U032 repaint1; + U032 screen; + U032 pixel; + U032 horiz; + U032 arbitration0; + U032 arbitration1; + U032 vpll; + U032 pllsel; + U032 general; + U032 config; + U032 cursor0; + U032 cursor1; + U032 cursor2; + U032 offset0; + U032 offset1; + U032 offset2; + U032 offset3; + U032 pitch0; + U032 pitch1; + U032 pitch2; + U032 pitch3; } RIVA_HW_STATE; /* * External routines. @@ -331,13 +449,12 @@ int RivaGetConfig(RIVA_HW_INST *); /* * FIFO Free Count. Should attempt to yield processor if RIVA is busy. */ -#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ -{ \ -while ((hwinst).FifoFreeCount < (cnt)) \ -{ \ - (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ -} \ -(hwinst).FifoFreeCount -= (cnt); \ + +#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ +{ \ + while ((hwinst).FifoFreeCount < (cnt)) \ + (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ + (hwinst).FifoFreeCount -= (cnt); \ } #endif /* __RIVA_HW_H__ */ diff --git a/drivers/video/riva/riva_tbl.h b/drivers/video/riva/riva_tbl.h index 23e7cb75b..6760b28a2 100644 --- a/drivers/video/riva/riva_tbl.h +++ b/drivers/video/riva/riva_tbl.h @@ -1,6 +1,6 @@ /***************************************************************************\ |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NOTICE TO USER: The source code is copyrighted under U.S. and *| |* international laws. Users and possessors of this source code are *| @@ -11,7 +11,7 @@ |* tion and internal comments to the code, notices to the end user *| |* as follows: *| |* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| +|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| |* *| |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| @@ -36,14 +36,15 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of + +/* + * GPL licensing note -- nVidia is allowing a liberal interpretation of * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 + * copyright and disclaimer should be included with all code derived + * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_tbl.h,v 1.1.2.2 1998/12/22 16:33:20 hohndel Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.5 2000/02/08 17:19:12 dawes Exp $ */ /* * RIVA Fixed Functionality Init Tables. */ @@ -60,8 +61,6 @@ static unsigned RivaTablePTIMER[][2] = {0x00000050, 0x00000000}, {0x00000040, 0xFFFFFFFF} }; - -#if 0 static unsigned RivaTableFIFO[][2] = { {0x00000000, 0x80000000}, @@ -72,8 +71,6 @@ static unsigned RivaTableFIFO[][2] = {0x00002800, 0x80000012}, {0x00003800, 0x80000013} }; -#endif - static unsigned nv3TablePFIFO[][2] = { {0x00000140, 0x00000000}, @@ -161,6 +158,14 @@ static unsigned nv3TablePRAMIN[][2] = {0x00000205, 0x00C50342}, {0x00000208, 0x80000002}, {0x00000209, 0x00C60343}, + {0x0000020C, 0x80000003}, + {0x0000020D, 0x00DC0348}, + {0x00000210, 0x80000004}, + {0x00000211, 0x00DC0349}, + {0x00000214, 0x80000005}, + {0x00000215, 0x00DC034A}, + {0x00000218, 0x80000006}, + {0x00000219, 0x00DC034B}, {0x00000240, 0x80000010}, {0x00000241, 0x00D10344}, {0x00000244, 0x80000011}, @@ -189,13 +194,31 @@ static unsigned nv3TablePRAMIN[][2] = {0x00000D1B, 0x00000000}, {0x00000D1D, 0x00000140}, {0x00000D1E, 0x00000000}, - {0x00000D1F, 0x00000000} + {0x00000D1F, 0x00000000}, + {0x00000D20, 0x10100200}, + {0x00000D21, 0x00000000}, + {0x00000D22, 0x00000000}, + {0x00000D23, 0x00000000}, + {0x00000D24, 0x10210200}, + {0x00000D25, 0x00000000}, + {0x00000D26, 0x00000000}, + {0x00000D27, 0x00000000}, + {0x00000D28, 0x10420200}, + {0x00000D29, 0x00000000}, + {0x00000D2A, 0x00000000}, + {0x00000D2B, 0x00000000}, + {0x00000D2C, 0x10830200}, + {0x00000D2D, 0x00000000}, + {0x00000D2E, 0x00000000}, + {0x00000D2F, 0x00000000} }; static unsigned nv3TablePRAMIN_8BPP[][2] = { + /* 0xXXXXX3XX For MSB mono format */ + /* 0xXXXXX2XX For LSB mono format */ {0x00000D04, 0x10110203}, {0x00000D08, 0x10110203}, - {0x00000D0C, 0x10110203}, + {0x00000D0C, 0x1011020B}, {0x00000D10, 0x10118203}, {0x00000D14, 0x10110203}, {0x00000D18, 0x10110203}, @@ -203,9 +226,11 @@ static unsigned nv3TablePRAMIN_8BPP[][2] = }; static unsigned nv3TablePRAMIN_15BPP[][2] = { + /* 0xXXXXX2XX For MSB mono format */ + /* 0xXXXXX3XX For LSB mono format */ {0x00000D04, 0x10110200}, {0x00000D08, 0x10110200}, - {0x00000D0C, 0x10110200}, + {0x00000D0C, 0x10110208}, {0x00000D10, 0x10118200}, {0x00000D14, 0x10110200}, {0x00000D18, 0x10110200}, @@ -213,19 +238,27 @@ static unsigned nv3TablePRAMIN_15BPP[][2] = }; static unsigned nv3TablePRAMIN_32BPP[][2] = { + /* 0xXXXXX3XX For MSB mono format */ + /* 0xXXXXX2XX For LSB mono format */ {0x00000D04, 0x10110201}, {0x00000D08, 0x10110201}, - {0x00000D0C, 0x10110201}, + {0x00000D0C, 0x10110209}, {0x00000D10, 0x10118201}, {0x00000D14, 0x10110201}, {0x00000D18, 0x10110201}, {0x00000D1C, 0x10419208} }; +static unsigned nv4TableFIFO[][2] = +{ + {0x00003800, 0x80000014} +}; static unsigned nv4TablePFIFO[][2] = { {0x00000140, 0x00000000}, {0x00000480, 0x00000000}, {0x00000494, 0x00000000}, + {0x00000481, 0x00000000}, + {0x0000048B, 0x00000000}, {0x00000400, 0x00000000}, {0x00000414, 0x00000000}, {0x00000084, 0x03000100}, @@ -284,45 +317,44 @@ static unsigned nv4TablePGRAPH[][2] = {0x0000005A, 0x00000000}, {0x0000005B, 0x00000000}, {0x00000196, 0x00000000}, - {0x000001A1, 0x00FFFFFF}, + {0x000001A1, 0x01FFFFFF}, {0x00000197, 0x00000000}, - {0x000001A2, 0x00FFFFFF}, + {0x000001A2, 0x01FFFFFF}, {0x00000198, 0x00000000}, - {0x000001A3, 0x00FFFFFF}, + {0x000001A3, 0x01FFFFFF}, {0x00000199, 0x00000000}, - {0x000001A4, 0x00FFFFFF}, + {0x000001A4, 0x01FFFFFF}, {0x00000050, 0x00000000}, {0x00000040, 0xFFFFFFFF}, {0x0000005C, 0x10010100}, - {0x000001C8, 0x00000001} + {0x000001C4, 0xFFFFFFFF}, + {0x000001C8, 0x00000001}, + {0x00000204, 0x00000000}, + {0x000001C3, 0x00000001} }; static unsigned nv4TablePGRAPH_8BPP[][2] = { - {0x000001C4, 0xFFFFFFFF}, {0x000001C9, 0x00111111}, {0x00000186, 0x00001010}, - {0x0000020C, 0x01010101} + {0x0000020C, 0x03020202} }; static unsigned nv4TablePGRAPH_15BPP[][2] = { - {0x000001C4, 0xFFFFFFFF}, {0x000001C9, 0x00226222}, {0x00000186, 0x00002071}, - {0x0000020C, 0x09090909} + {0x0000020C, 0x09080808} }; static unsigned nv4TablePGRAPH_16BPP[][2] = { - {0x000001C4, 0xFFFFFFFF}, {0x000001C9, 0x00556555}, {0x00000186, 0x000050C2}, - {0x0000020C, 0x0C0C0C0C} + {0x0000020C, 0x0C0B0B0B} }; static unsigned nv4TablePGRAPH_32BPP[][2] = { - {0x000001C4, 0xFFFFFFFF}, {0x000001C9, 0x0077D777}, {0x00000186, 0x000070E5}, - {0x0000020C, 0x07070707} + {0x0000020C, 0x0E0D0D0D} }; static unsigned nv4TablePRAMIN[][2] = { @@ -334,14 +366,26 @@ static unsigned nv4TablePRAMIN[][2] = {0x00000005, 0x80011147}, {0x00000006, 0x80000013}, {0x00000007, 0x80011148}, + {0x00000008, 0x80000014}, + {0x00000009, 0x80011149}, + {0x0000000A, 0x80000015}, + {0x0000000B, 0x8001114A}, {0x00000020, 0x80000000}, {0x00000021, 0x80011142}, {0x00000022, 0x80000001}, {0x00000023, 0x80011143}, {0x00000024, 0x80000002}, {0x00000025, 0x80011144}, + {0x00000026, 0x80000003}, + {0x00000027, 0x8001114B}, + {0x00000028, 0x80000004}, + {0x00000029, 0x8001114C}, + {0x0000002A, 0x80000005}, + {0x0000002B, 0x8001114D}, + {0x0000002C, 0x80000006}, + {0x0000002D, 0x8001114E}, {0x00000500, 0x00003000}, - {0x00000501, 0x02FFFFFF}, + {0x00000501, 0x01FFFFFF}, {0x00000502, 0x00000002}, {0x00000503, 0x00000002}, {0x00000508, 0x01008043}, @@ -350,57 +394,558 @@ static unsigned nv4TablePRAMIN[][2] = {0x0000050C, 0x01008019}, {0x0000050E, 0x00000000}, {0x0000050F, 0x00000000}, +#if 1 {0x00000510, 0x01008018}, +#else + {0x00000510, 0x01008044}, +#endif {0x00000512, 0x00000000}, {0x00000513, 0x00000000}, - {0x00000514, 0x0100A033}, + {0x00000514, 0x01008021}, {0x00000516, 0x00000000}, {0x00000517, 0x00000000}, {0x00000518, 0x0100805F}, {0x0000051A, 0x00000000}, {0x0000051B, 0x00000000}, +#if 1 {0x0000051C, 0x0100804B}, +#else + {0x0000051C, 0x0100804A}, +#endif {0x0000051E, 0x00000000}, {0x0000051F, 0x00000000}, {0x00000520, 0x0100A048}, {0x00000521, 0x00000D01}, {0x00000522, 0x11401140}, - {0x00000523, 0x00000000} + {0x00000523, 0x00000000}, + {0x00000524, 0x0300A054}, + {0x00000525, 0x00000D01}, + {0x00000526, 0x11401140}, + {0x00000527, 0x00000000}, + {0x00000528, 0x0300A055}, + {0x00000529, 0x00000D01}, + {0x0000052A, 0x11401140}, + {0x0000052B, 0x00000000}, + {0x0000052C, 0x00000058}, + {0x0000052E, 0x11401140}, + {0x0000052F, 0x00000000}, + {0x00000530, 0x00000059}, + {0x00000532, 0x11401140}, + {0x00000533, 0x00000000}, + {0x00000534, 0x0000005A}, + {0x00000536, 0x11401140}, + {0x00000537, 0x00000000}, + {0x00000538, 0x0000005B}, + {0x0000053A, 0x11401140}, + {0x0000053B, 0x00000000} }; static unsigned nv4TablePRAMIN_8BPP[][2] = { - {0x00000509, 0x00000301}, - {0x0000050D, 0x00000301}, - {0x00000511, 0x00000301}, - {0x00000515, 0x00000301}, - {0x00000519, 0x00000301}, - {0x0000051D, 0x00000301} + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000302}, + {0x0000050D, 0x00000302}, + {0x00000511, 0x00000202}, + {0x00000515, 0x00000302}, + {0x00000519, 0x00000302}, + {0x0000051D, 0x00000302}, + {0x0000052D, 0x00000302}, + {0x0000052E, 0x00000302}, + {0x00000535, 0x00000000}, + {0x00000539, 0x00000000} }; static unsigned nv4TablePRAMIN_15BPP[][2] = { - {0x00000509, 0x00000901}, - {0x0000050D, 0x00000901}, - {0x00000511, 0x00000901}, - {0x00000515, 0x00000901}, - {0x00000519, 0x00000901}, - {0x0000051D, 0x00000901} + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000902}, + {0x0000050D, 0x00000902}, + {0x00000511, 0x00000802}, + {0x00000515, 0x00000902}, + {0x00000519, 0x00000902}, + {0x0000051D, 0x00000902}, + {0x0000052D, 0x00000902}, + {0x0000052E, 0x00000902}, + {0x00000535, 0x00000702}, + {0x00000539, 0x00000702} }; static unsigned nv4TablePRAMIN_16BPP[][2] = { - {0x00000509, 0x00000C01}, - {0x0000050D, 0x00000C01}, - {0x00000511, 0x00000C01}, - {0x00000515, 0x00000C01}, - {0x00000519, 0x00000C01}, - {0x0000051D, 0x00000C01} + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000C02}, + {0x0000050D, 0x00000C02}, + {0x00000511, 0x00000B02}, + {0x00000515, 0x00000C02}, + {0x00000519, 0x00000C02}, + {0x0000051D, 0x00000C02}, + {0x0000052D, 0x00000C02}, + {0x0000052E, 0x00000C02}, + {0x00000535, 0x00000702}, + {0x00000539, 0x00000702} }; static unsigned nv4TablePRAMIN_32BPP[][2] = { - {0x00000509, 0x00000E01}, - {0x0000050D, 0x00000E01}, - {0x00000511, 0x00000E01}, - {0x00000515, 0x00000E01}, - {0x00000519, 0x00000E01}, - {0x0000051D, 0x00000E01} + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000E02}, + {0x0000050D, 0x00000E02}, + {0x00000511, 0x00000D02}, + {0x00000515, 0x00000E02}, + {0x00000519, 0x00000E02}, + {0x0000051D, 0x00000E02}, + {0x0000052D, 0x00000E02}, + {0x0000052E, 0x00000E02}, + {0x00000535, 0x00000E02}, + {0x00000539, 0x00000E02} +}; +static unsigned nv10TableFIFO[][2] = +{ + {0x00003800, 0x80000014} +}; +static unsigned nv10TablePFIFO[][2] = +{ + {0x00000140, 0x00000000}, + {0x00000480, 0x00000000}, + {0x00000494, 0x00000000}, + {0x00000481, 0x00000000}, + {0x0000048B, 0x00000000}, + {0x00000400, 0x00000000}, + {0x00000414, 0x00000000}, + {0x00000084, 0x03000100}, + {0x00000085, 0x00000110}, + {0x00000086, 0x00000112}, + {0x00000143, 0x0000FFFF}, + {0x00000496, 0x0000FFFF}, + {0x00000050, 0x00000000}, + {0x00000040, 0xFFFFFFFF}, + {0x00000415, 0x00000001}, + {0x00000480, 0x00000001}, + {0x00000494, 0x00000001}, + {0x00000495, 0x00000001}, + {0x00000140, 0x00000001} +}; +static unsigned nv10TablePGRAPH[][2] = +{ + {0x00000020, 0x0003FFFF}, + {0x00000021, 0x00118701}, + {0x00000022, 0x24F82AD9}, + {0x00000023, 0x55DE0030}, + {0x00000020, 0x00000000}, + {0x00000024, 0x00000000}, + {0x00000058, 0x00000000}, + {0x00000060, 0x00000000}, + {0x00000068, 0x00000000}, + {0x00000070, 0x00000000}, + {0x00000078, 0x00000000}, + {0x00000059, 0x00000000}, + {0x00000061, 0x00000000}, + {0x00000069, 0x00000000}, + {0x00000071, 0x00000000}, + {0x00000079, 0x00000000}, + {0x0000005A, 0x00000000}, + {0x00000062, 0x00000000}, + {0x0000006A, 0x00000000}, + {0x00000072, 0x00000000}, + {0x0000007A, 0x00000000}, + {0x0000005B, 0x00000000}, + {0x00000063, 0x00000000}, + {0x0000006B, 0x00000000}, + {0x00000073, 0x00000000}, + {0x0000007B, 0x00000000}, + {0x0000005C, 0x00000000}, + {0x00000064, 0x00000000}, + {0x0000006C, 0x00000000}, + {0x00000074, 0x00000000}, + {0x0000007C, 0x00000000}, + {0x0000005D, 0x00000000}, + {0x00000065, 0x00000000}, + {0x0000006D, 0x00000000}, + {0x00000075, 0x00000000}, + {0x0000007D, 0x00000000}, + {0x0000005E, 0x00000000}, + {0x00000066, 0x00000000}, + {0x0000006E, 0x00000000}, + {0x00000076, 0x00000000}, + {0x0000007E, 0x00000000}, + {0x0000005F, 0x00000000}, + {0x00000067, 0x00000000}, + {0x0000006F, 0x00000000}, + {0x00000077, 0x00000000}, + {0x0000007F, 0x00000000}, + {0x00000053, 0x00000000}, + {0x00000054, 0x00000000}, + {0x00000055, 0x00000000}, + {0x00000056, 0x00000000}, + {0x00000057, 0x00000000}, + {0x00000196, 0x00000000}, + {0x000001A1, 0x01FFFFFF}, + {0x00000197, 0x00000000}, + {0x000001A2, 0x01FFFFFF}, + {0x00000198, 0x00000000}, + {0x000001A3, 0x01FFFFFF}, + {0x00000199, 0x00000000}, + {0x000001A4, 0x01FFFFFF}, + {0x0000019A, 0x00000000}, + {0x000001A5, 0x01FFFFFF}, + {0x0000019B, 0x00000000}, + {0x000001A6, 0x01FFFFFF}, + {0x00000050, 0x01111111}, + {0x00000040, 0xFFFFFFFF}, + {0x00000051, 0x10010100}, + {0x000001C5, 0xFFFFFFFF}, + {0x000001C8, 0x00000001}, + {0x00000204, 0x00000000}, + {0x000001C4, 0x00000001} +}; +static unsigned nv10TablePGRAPH_8BPP[][2] = +{ + {0x000001C9, 0x00111111}, + {0x00000186, 0x00001010}, + {0x0000020C, 0x03020202} +}; +static unsigned nv10TablePGRAPH_15BPP[][2] = +{ + {0x000001C9, 0x00226222}, + {0x00000186, 0x00002071}, + {0x0000020C, 0x09080808} +}; +static unsigned nv10TablePGRAPH_16BPP[][2] = +{ + {0x000001C9, 0x00556555}, + {0x00000186, 0x000050C2}, + {0x0000020C, 0x000B0B0C} +}; +static unsigned nv10TablePGRAPH_32BPP[][2] = +{ + {0x000001C9, 0x0077D777}, + {0x00000186, 0x000070E5}, + {0x0000020C, 0x0E0D0D0D} +}; +static unsigned nv10tri05TablePGRAPH[][2] = +{ + {(0x00000E00/4), 0x00000000}, + {(0x00000E04/4), 0x00000000}, + {(0x00000E08/4), 0x00000000}, + {(0x00000E0C/4), 0x00000000}, + {(0x00000E10/4), 0x00001000}, + {(0x00000E14/4), 0x00001000}, + {(0x00000E18/4), 0x4003ff80}, + {(0x00000E1C/4), 0x00000000}, + {(0x00000E20/4), 0x00000000}, + {(0x00000E24/4), 0x00000000}, + {(0x00000E28/4), 0x00000000}, + {(0x00000E2C/4), 0x00000000}, + {(0x00000E30/4), 0x00080008}, + {(0x00000E34/4), 0x00080008}, + {(0x00000E38/4), 0x00000000}, + {(0x00000E3C/4), 0x00000000}, + {(0x00000E40/4), 0x00000000}, + {(0x00000E44/4), 0x00000000}, + {(0x00000E48/4), 0x00000000}, + {(0x00000E4C/4), 0x00000000}, + {(0x00000E50/4), 0x00000000}, + {(0x00000E54/4), 0x00000000}, + {(0x00000E58/4), 0x00000000}, + {(0x00000E5C/4), 0x00000000}, + {(0x00000E60/4), 0x00000000}, + {(0x00000E64/4), 0x10000000}, + {(0x00000E68/4), 0x00000000}, + {(0x00000E6C/4), 0x00000000}, + {(0x00000E70/4), 0x00000000}, + {(0x00000E74/4), 0x00000000}, + {(0x00000E78/4), 0x00000000}, + {(0x00000E7C/4), 0x00000000}, + {(0x00000E80/4), 0x00000000}, + {(0x00000E84/4), 0x00000000}, + {(0x00000E88/4), 0x08000000}, + {(0x00000E8C/4), 0x00000000}, + {(0x00000E90/4), 0x00000000}, + {(0x00000E94/4), 0x00000000}, + {(0x00000E98/4), 0x00000000}, + {(0x00000E9C/4), 0x4B7FFFFF}, + {(0x00000EA0/4), 0x00000000}, + {(0x00000EA4/4), 0x00000000}, + {(0x00000EA8/4), 0x00000000}, + {(0x00000F00/4), 0x07FF0800}, + {(0x00000F04/4), 0x07FF0800}, + {(0x00000F08/4), 0x07FF0800}, + {(0x00000F0C/4), 0x07FF0800}, + {(0x00000F10/4), 0x07FF0800}, + {(0x00000F14/4), 0x07FF0800}, + {(0x00000F18/4), 0x07FF0800}, + {(0x00000F1C/4), 0x07FF0800}, + {(0x00000F20/4), 0x07FF0800}, + {(0x00000F24/4), 0x07FF0800}, + {(0x00000F28/4), 0x07FF0800}, + {(0x00000F2C/4), 0x07FF0800}, + {(0x00000F30/4), 0x07FF0800}, + {(0x00000F34/4), 0x07FF0800}, + {(0x00000F38/4), 0x07FF0800}, + {(0x00000F3C/4), 0x07FF0800}, + {(0x00000F40/4), 0x10000000}, + {(0x00000F44/4), 0x00000000}, + {(0x00000F50/4), 0x00006740}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F50/4), 0x00006750}, + {(0x00000F54/4), 0x40000000}, + {(0x00000F54/4), 0x40000000}, + {(0x00000F54/4), 0x40000000}, + {(0x00000F54/4), 0x40000000}, + {(0x00000F50/4), 0x00006760}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006770}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006780}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x000067A0}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F50/4), 0x00006AB0}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F50/4), 0x00006AC0}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006C10}, + {(0x00000F54/4), 0xBF800000}, + {(0x00000F50/4), 0x00007030}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007040}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007050}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007060}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007070}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007080}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00007090}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x000070A0}, + {(0x00000F54/4), 0x7149F2CA}, + {(0x00000F50/4), 0x00006A80}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F50/4), 0x00006AA0}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00000040}, + {(0x00000F54/4), 0x00000005}, + {(0x00000F50/4), 0x00006400}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x4B7FFFFF}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006410}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006420}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x00006430}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x000064C0}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F54/4), 0x477FFFFF}, + {(0x00000F54/4), 0x3F800000}, + {(0x00000F50/4), 0x000064D0}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0xC5000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x000064E0}, + {(0x00000F54/4), 0xC4FFF000}, + {(0x00000F54/4), 0xC4FFF000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F50/4), 0x000064F0}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F54/4), 0x00000000}, + {(0x00000F40/4), 0x30000000}, + {(0x00000F44/4), 0x00000004}, + {(0x00000F48/4), 0x10000000}, + {(0x00000F4C/4), 0x00000000} +}; +static unsigned nv10TablePRAMIN[][2] = +{ + {0x00000000, 0x80000010}, + {0x00000001, 0x80011145}, + {0x00000002, 0x80000011}, + {0x00000003, 0x80011146}, + {0x00000004, 0x80000012}, + {0x00000005, 0x80011147}, + {0x00000006, 0x80000013}, + {0x00000007, 0x80011148}, + {0x00000008, 0x80000014}, + {0x00000009, 0x80011149}, + {0x0000000A, 0x80000015}, + {0x0000000B, 0x8001114A}, + {0x00000020, 0x80000000}, + {0x00000021, 0x80011142}, + {0x00000022, 0x80000001}, + {0x00000023, 0x80011143}, + {0x00000024, 0x80000002}, + {0x00000025, 0x80011144}, + {0x00000026, 0x80000003}, + {0x00000027, 0x8001114B}, + {0x00000028, 0x80000004}, + {0x00000029, 0x8001114C}, + {0x0000002A, 0x80000005}, + {0x0000002B, 0x8001114D}, + {0x0000002C, 0x80000006}, + {0x0000002D, 0x8001114E}, + {0x0000002E, 0x80000007}, + {0x0000002F, 0x8001114F}, + {0x00000500, 0x00003000}, + {0x00000501, 0x01FFFFFF}, + {0x00000502, 0x00000002}, + {0x00000503, 0x00000002}, + {0x00000508, 0x01008043}, + {0x0000050A, 0x00000000}, + {0x0000050B, 0x00000000}, + {0x0000050C, 0x01008019}, + {0x0000050E, 0x00000000}, + {0x0000050F, 0x00000000}, +#if 1 + {0x00000510, 0x01008018}, +#else + {0x00000510, 0x01008044}, +#endif + {0x00000512, 0x00000000}, + {0x00000513, 0x00000000}, + {0x00000514, 0x01008021}, + {0x00000516, 0x00000000}, + {0x00000517, 0x00000000}, + {0x00000518, 0x0100805F}, + {0x0000051A, 0x00000000}, + {0x0000051B, 0x00000000}, +#if 1 + {0x0000051C, 0x0100804B}, +#else + {0x0000051C, 0x0100804A}, +#endif + {0x0000051E, 0x00000000}, + {0x0000051F, 0x00000000}, + {0x00000520, 0x0100A048}, + {0x00000521, 0x00000D01}, + {0x00000522, 0x11401140}, + {0x00000523, 0x00000000}, + {0x00000524, 0x0300A094}, + {0x00000525, 0x00000D01}, + {0x00000526, 0x11401140}, + {0x00000527, 0x00000000}, + {0x00000528, 0x0300A095}, + {0x00000529, 0x00000D01}, + {0x0000052A, 0x11401140}, + {0x0000052B, 0x00000000}, + {0x0000052C, 0x00000058}, + {0x0000052E, 0x11401140}, + {0x0000052F, 0x00000000}, + {0x00000530, 0x00000059}, + {0x00000532, 0x11401140}, + {0x00000533, 0x00000000}, + {0x00000534, 0x0000005A}, + {0x00000536, 0x11401140}, + {0x00000537, 0x00000000}, + {0x00000538, 0x0000005B}, + {0x0000053A, 0x11401140}, + {0x0000053B, 0x00000000}, + {0x0000053C, 0x00000093}, + {0x0000053E, 0x11401140}, + {0x0000053F, 0x00000000} +}; +static unsigned nv10TablePRAMIN_8BPP[][2] = +{ + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000302}, + {0x0000050D, 0x00000302}, + {0x00000511, 0x00000202}, + {0x00000515, 0x00000302}, + {0x00000519, 0x00000302}, + {0x0000051D, 0x00000302}, + {0x0000052D, 0x00000302}, + {0x0000052E, 0x00000302}, + {0x00000535, 0x00000000}, + {0x00000539, 0x00000000}, + {0x0000053D, 0x00000000} +}; +static unsigned nv10TablePRAMIN_15BPP[][2] = +{ + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000902}, + {0x0000050D, 0x00000902}, + {0x00000511, 0x00000802}, + {0x00000515, 0x00000902}, + {0x00000519, 0x00000902}, + {0x0000051D, 0x00000902}, + {0x0000052D, 0x00000902}, + {0x0000052E, 0x00000902}, + {0x00000535, 0x00000902}, + {0x00000539, 0x00000902}, + {0x0000053D, 0x00000902} +}; +static unsigned nv10TablePRAMIN_16BPP[][2] = +{ + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000C02}, + {0x0000050D, 0x00000C02}, + {0x00000511, 0x00000B02}, + {0x00000515, 0x00000C02}, + {0x00000519, 0x00000C02}, + {0x0000051D, 0x00000C02}, + {0x0000052D, 0x00000C02}, + {0x0000052E, 0x00000C02}, + {0x00000535, 0x00000C02}, + {0x00000539, 0x00000C02}, + {0x0000053D, 0x00000C02} +}; +static unsigned nv10TablePRAMIN_32BPP[][2] = +{ + /* 0xXXXXXX01 For MSB mono format */ + /* 0xXXXXXX02 For LSB mono format */ + {0x00000509, 0x00000E02}, + {0x0000050D, 0x00000E02}, + {0x00000511, 0x00000D02}, + {0x00000515, 0x00000E02}, + {0x00000519, 0x00000E02}, + {0x0000051D, 0x00000E02}, + {0x0000052D, 0x00000E02}, + {0x0000052E, 0x00000E02}, + {0x00000535, 0x00000E02}, + {0x00000539, 0x00000E02}, + {0x0000053D, 0x00000E02} }; diff --git a/drivers/video/riva/rivafb.h b/drivers/video/riva/rivafb.h new file mode 100644 index 000000000..7134ed233 --- /dev/null +++ b/drivers/video/riva/rivafb.h @@ -0,0 +1,85 @@ +#ifndef __RIVAFB_H +#define __RIVAFB_H + +#include <linux/config.h> +#include <linux/fb.h> +#include <video/fbcon.h> +#include <video/fbcon-cfb4.h> +#include <video/fbcon-cfb8.h> +#include <video/fbcon-cfb16.h> +#include <video/fbcon-cfb32.h> +#include "riva_hw.h" + +/* GGI compatibility macros */ +#define NUM_SEQ_REGS 0x05 +#define NUM_CRT_REGS 0x41 +#define NUM_GRC_REGS 0x09 +#define NUM_ATC_REGS 0x15 + +/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. + * From KGI originally. */ +struct riva_regs { + u8 attr[NUM_ATC_REGS]; + u8 crtc[NUM_CRT_REGS]; + u8 gra[NUM_GRC_REGS]; + u8 seq[NUM_SEQ_REGS]; + u8 misc_output; + RIVA_HW_STATE ext; +}; + +typedef struct { + unsigned char red, green, blue, transp; +} riva_cfb8_cmap_t; + +struct rivafb_info; +struct rivafb_info { + struct fb_info info; /* kernel framebuffer info */ + + RIVA_HW_INST riva; /* interface to riva_hw.c */ + + const char *drvr_name; /* Riva hardware board type */ + + unsigned long ctrl_base_phys; /* physical control register base addr */ + unsigned long fb_base_phys; /* physical framebuffer base addr */ + + caddr_t ctrl_base; /* virtual control register base addr */ + caddr_t fb_base; /* virtual framebuffer base addr */ + + unsigned ram_amount; /* amount of RAM on card, in bytes */ + unsigned dclk_max; /* max DCLK */ + + struct riva_regs initial_state; /* initial startup video mode */ + struct riva_regs current_state; + + struct display disp; + int currcon; + struct display *currcon_display; + + struct rivafb_info *next; + + struct pci_dev *pd; /* pointer to board's pci info */ + unsigned base0_region_size; /* size of control register region */ + unsigned base1_region_size; /* size of framebuffer region */ + + struct riva_cursor *cursor; + + struct display_switch dispsw; + + riva_cfb8_cmap_t palette[256]; /* VGA DAC palette cache */ + +#if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32) + union { +#ifdef FBCON_HAS_CFB16 + u_int16_t cfb16[16]; +#endif +#ifdef FBCON_HAS_CFB32 + u_int32_t cfb32[16]; +#endif + } con_cmap; +#endif /* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */ +#ifdef CONFIG_MTRR + struct { int vram; int vram_valid; } mtrr; +#endif +}; + +#endif /* __RIVAFB_H */
\ No newline at end of file diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index 2f4e2c140..7fc1e0c71 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c @@ -65,7 +65,7 @@ #include <linux/ctype.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/init.h> #include <linux/fb.h> #include <linux/delay.h> diff --git a/drivers/video/sbusfb.c b/drivers/video/sbusfb.c index 4d5b66386..e68950bf4 100644 --- a/drivers/video/sbusfb.c +++ b/drivers/video/sbusfb.c @@ -28,7 +28,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/sgivwfb.c b/drivers/video/sgivwfb.c index e1751e84e..bf8d17e54 100644 --- a/drivers/video/sgivwfb.c +++ b/drivers/video/sgivwfb.c @@ -16,7 +16,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 592180c18..e53a45e5c 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -18,7 +18,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/console.h> diff --git a/drivers/video/skeletonfb.c b/drivers/video/skeletonfb.c index f6cd0a21e..bac350b74 100644 --- a/drivers/video/skeletonfb.c +++ b/drivers/video/skeletonfb.c @@ -14,7 +14,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> diff --git a/drivers/video/sticon-bmode.c b/drivers/video/sticon-bmode.c index e401cbfcd..67ad61671 100644 --- a/drivers/video/sticon-bmode.c +++ b/drivers/video/sticon-bmode.c @@ -67,7 +67,7 @@ this file *will* be replaced with it. You have been warned. #include <linux/console.h> #include <linux/string.h> #include <linux/kd.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vt_kern.h> #include <linux/selection.h> #include <linux/ioport.h> diff --git a/drivers/video/sticore.c b/drivers/video/sticore.c index 56e7f43ce..11f40694f 100644 --- a/drivers/video/sticore.c +++ b/drivers/video/sticore.c @@ -1,7 +1,7 @@ #include <linux/module.h> #include <linux/types.h> #include <linux/kernel.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/init.h> #include <asm/uaccess.h> diff --git a/drivers/video/stifb.c b/drivers/video/stifb.c index 661ff29c5..27a28f10c 100644 --- a/drivers/video/stifb.c +++ b/drivers/video/stifb.c @@ -28,7 +28,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> diff --git a/drivers/video/sun3fb.c b/drivers/video/sun3fb.c index 87936fc0a..04e6c5167 100644 --- a/drivers/video/sun3fb.c +++ b/drivers/video/sun3fb.c @@ -32,7 +32,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/tcxfb.c b/drivers/video/tcxfb.c index dc23dd405..d3ea67d97 100644 --- a/drivers/video/tcxfb.c +++ b/drivers/video/tcxfb.c @@ -1,4 +1,4 @@ -/* $Id: tcxfb.c,v 1.11 1999/11/19 09:57:21 davem Exp $ +/* $Id: tcxfb.c,v 1.12 2001/02/13 01:17:15 davem Exp $ * tcxfb.c: TCX 24/8bit frame buffer driver * * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz) @@ -13,7 +13,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c index d954dc02e..812c3f9c8 100644 --- a/drivers/video/tdfxfb.c +++ b/drivers/video/tdfxfb.c @@ -61,7 +61,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c index 880f1d1db..9e41f7f38 100644 --- a/drivers/video/tgafb.c +++ b/drivers/video/tgafb.c @@ -34,7 +34,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/valkyriefb.c b/drivers/video/valkyriefb.c index 24a8b04a1..7f7bd3a1b 100644 --- a/drivers/video/valkyriefb.c +++ b/drivers/video/valkyriefb.c @@ -44,7 +44,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index 11e803273..01862992d 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c @@ -14,7 +14,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/console.h> diff --git a/drivers/video/vfb.c b/drivers/video/vfb.c index b494e25c6..a2d101945 100644 --- a/drivers/video/vfb.c +++ b/drivers/video/vfb.c @@ -14,7 +14,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/delay.h> #include <linux/interrupt.h> diff --git a/drivers/video/vga16fb.c b/drivers/video/vga16fb.c index 35197da60..a1fa94d37 100644 --- a/drivers/video/vga16fb.c +++ b/drivers/video/vga16fb.c @@ -15,7 +15,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/console.h> diff --git a/drivers/video/vgacon.c b/drivers/video/vgacon.c index 6268b1766..0f341e222 100644 --- a/drivers/video/vgacon.c +++ b/drivers/video/vgacon.c @@ -43,7 +43,7 @@ #include <linux/console_struct.h> #include <linux/string.h> #include <linux/kd.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/vt_kern.h> #include <linux/selection.h> #include <linux/spinlock.h> diff --git a/drivers/video/virgefb.c b/drivers/video/virgefb.c index 047482699..9fbafbaf4 100644 --- a/drivers/video/virgefb.c +++ b/drivers/video/virgefb.c @@ -22,7 +22,7 @@ #include <linux/string.h> #include <linux/mm.h> #include <linux/tty.h> -#include <linux/malloc.h> +#include <linux/slab.h> #include <linux/delay.h> #include <linux/zorro.h> #include <linux/fb.h> |