Merge with 2.3.99-pre9.

22 files changed, 821 insertions, 133 deletions

diff --git a/include/asm-arm/arch-ebsa285/irq.h b/include/asm-arm/arch-ebsa285/irq.h
index 9dcfa9480..134729f34 100644
--- a/include/asm-arm/arch-ebsa285/irq.h
+++ b/include/asm-arm/arch-ebsa285/irq.h
@@ -44,19 +44,8 @@ static int isa_irq = -1;
 static inline int fixup_irq(unsigned int irq)
 {
 #ifdef CONFIG_HOST_FOOTBRIDGE
-	if (irq == isa_irq) {
+	if (irq == isa_irq)
 		irq = *(unsigned char *)PCIIACK_BASE;
-
-		/*
-		 * The NetWinder appears to randomly give wrong interrupt
-		 * numbers from time to time.  When it does, map them to
-		 * the unused IRQ 13
-		 */
-		if (irq >= NR_IRQS) {
-			printk(KERN_ERR "Strange interrupt %d?\n", irq);
-			irq = _ISA_IRQ(13);
-		}
-	}
 #endif
 
 	return irq;
diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h
new file mode 100644
index 000000000..be68279f7
--- /dev/null
+++ b/include/asm-arm/arch-l7200/dma.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS		0xd0000000
+#define MAX_DMA_CHANNELS	8
+
+#define DMA_0			0
+#define DMA_1			1
+#define DMA_2			2
+#define DMA_3			3
+#define DMA_S0			4
+#define DMA_S1			5
+#define DMA_VIRTUAL_FLOPPY	6
+#define DMA_VIRTUAL_SOUND	7
+
+#define DMA_FLOPPY		DMA_VIRTUAL_FLOPPY
+
+#endif
diff --git a/include/asm-arm/arch-l7200/hardware.h b/include/asm-arm/arch-l7200/hardware.h
new file mode 100644
index 000000000..d800cbc8d
--- /dev/null
+++ b/include/asm-arm/arch-l7200/hardware.h
@@ -0,0 +1,49 @@
+/*
+ * linux/include/asm-arm/arch-l7200/hardware.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * This file contains the hardware definitions for the 
+ * LinkUp Systems L7200 SOC development board.
+ *
+ * Changelog:
+ *   02-01-2000	 RS	Created L7200 version, derived from rpc code
+ *   03-21-2000	SJH	Cleaned up file
+ *   04-21-2000	 RS 	Changed mapping of I/O in virtual space
+ *   04-25-2000	SJH	Removed unused symbols and such
+ *   05-05-2000	SJH	Complete rewrite
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_START		0xf0000000
+#define RAM_SIZE		0x02000000
+#define RAM_BASE		0xc0000000
+
+#define IO_START		0x80000000      /* I/O */
+#define IO_SIZE			0x01000000
+#define IO_BASE			0xd0000000
+
+#define IO_START_2		0x90000000      /* I/O */
+#define IO_SIZE_2		0x01000000
+#define IO_BASE_2		0xd1000000
+
+#define ISA_START		0x20000000	/* ISA */
+#define ISA_SIZE		0x20000000
+#define ISA_BASE		0xe0000000
+
+#define FLUSH_BASE_PHYS		0x40000000	/* ROM */
+#define FLUSH_BASE		0xdf000000
+
+#define PARAMS_BASE		(PAGE_OFFSET + 0x0100)
+#define Z_PARAMS_BASE		(RAM_START + PARAMS_OFFSET)
+
+#define PCIO_BASE		IO_BASE
+
+#endif
diff --git a/include/asm-arm/arch-l7200/ide.h b/include/asm-arm/arch-l7200/ide.h
new file mode 100644
index 000000000..0cfcf3aac
--- /dev/null
+++ b/include/asm-arm/arch-l7200/ide.h
@@ -0,0 +1,27 @@
+/*
+ * linux/include/asm-arm/arch-l7200/ide.h
+ *
+ * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  29-03-2000	SJH	Created file placeholder
+ */
+#include <asm/irq.h>
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static __inline__ void
+ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int irq)
+{
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void
+ide_init_default_hwifs(void)
+{
+}
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
new file mode 100644
index 000000000..787b62108
--- /dev/null
+++ b/include/asm-arm/arch-l7200/io.h
@@ -0,0 +1,210 @@
+/*
+ * linux/include/asm-arm/arch-l7200/io.h
+ *
+ * Copyright (C) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Modifications:
+ *  21-03-2000	SJH	Created from linux/include/asm-arm/arch-nexuspci/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/arch/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.  Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x)	(!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions.
+ */
+
+extern __inline__ void __outb (unsigned int value, unsigned int port)
+{
+	unsigned long temp;
+	__asm__ __volatile__(
+	"tst	%2, #0x80000000\n\t"
+	"mov	%0, %4\n\t"
+	"addeq	%0, %0, %3\n\t"
+	"strb	%1, [%0, %2, lsl #2]	@ outb"
+	: "=&r" (temp)
+	: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+	: "cc");
+}
+
+extern __inline__ void __outw (unsigned int value, unsigned int port)
+{
+	unsigned long temp;
+	__asm__ __volatile__(
+	"tst	%2, #0x80000000\n\t"
+	"mov	%0, %4\n\t"
+	"addeq	%0, %0, %3\n\t"
+	"str	%1, [%0, %2, lsl #2]	@ outw"
+	: "=&r" (temp)
+	: "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+	: "cc");
+}
+
+extern __inline__ void __outl (unsigned int value, unsigned int port)
+{
+	unsigned long temp;
+	__asm__ __volatile__(
+	"tst	%2, #0x80000000\n\t"
+	"mov	%0, %4\n\t"
+	"addeq	%0, %0, %3\n\t"
+	"str	%1, [%0, %2, lsl #2]	@ outl"
+	: "=&r" (temp)
+	: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+	: "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)					\
+extern __inline__ unsigned sz __in##fnsuffix (unsigned int port)		\
+{										\
+	unsigned long temp, value;						\
+	__asm__ __volatile__(							\
+	"tst	%2, #0x80000000\n\t"						\
+	"mov	%0, %4\n\t"							\
+	"addeq	%0, %0, %3\n\t"							\
+	"ldr" ##instr## "	%1, [%0, %2, lsl #2]	@ in"###fnsuffix	\
+	: "=&r" (temp), "=r" (value)						\
+	: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)		\
+	: "cc");								\
+	return (unsigned sz)value;						\
+}
+
+extern __inline__ unsigned int __ioaddr (unsigned int port)			\
+{										\
+	if (__PORT_PCIO(port))							\
+		return (unsigned int)(PCIO_BASE + (port << 2));			\
+	else									\
+		return (unsigned int)(IO_BASE + (port << 2));			\
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)	\
+	DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)							\
+({										\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"strb	%0, [%1, %2]	@ outbc"				\
+		: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));		\
+	else									\
+		__asm__ __volatile__(						\
+		"strb	%0, [%1, %2]	@ outbc"				\
+		: : "r" (value), "r" (IO_BASE), "r" ((port) << 2));		\
+})
+
+#define __inbc(port)								\
+({										\
+	unsigned char result;							\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"ldrb	%0, [%1, %2]	@ inbc"					\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));		\
+	else									\
+		__asm__ __volatile__(						\
+		"ldrb	%0, [%1, %2]	@ inbc"					\
+		: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));		\
+	result;									\
+})
+
+#define __outwc(value,port)							\
+({										\
+	unsigned long v = value;						\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"str	%0, [%1, %2]	@ outwc"				\
+		: : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));	\
+	else									\
+		__asm__ __volatile__(						\
+		"str	%0, [%1, %2]	@ outwc"				\
+		: : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2));		\
+})
+
+#define __inwc(port)								\
+({										\
+	unsigned short result;							\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"ldr	%0, [%1, %2]	@ inwc"					\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));		\
+	else									\
+		__asm__ __volatile__(						\
+		"ldr	%0, [%1, %2]	@ inwc"					\
+		: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));		\
+	result & 0xffff;							\
+})
+
+#define __outlc(value,port)							\
+({										\
+	unsigned long v = value;						\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"str	%0, [%1, %2]	@ outlc"				\
+		: : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2));		\
+	else									\
+		__asm__ __volatile__(						\
+		"str	%0, [%1, %2]	@ outlc"				\
+		: : "r" (v), "r" (IO_BASE), "r" ((port) << 2));			\
+})
+
+#define __inlc(port)								\
+({										\
+	unsigned long result;							\
+	if (__PORT_PCIO((port)))						\
+		__asm__ __volatile__(						\
+		"ldr	%0, [%1, %2]	@ inlc"					\
+		: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));		\
+	else									\
+		__asm__ __volatile__(						\
+		"ldr	%0, [%1, %2]	@ inlc"					\
+		: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));		\
+	result;									\
+})
+
+#define __ioaddrc(port)								\
+	(__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
+
+#define inb(p)	 	(__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)	 	(__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)	 	(__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)	(__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)	(__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)	(__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)	(__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+
+/*
+ * Translated address IO functions
+ *
+ * IO address has already been translated to a virtual address
+ */
+#define outb_t(v,p)	(*(volatile unsigned char *)(p) = (v))
+#define inb_t(p)	(*(volatile unsigned char *)(p))
+#define outw_t(v,p)	(*(volatile unsigned int *)(p) = (v))
+#define inw_t(p)	(*(volatile unsigned int *)(p))
+#define outl_t(v,p)	(*(volatile unsigned long *)(p) = (v))
+#define inl_t(p)	(*(volatile unsigned long *)(p))
+
+#endif
diff --git a/include/asm-arm/arch-l7200/irq.h b/include/asm-arm/arch-l7200/irq.h
new file mode 100644
index 000000000..58b61664f
--- /dev/null
+++ b/include/asm-arm/arch-l7200/irq.h
@@ -0,0 +1,66 @@
+/*
+ * include/asm-arm/arch-l7200/irq.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.ne
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000	RS	Created l7200 version, derived from ebsa110 code
+ *   04-15-2000 RS      Made dependent on hardware.h
+ *   05-05-2000 SJH     Complete rewrite
+ */
+
+/*
+ * IRQ base register
+ */
+#define	IRQ_BASE	(IO_BASE_2 + 0x1000)
+
+/* 
+ * Normal IRQ registers
+ */
+#define IRQ_STATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x000))
+#define IRQ_RAWSTATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x004))
+#define IRQ_ENABLE	(*(volatile unsigned long *) (IRQ_BASE + 0x008))
+#define IRQ_ENABLECLEAR	(*(volatile unsigned long *) (IRQ_BASE + 0x00c))
+#define IRQ_SOFT	(*(volatile unsigned long *) (IRQ_BASE + 0x010))
+#define IRQ_SOURCESEL	(*(volatile unsigned long *) (IRQ_BASE + 0x018))
+
+/* 
+ * Fast IRQ registers
+ */
+#define FIQ_STATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x100))
+#define FIQ_RAWSTATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x104))
+#define FIQ_ENABLE	(*(volatile unsigned long *) (IRQ_BASE + 0x108))
+#define FIQ_ENABLECLEAR	(*(volatile unsigned long *) (IRQ_BASE + 0x10c))
+#define FIQ_SOFT	(*(volatile unsigned long *) (IRQ_BASE + 0x110))
+#define FIQ_SOURCESEL	(*(volatile unsigned long *) (IRQ_BASE + 0x118))
+
+#define fixup_irq(x) (x)
+
+static void l7200_mask_irq(unsigned int irq)
+{
+	IRQ_ENABLECLEAR = 1 << irq;
+}
+
+static void l7200_unmask_irq(unsigned int irq)
+{
+	IRQ_ENABLE = 1 << irq;
+}
+ 
+static __inline__ void irq_init_irq(void)
+{
+	int irq;
+
+	IRQ_ENABLECLEAR = 0xffffffff;	/* clear all interrupt enables */
+	FIQ_ENABLECLEAR = 0xffffffff;	/* clear all fast interrupt enables */
+
+	for (irq = 0; irq < NR_IRQS; irq++) {
+		irq_desc[irq].valid	= 1;
+		irq_desc[irq].probe_ok	= 1;
+		irq_desc[irq].mask_ack	= l7200_mask_irq;
+		irq_desc[irq].mask	= l7200_mask_irq;
+		irq_desc[irq].unmask	= l7200_unmask_irq;
+	}
+
+	init_FIQ();
+}
diff --git a/include/asm-arm/arch-l7200/irqs.h b/include/asm-arm/arch-l7200/irqs.h
new file mode 100644
index 000000000..175efa1bd
--- /dev/null
+++ b/include/asm-arm/arch-l7200/irqs.h
@@ -0,0 +1,45 @@
+/*
+ * include/asm-arm/arch-l7200/irqs.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000 RS	Create l7200 version
+ *   03-28-2000 SJH	Removed unused interrupt
+ */
+
+#define NR_IRQS          32
+
+#define IRQ_STWDOG        0   /* Watchdog timer */
+#define IRQ_PROG          1   /* Programmable interrupt */
+#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
+#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
+#define IRQ_GCTC1         4   /* Timer 1 */
+#define IRQ_GCTC2         5   /* Timer 2 */
+#define IRQ_DMA           6   /* DMA controller */
+#define IRQ_CLCD          7   /* Color LCD controller */
+#define IRQ_SM_RX         8   /* Smart card */
+#define IRQ_SM_TX         9   /* Smart cart */
+#define IRQ_SM_RST       10   /* Smart card */
+#define IRQ_SIB          11   /* Serial Interface Bus */
+#define IRQ_MMC          12   /* MultiMediaCard */
+#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
+#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
+#define IRQ_SPI          15   /* SPI slave */
+#define IRQ_UART_1       16   /* UART 1 */
+#define IRQ_UART_2       17   /* UART 2 */
+#define IRQ_IRDA         18   /* IRDA */
+#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
+#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
+#define IRQ_GPIO         21   /* General Purpose IO */
+#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
+#define IRQ_M2M          23   /* Memory to memory DMA  */
+#define IRQ_RESERVED     24   /* RESERVED, don't use */
+#define IRQ_INTF         25   /* External active low interrupt */
+#define IRQ_INT0         26   /* External active low interrupt */
+#define IRQ_INT1         27   /* External active low interrupt */
+#define IRQ_INT2         28   /* External active low interrupt */
+#define IRQ_INT3         29   /* External active low interrupt */
+#define IRQ_BAT_LO       30   /* Low batery or external power */
+#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
new file mode 100644
index 000000000..f2aaabd5c
--- /dev/null
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -0,0 +1,44 @@
+/*
+ * linux/include/asm-arm/arch-l7200/memory.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *
+ * Changelog:
+ *  03-13-2000	SJH	Created
+ *  04-13-2000  RS      Changed bus macros for new addr
+ *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE       (0xc0000000UL)
+#define TASK_SIZE_26    (0x04000000UL)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET     (0xc0000000UL)
+
+/*
+ * Physical DRAM offset on the L7200 SDB.
+ */
+#define PHYS_OFFSET     (0xf0000000UL)
+
+/*
+ * The DRAM is contiguous.
+ */
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-l7200/param.h b/include/asm-arm/arch-l7200/param.h
new file mode 100644
index 000000000..5cd0bcc78
--- /dev/null
+++ b/include/asm-arm/arch-l7200/param.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-l7200/param.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * This file contains the hardware definitions for the
+ * LinkUp Systems L7200 SOC development board.
+ *
+ * Changelog:
+ *   04-21-2000 RS      Created L7200 version
+ *   04-25-2000 SJH     Cleaned up file
+ *   05-03-2000 SJH     Change comments and rate
+ */
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+/*
+ * See 'time.h' for how the RTC HZ rate is set
+ */
+#define HZ 128
+
+#endif
diff --git a/include/asm-arm/arch-l7200/processor.h b/include/asm-arm/arch-l7200/processor.h
new file mode 100644
index 000000000..ee4b4b2ca
--- /dev/null
+++ b/include/asm-arm/arch-l7200/processor.h
@@ -0,0 +1,27 @@
+/*
+ * linux/include/asm-arm/arch-l7200/processor.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  03-21-2000	SJH	Created
+ *  05-03-2000	SJH	Comment cleaning
+ */
+
+#ifndef __ASM_ARCH_PROCESSOR_H
+#define __ASM_ARCH_PROCESSOR_H
+
+/*
+ * Bus types
+ */
+#define EISA_bus 0
+#define EISA_bus__is_a_macro /* for versions in ksyms.c */
+#define MCA_bus 0
+#define MCA_bus__is_a_macro /* for versions in ksyms.c */
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+#endif
diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h
new file mode 100644
index 000000000..238c595d9
--- /dev/null
+++ b/include/asm-arm/arch-l7200/serial_l7200.h
@@ -0,0 +1,101 @@
+/*
+ * linux/include/asm-arm/arch-l7200/serial_l7200.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  05-09-2000	SJH	Created
+ */
+#ifndef __ASM_ARCH_SERIAL_L7200_H
+#define __ASM_ARCH_SERIAL_L7200_H
+
+#include <asm/arch/memory.h>
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD 3686400
+
+/*
+ * UART base register addresses
+ */
+#define UART1_BASE	(IO_BASE + 0x00044000)
+#define UART2_BASE	(IO_BASE + 0x00045000)
+
+/*
+ * UART register offsets
+ */
+#define UARTDR			0x00	/* Tx/Rx data */
+#define RXSTAT			0x04	/* Rx status */
+#define H_UBRLCR		0x08	/* mode register high */
+#define M_UBRLCR		0x0C	/* mode reg mid (MSB of buad)*/
+#define L_UBRLCR		0x10	/* mode reg low (LSB of baud)*/
+#define UARTCON			0x14	/* control register */
+#define UARTFLG			0x18	/* flag register */
+#define UARTINTSTAT		0x1C	/* FIFO IRQ status register */
+#define UARTINTMASK		0x20	/* FIFO IRQ mask register */
+
+/*
+ * UART baud rate register values
+ */
+#define BR_110			0x827
+#define BR_1200			0x06e
+#define BR_2400			0x05f
+#define BR_4800			0x02f
+#define BR_9600			0x017
+#define BR_14400		0x00f
+#define BR_19200		0x00b
+#define BR_38400		0x005
+#define BR_57600		0x003
+#define BR_76800 		0x002
+#define BR_115200		0x001
+
+/*
+ * Receiver status register (RXSTAT) mask values
+ */
+#define RXSTAT_NO_ERR		0x00	/* No error */
+#define RXSTAT_FRM_ERR		0x01	/* Framing error */
+#define RXSTAT_PAR_ERR		0x02	/* Parity error */
+#define RXSTAT_OVR_ERR		0x04	/* Overrun error */
+
+/*
+ * High byte of UART bit rate and line control register (H_UBRLCR) values
+ */
+#define UBRLCR_BRK		0x01	/* generate break on tx */
+#define UBRLCR_PEN		0x02	/* enable parity */
+#define UBRLCR_PDIS		0x00	/* disable parity */
+#define UBRLCR_EVEN		0x04	/* 1= even parity,0 = odd parity */
+#define UBRLCR_STP2		0x08	/* transmit 2 stop bits */
+#define UBRLCR_FIFO		0x10	/* enable FIFO */
+#define UBRLCR_LEN5		0x60	/* word length5 */
+#define UBRLCR_LEN6		0x40	/* word length6 */
+#define UBRLCR_LEN7		0x20	/* word length7 */
+#define UBRLCR_LEN8		0x00	/* word length8 */
+
+/*
+ * UART control register (UARTCON) values
+ */
+#define UARTCON_UARTEN		0x01	/* Enable UART */
+#define UARTCON_DMAONERR	0x08	/* Mask RxDmaRq when errors occur */
+
+/*
+ * UART flag register (UARTFLG) mask values
+ */
+#define UARTFLG_UTXFF		0x20	/* Transmit FIFO full */
+#define UARTFLG_URXFE		0x10	/* Receiver FIFO empty */
+#define UARTFLG_UBUSY		0x08	/* Transmitter busy */
+#define UARTFLG_DCD		0x04	/* Data carrier detect */
+#define UARTFLG_DSR		0x02	/* Data set ready */
+#define UARTFLG_CTS		0x01	/* Clear to send */
+
+/*
+ * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
+ */
+#define UART_TXINT		0x01	/* TX interrupt */
+#define UART_RXINT		0x02	/* RX interrupt */
+#define UART_RXERRINT		0x04	/* RX error interrupt */
+#define UART_MSINT		0x08	/* Modem Status interrupt */
+#define UART_UDINT		0x10	/* UART Disabled interrupt */
+#define UART_ALLIRQS		0x1f	/* All interrupts */
+
+#endif
diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h
new file mode 100644
index 000000000..c3bbe3773
--- /dev/null
+++ b/include/asm-arm/arch-l7200/system.h
@@ -0,0 +1,30 @@
+/*
+ * linux/include/asm-arm/arch-l7200/system.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Changelog
+ *  03-21-2000  SJH	Created
+ *  04-26-2000  SJH	Fixed functions
+ *  05-03-2000  SJH	Removed usage of obsolete 'iomd.h'
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+extern __inline__ void arch_idle(void)
+{
+        while (!current->need_resched && !hlt_counter)
+		{ };
+/*                outb(0, IOMD_SUSMODE);*/
+}
+
+#define arch_power_off()	do { } while (0)
+
+extern inline void arch_reset(char mode)
+{
+	if (mode == 's') {
+		cpu_reset(0);
+	}
+}
+
+#endif
diff --git a/include/asm-arm/arch-l7200/time.h b/include/asm-arm/arch-l7200/time.h
new file mode 100644
index 000000000..077735e21
--- /dev/null
+++ b/include/asm-arm/arch-l7200/time.h
@@ -0,0 +1,68 @@
+/*
+ * linux/include/asm-arm/arch-l7200/time.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000	RS	Created l7200 version, derived from rpc code
+ *   05-03-2000	SJH	Complete rewrite
+ */
+#ifndef _ASM_ARCH_TIME_H
+#define _ASM_ARCH_TIME_H
+
+#include <asm/arch/irqs.h>
+
+/*
+ * RTC base register address
+ */
+#define RTC_BASE	(IO_BASE_2 + 0x2000)
+
+/*
+ * RTC registers
+ */
+#define RTC_RTCDR	(*(volatile unsigned char *) (RTC_BASE + 0x000))
+#define RTC_RTCMR	(*(volatile unsigned char *) (RTC_BASE + 0x004))
+#define RTC_RTCS	(*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCC	(*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCDV	(*(volatile unsigned char *) (RTC_BASE + 0x00c))
+#define RTC_RTCCR	(*(volatile unsigned char *) (RTC_BASE + 0x010))
+
+/*
+ * RTCCR register values
+ */
+#define RTC_RATE_32	0x00      /* 32 Hz tick */
+#define RTC_RATE_64	0x10      /* 64 Hz tick */
+#define RTC_RATE_128	0x20      /* 128 Hz tick */
+#define RTC_RATE_256	0x30      /* 256 Hz tick */
+#define RTC_EN_ALARM	0x01      /* Enable alarm */
+#define RTC_EN_TIC	0x04      /* Enable counter */
+#define RTC_EN_STWDOG	0x08      /* Enable watchdog */
+
+/*
+ * Handler for timer interrupt
+ */
+static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	do_timer(regs);
+	do_profile(regs);
+	RTC_RTCC = 0;				/* Clear interrupt */
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+extern __inline__ void setup_timer(void)
+{
+	xtime.tv_sec = RTC_RTCDR;
+
+	RTC_RTCC = 0;				/* Clear interrupt */
+
+	timer_irq.handler = timer_interrupt;
+
+	setup_arm_irq(IRQ_RTC_TICK, &timer_irq);
+
+	RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;	/* Set rate and enable timer */
+}
+
+#endif
diff --git a/include/asm-arm/arch-l7200/timex.h b/include/asm-arm/arch-l7200/timex.h
new file mode 100644
index 000000000..3c3202620
--- /dev/null
+++ b/include/asm-arm/arch-l7200/timex.h
@@ -0,0 +1,20 @@
+/*
+ * linux/include/asm-arm/arch-l7200/timex.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * 04-21-2000  RS Created file
+ * 05-03-2000 SJH Tick rate was wrong
+ *
+ */
+
+/*
+ * On the ARM720T, clock ticks are set to 128 Hz.
+ *
+ * NOTE: The actual RTC value is set in 'time.h' which
+ *       must be changed when choosing a different tick
+ *       rate. The value of HZ in 'param.h' must also
+ *       be changed to match below.
+ */
+#define CLOCK_TICK_RATE		128
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
new file mode 100644
index 000000000..d2e56455b
--- /dev/null
+++ b/include/asm-arm/arch-l7200/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm-arm/arch-l7200/uncompress.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ */
+
+static __inline__ void putc(char c)
+{
+}
+
+static void puts(const char *s)
+{
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h
new file mode 100644
index 000000000..04fa07e7c
--- /dev/null
+++ b/include/asm-arm/arch-l7200/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * linux/include/asm-arm/arch-l7200/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h
index 77a36a2a4..c12ed91e3 100644
--- a/include/asm-arm/hardirq.h
+++ b/include/asm-arm/hardirq.h
@@ -5,23 +5,27 @@
 #include <linux/threads.h>
 
 extern unsigned int local_irq_count[NR_CPUS];
+extern unsigned int local_bh_count[NR_CPUS];
+
+#define local_irq_count(cpu)	(local_irq_count[(cpu)])
+#define local_bh_count(cpu)	(local_bh_count[(cpu)])
 
 /*
  * Are we in an interrupt context? Either doing bottom half
  * or hardware interrupt processing?
  */
 #define in_interrupt() ({ const int __cpu = smp_processor_id(); \
-	(local_irq_count[__cpu] + local_bh_count[__cpu] != 0); })
+	(local_irq_count(__cpu) + local_bh_count(__cpu) != 0); })
 
-#define in_irq() (local_irq_count[smp_processor_id()] != 0)
+#define in_irq() (local_irq_count(smp_processor_id()) != 0)
 
 #ifndef CONFIG_SMP
 
-#define hardirq_trylock(cpu)	(local_irq_count[cpu] == 0)
+#define hardirq_trylock(cpu)	(local_irq_count(cpu) == 0)
 #define hardirq_endlock(cpu)	do { } while (0)
 
-#define hardirq_enter(cpu)	(local_irq_count[cpu]++)
-#define hardirq_exit(cpu)	(local_irq_count[cpu]--)
+#define irq_enter(cpu,irq)	(local_irq_count(cpu)++)
+#define irq_exit(cpu,irq)	(local_irq_count(cpu)--)
 
 #define synchronize_irq()	do { } while (0)
 
diff --git a/include/asm-arm/proc-armo/semaphore.h b/include/asm-arm/proc-armo/semaphore.h
deleted file mode 100644
index 6926fad12..000000000
--- a/include/asm-arm/proc-armo/semaphore.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/proc-armo/locks.h
- *
- * Copyright (C) 2000 Russell King
- *
- * Interrupt safe locking assembler.
- */
-#ifndef __ASM_PROC_LOCKS_H
-#define __ASM_PROC_LOCKS_H
-
-#define __down_op(ptr,fail)			\
-	({					\
-	__asm__ __volatile__ (			\
-	"@ atomic down operation\n"		\
-"	mov	r0, pc\n"			\
-"	orr	lr, r0, #0x08000000\n"		\
-"	teqp	lr, #0\n"			\
-"	ldr	lr, [%0]\n"			\
-"	and	r0, r0, #0x0c000003\n"		\
-"	subs	lr, lr, #1\n"			\
-"	str	lr, [%0]\n"			\
-"	orrmi	r0, r0, #0x80000000	@ set N\n" \
-"	teqp	r0, #0\n"			\
-"	movmi	r0, %0\n"			\
-	blmi	" SYMBOL_NAME_STR(fail)		\
-	:					\
-	: "r" (ptr)				\
-	: "r0", "lr", "cc");			\
-	})
-
-#define __down_op_ret(ptr,fail)			\
-	({					\
-		unsigned int result;		\
-	__asm__ __volatile__ (			\
-"	@ down_op_ret\n"			\
-"	mov	r0, pc\n"			\
-"	orr	lr, r0, #0x08000000\n"		\
-"	teqp	lr, #0\n"			\
-"	ldr	lr, [%1]\m"			\
-"	and	r0, r0, #0x0c000003\n"		\
-"	subs	lr, lr, #1\n"			\
-"	str	lr, [%1]\n"			\
-"	orrmi	r0, r0, #0x80000000	@ set N\n" \
-"	teqp	r0, #0\n"			\
-"	movmi	r0, %1\n"			\
-"	movpl	r0, #0\n"			\
-"	blmi	" SYMBOL_NAME_STR(fail) "\n"	\
-"	mov	%0, r0"				\
-	: "=&r" (result)			\
-	: "r" (ptr)				\
-	: "r0", "lr", "cc");			\
-	result;					\
-	})
-
-#define __up_op(ptr,wake)			\
-	({					\
-	__asm__ __volatile__ (			\
-	"@ up_op\n"				\
-	mov	r0, pc\n"			\
-	orr	lr, r0, #0x08000000\n"		\
-	teqp	lr, #0\n"			\
-	ldr	lr, [%0]\n"			\
-	and	r0, r0, #0x0c000003\n"		\
-	adds	lr, lr, #1\n"			\
-	str	lr, [%0]\n"			\
-	orrle	r0, r0, #0x80000000	@ set N\n" \
-	teqp	r0, #0\n"			\
-	movmi	r0, %0\n"			\
-	blmi	" SYMBOL_NAME_STR(wake)		\
-	:					\
-	: "r" (ptr)				\
-	: "r0", "lr", "cc");			\
-	})
-
-#endif
diff --git a/include/asm-arm/proc-armv/locks.h b/include/asm-arm/proc-armv/locks.h
index c1cfded3e..0a0391fae 100644
--- a/include/asm-arm/proc-armv/locks.h
+++ b/include/asm-arm/proc-armv/locks.h
@@ -12,18 +12,18 @@
 	({					\
 	__asm__ __volatile__(			\
 	"@ down_op\n"				\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%0]\n"			\
 "	subs	lr, lr, %1\n"			\
 "	str	lr, [%0]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	movmi	r0, %0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	movmi	ip, %0\n"			\
 "	blmi	" SYMBOL_NAME_STR(fail)		\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	})
 
 #define __down_op_ret(ptr,fail)			\
@@ -31,20 +31,20 @@
 		unsigned int ret;		\
 	__asm__ __volatile__(			\
 	"@ down_op_ret\n"			\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%1]\n"			\
 "	subs	lr, lr, %2\n"			\
 "	str	lr, [%1]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	movmi	r0, %1\n"			\
-"	movpl	r0, #0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	movmi	ip, %1\n"			\
+"	movpl	ip, #0\n"			\
 "	blmi	" SYMBOL_NAME_STR(fail) "\n"	\
-"	mov	%0, r0"				\
+"	mov	%0, ip"				\
 	: "=&r" (ret)				\
 	: "r" (ptr), "I" (1)			\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	ret;					\
 	})
 
@@ -52,18 +52,18 @@
 	({					\
 	__asm__ __volatile__(			\
 	"@ up_op\n"				\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%0]\n"			\
 "	adds	lr, lr, %1\n"			\
 "	str	lr, [%0]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	movle	r0, %0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	movle	ip, %0\n"			\
 "	blle	" SYMBOL_NAME_STR(wake)		\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	})
 
 /*
@@ -78,36 +78,36 @@
 	({					\
 	__asm__ __volatile__(			\
 	"@ down_op_write\n"			\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%0]\n"			\
 "	subs	lr, lr, %1\n"			\
 "	str	lr, [%0]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	movne	r0, %0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	movne	ip, %0\n"			\
 "	blne	" SYMBOL_NAME_STR(fail)		\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	})
 
 #define __up_op_write(ptr,wake)			\
 	({					\
 	__asm__ __volatile__(			\
 	"@ up_op_read\n"			\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%0]\n"			\
 "	adds	lr, lr, %1\n"			\
 "	str	lr, [%0]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	movcs	r0, %0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	movcs	ip, %0\n"			\
 "	blcs	" SYMBOL_NAME_STR(wake)		\
 	:					\
 	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	})
 
 #define __down_op_read(ptr,fail)		\
@@ -117,18 +117,18 @@
 	({					\
 	__asm__ __volatile__(			\
 	"@ up_op_read\n"			\
-"	mrs	r0, cpsr\n"			\
-"	orr	lr, r0, #128\n"			\
+"	mrs	ip, cpsr\n"			\
+"	orr	lr, ip, #128\n"			\
 "	msr	cpsr_c, lr\n"			\
 "	ldr	lr, [%0]\n"			\
 "	adds	lr, lr, %1\n"			\
 "	str	lr, [%0]\n"			\
-"	msr	cpsr_c, r0\n"			\
-"	moveq	r0, %0\n"			\
+"	msr	cpsr_c, ip\n"			\
+"	moveq	ip, %0\n"			\
 "	bleq	" SYMBOL_NAME_STR(wake)		\
 	:					\
 	: "r" (ptr), "I" (1)			\
-	: "r0", "lr", "cc");			\
+	: "ip", "lr", "cc");			\
 	})
 
 #endif
diff --git a/include/asm-arm/softirq.h b/include/asm-arm/softirq.h
index f98754813..01e0d73d1 100644
--- a/include/asm-arm/softirq.h
+++ b/include/asm-arm/softirq.h
@@ -4,14 +4,12 @@
 #include <asm/atomic.h>
 #include <asm/hardirq.h>
 
-extern unsigned int local_bh_count[NR_CPUS];
-
-#define cpu_bh_disable(cpu)	do { local_bh_count[(cpu)]++; barrier(); } while (0)
-#define cpu_bh_enable(cpu)	do { barrier(); local_bh_count[(cpu)]--; } while (0)
+#define cpu_bh_disable(cpu)	do { local_bh_count(cpu)++; barrier(); } while (0)
+#define cpu_bh_enable(cpu)	do { barrier(); local_bh_count(cpu)--; } while (0)
 
 #define local_bh_disable()	cpu_bh_disable(smp_processor_id())
 #define local_bh_enable()	cpu_bh_enable(smp_processor_id())
 
-#define in_softirq()		(local_bh_count[smp_processor_id()] != 0)
+#define in_softirq()		(local_bh_count(smp_processor_id()) != 0)
 
 #endif	/* __ASM_SOFTIRQ_H */
diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h
index dfe4cd9ac..2a8ab1624 100644
--- a/include/asm-arm/string.h
+++ b/include/asm-arm/string.h
@@ -13,12 +13,17 @@ extern char * strrchr(const char * s, int c);
 extern char * strchr(const char * s, int c);
 
 #define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
 #define __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
 #define __HAVE_ARCH_MEMCHR
-extern void * memchr(const void *cs, int c, size_t count);
+extern void * memchr(const void *, int, __kernel_size_t);
 
 #define __HAVE_ARCH_MEMZERO
 #define __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
 
 extern void __memzero(void *ptr, __kernel_size_t n);
 
@@ -36,4 +41,3 @@ extern void __memzero(void *ptr, __kernel_size_t n);
 #define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
 
 #endif
- 
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index ca6da3e13..9755af1ab 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -65,7 +65,7 @@
 #define __NR_mpx			(__NR_SYSCALL_BASE+ 56)
 #define __NR_setpgid			(__NR_SYSCALL_BASE+ 57)
 #define __NR_ulimit			(__NR_SYSCALL_BASE+ 58)
-#define __NR_oldolduname		(__NR_SYSCALL_BASE+ 59)
+
 #define __NR_umask			(__NR_SYSCALL_BASE+ 60)
 #define __NR_chroot			(__NR_SYSCALL_BASE+ 61)
 #define __NR_ustat			(__NR_SYSCALL_BASE+ 62)
@@ -115,7 +115,7 @@
 #define __NR_stat			(__NR_SYSCALL_BASE+106)
 #define __NR_lstat			(__NR_SYSCALL_BASE+107)
 #define __NR_fstat			(__NR_SYSCALL_BASE+108)
-#define __NR_olduname			(__NR_SYSCALL_BASE+109)
+
 #define __NR_iopl			(__NR_SYSCALL_BASE+110)
 #define __NR_vhangup			(__NR_SYSCALL_BASE+111)
 #define __NR_idle			(__NR_SYSCALL_BASE+112)