diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-01-31 22:22:27 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-01-31 22:22:27 +0000 |
| commit | 825423e4c4f18289df2393951cfd2a7a31fc0464 (patch) | |
| tree | 4ad80e981c3d9effa910d2247d118d254f9a5d09 /include/asm-i386/system.h | |
| parent | c4693dc4856ab907a5c02187a8d398861bebfc7e (diff) | |
Merge with Linux 2.4.1.
Diffstat (limited to 'include/asm-i386/system.h')
| -rw-r--r-- | include/asm-i386/system.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h index d3b01ab8b..52e24682e 100644 --- a/include/asm-i386/system.h +++ b/include/asm-i386/system.h @@ -267,15 +267,8 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, * I expect future Intel CPU's to have a weaker ordering, * but I'd also expect them to finally get their act together * and add some real memory barriers if so. - * - * The Pentium III does add a real memory barrier with the - * sfence instruction, so we use that where appropriate. */ -#ifndef CONFIG_X86_XMM #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory") -#else -#define mb() __asm__ __volatile__ ("sfence": : :"memory") -#endif #define rmb() mb() #define wmb() __asm__ __volatile__ ("": : :"memory") |