diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-01-11 04:02:40 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-01-11 04:02:40 +0000 |
| commit | e47f00743fc4776491344f2c618cc8dc2c23bcbc (patch) | |
| tree | 13e03a113a82a184c51c19c209867cfd3a59b3b9 /include/asm-ia64/sn/pci | |
| parent | b2ad5f821b1381492d792ca10b1eb7a107b48f14 (diff) | |
Merge with Linux 2.4.0.
Diffstat (limited to 'include/asm-ia64/sn/pci')
| -rw-r--r-- | include/asm-ia64/sn/pci/bridge.h | 1729 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pci_bus_cvlink.h | 29 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pci_defs.h | 244 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pcibr.h | 360 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pcibr_private.h | 415 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pciio.h | 717 | ||||
| -rw-r--r-- | include/asm-ia64/sn/pci/pciio_private.h | 100 |
7 files changed, 3594 insertions, 0 deletions
diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h new file mode 100644 index 000000000..f070d6d2c --- /dev/null +++ b/include/asm-ia64/sn/pci/bridge.h @@ -0,0 +1,1729 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_BRIDGE_H +#define _ASM_SN_PCI_BRIDGE_H + + +/* + * bridge.h - header file for bridge chip and bridge portion of xbridge chip + */ + +#include <asm/sn/xtalk/xwidget.h> + +/* I/O page size */ + +#if _PAGESZ == 4096 +#define IOPFNSHIFT 12 /* 4K per mapped page */ +#else +#define IOPFNSHIFT 14 /* 16K per mapped page */ +#endif /* _PAGESZ */ + +#define IOPGSIZE (1 << IOPFNSHIFT) +#define IOPG(x) ((x) >> IOPFNSHIFT) +#define IOPGOFF(x) ((x) & (IOPGSIZE-1)) + +/* Bridge RAM sizes */ + +#define BRIDGE_INTERNAL_ATES 128 +#define XBRIDGE_INTERNAL_ATES 1024 + +#define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ +#define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ + +#define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ + /* map to each device's */ + /* config space */ +#define BRIDGE_CONFIG1_BASE 0x28000 /* type 1 device config space */ +#define BRIDGE_CONFIG_END 0x30000 +#define BRIDGE_CONFIG_SLOT_SIZE 0x1000 /* each map == 4k */ + +#define BRIDGE_SSRAM_512K 0x00080000 /* 512kB */ +#define BRIDGE_SSRAM_128K 0x00020000 /* 128kB */ +#define BRIDGE_SSRAM_64K 0x00010000 /* 64kB */ +#define BRIDGE_SSRAM_0K 0x00000000 /* 0kB */ + +/* ======================================================================== + * Bridge address map + */ + +#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * All accesses to bridge hardware registers must be done + * using 32-bit loads and stores. + */ +typedef uint32_t bridgereg_t; + +typedef uint64_t bridge_ate_t; + +/* pointers to bridge ATEs + * are always "pointer to volatile" + */ +typedef volatile bridge_ate_t *bridge_ate_p; + +/* + * It is generally preferred that hardware registers on the bridge + * are located from C code via this structure. + * + * Generated from Bridge spec dated 04oct95 + */ + +#ifdef LITTLE_ENDIAN + +typedef volatile struct bridge_s { + + /* Local Registers 0x000000-0x00FFFF */ + + /* standard widget configuration 0x000000-0x000057 */ + widget_cfg_t b_widget; /* 0x000000 */ + + /* helper fieldnames for accessing bridge widget */ + +#define b_wid_id b_widget.w_id +#define b_wid_stat b_widget.w_status +#define b_wid_err_upper b_widget.w_err_upper_addr +#define b_wid_err_lower b_widget.w_err_lower_addr +#define b_wid_control b_widget.w_control +#define b_wid_req_timeout b_widget.w_req_timeout +#define b_wid_int_upper b_widget.w_intdest_upper_addr +#define b_wid_int_lower b_widget.w_intdest_lower_addr +#define b_wid_err_cmdword b_widget.w_err_cmd_word +#define b_wid_llp b_widget.w_llp_cfg +#define b_wid_tflush b_widget.w_tflush + + /* + * we access these through synergy unswizzled space, so the address + * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.) + * That's why we put the register first and filler second. + */ + /* bridge-specific widget configuration 0x000058-0x00007F */ + bridgereg_t b_wid_aux_err; /* 0x00005C */ + bridgereg_t _pad_000058; + + bridgereg_t b_wid_resp_upper; /* 0x000064 */ + bridgereg_t _pad_000060; + + bridgereg_t b_wid_resp_lower; /* 0x00006C */ + bridgereg_t _pad_000068; + + bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ + bridgereg_t _pad_000070; + + bridgereg_t _pad_000078[2]; + + /* PMU & Map 0x000080-0x00008F */ + bridgereg_t b_dir_map; /* 0x000084 */ + bridgereg_t _pad_000080; + bridgereg_t _pad_000088[2]; + + /* SSRAM 0x000090-0x00009F */ + bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ + bridgereg_t _pad_000090; +#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ +#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ + bridgereg_t _pad_000098[2]; + + /* Arbitration 0x0000A0-0x0000AF */ + bridgereg_t b_arb; /* 0x0000A4 */ + bridgereg_t _pad_0000A0; + bridgereg_t _pad_0000A8[2]; + + /* Number In A Can 0x0000B0-0x0000BF */ + bridgereg_t b_nic; /* 0x0000B4 */ + bridgereg_t _pad_0000B0; + bridgereg_t _pad_0000B8[2]; + + /* PCI/GIO 0x0000C0-0x0000FF */ + bridgereg_t b_bus_timeout; /* 0x0000C4 */ + bridgereg_t _pad_0000C0; +#define b_pci_bus_timeout b_bus_timeout + + bridgereg_t b_pci_cfg; /* 0x0000CC */ + bridgereg_t _pad_0000C8; + + bridgereg_t b_pci_err_upper; /* 0x0000D4 */ + bridgereg_t _pad_0000D0; + + bridgereg_t b_pci_err_lower; /* 0x0000DC */ + bridgereg_t _pad_0000D8; + bridgereg_t _pad_0000E0[8]; +#define b_gio_err_lower b_pci_err_lower +#define b_gio_err_upper b_pci_err_upper + + /* Interrupt 0x000100-0x0001FF */ + bridgereg_t b_int_status; /* 0x000104 */ + bridgereg_t _pad_000100; + + bridgereg_t b_int_enable; /* 0x00010C */ + bridgereg_t _pad_000108; + + bridgereg_t b_int_rst_stat; /* 0x000114 */ + bridgereg_t _pad_000110; + + bridgereg_t b_int_mode; /* 0x00011C */ + bridgereg_t _pad_000118; + + bridgereg_t b_int_device; /* 0x000124 */ + bridgereg_t _pad_000120; + + bridgereg_t b_int_host_err; /* 0x00012C */ + bridgereg_t _pad_000128; + + struct { + bridgereg_t addr; /* 0x0001{34,,,6C} */ + bridgereg_t __pad; /* 0x0001{30,,,68} */ + } b_int_addr[8]; /* 0x000130 */ + + bridgereg_t b_err_int_view; /* 0x000174 */ + bridgereg_t _pad_000170; + + bridgereg_t b_mult_int; /* 0x00017c */ + bridgereg_t _pad_000178; + + struct { + bridgereg_t intr; /* 0x0001{84,,,BC} */ + bridgereg_t __pad; /* 0x0001{80,,,B8} */ + } b_force_always[8]; /* 0x000180 */ + + struct { + bridgereg_t intr; /* 0x0001{C4,,,FC} */ + bridgereg_t __pad; /* 0x0001{C0,,,F8} */ + } b_force_pin[8]; /* 0x0001C0 */ + + /* Device 0x000200-0x0003FF */ + struct { + bridgereg_t reg; /* 0x0002{04,,,3C} */ + bridgereg_t __pad; /* 0x0002{00,,,38} */ + } b_device[8]; /* 0x000200 */ + + struct { + bridgereg_t reg; /* 0x0002{44,,,7C} */ + bridgereg_t __pad; /* 0x0002{40,,,78} */ + } b_wr_req_buf[8]; /* 0x000240 */ + + struct { + bridgereg_t reg; /* 0x0002{84,,,8C} */ + bridgereg_t __pad; /* 0x0002{80,,,88} */ + } b_rrb_map[2]; /* 0x000280 */ +#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ +#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ + + bridgereg_t b_resp_status; /* 0x000294 */ + bridgereg_t _pad_000290; + + bridgereg_t b_resp_clear; /* 0x00029C */ + bridgereg_t _pad_000298; + + bridgereg_t _pad_0002A0[24]; + + /* Xbridge only */ + struct { + bridgereg_t upper; /* 0x0003{04,,,F4} */ + bridgereg_t __pad1; /* 0x0003{00,,,F0} */ + bridgereg_t lower; /* 0x0003{0C,,,FC} */ + bridgereg_t __pad2; /* 0x0003{08,,,F8} */ + } b_buf_addr_match[16]; + + /* Performance Monitor Registers (even only) */ + struct { + bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ + bridgereg_t __pad1; /* 0x000400,,,5C0 */ + + bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ + bridgereg_t __pad2; /* 0x000408,,,5C8 */ + + bridgereg_t inflight; /* 0x000414,,,5D4 */ + bridgereg_t __pad3; /* 0x000410,,,5D0 */ + + bridgereg_t prefetch; /* 0x00041C,,,5DC */ + bridgereg_t __pad4; /* 0x000418,,,5D8 */ + + bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ + bridgereg_t __pad5; /* 0x000420,,,5E0 */ + + bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ + bridgereg_t __pad6; /* 0x000428,,,5E8 */ + + bridgereg_t max_latency; /* 0x000434,,,5F4 */ + bridgereg_t __pad7; /* 0x000430,,,5F0 */ + + bridgereg_t clear_all; /* 0x00043C,,,5FC */ + bridgereg_t __pad8; /* 0x000438,,,5F8 */ + } b_buf_count[8]; + + char _pad_000600[0x010000 - 0x000600]; + + /* + * The Xbridge has 1024 internal ATE's and the Bridge has 128. + * Make enough room for the Xbridge ATE's and depend on runtime + * checks to limit access to bridge ATE's. + */ + + /* Internal Address Translation Entry RAM 0x010000-0x011fff */ + union { + bridge_ate_t wr; /* write-only */ + struct { + bridgereg_t rd; /* read-only */ + bridgereg_t _p_pad; + } hi; + } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; + +#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd + + /* the xbridge read path for internal ates starts at 0x12000. + * I don't believe we ever try to read the ates. + */ + /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ + struct { + bridgereg_t rd; + bridgereg_t _p_pad; + } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; + + char _pad_014000[0x20000 - 0x014000]; + + /* PCI Device Configuration Spaces 0x020000-0x027FFF */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type0_cfg_dev[8]; /* 0x020000 */ + + /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + } b_type1_cfg; /* 0x028000-0x029000 */ + + char _pad_029000[0x007000]; /* 0x029000-0x030000 */ + + /* PCI Interrupt Acknowledge Cycle 0x030000 */ + union { + uchar_t c[8 / 1]; + uint16_t s[8 / 2]; + uint32_t l[8 / 4]; + uint64_t d[8 / 8]; + } b_pci_iack; /* 0x030000 */ + + uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ + + /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ + bridge_ate_t b_ext_ate_ram[0x10000]; + + /* Reserved 0x100000-0x1FFFFF */ + char _pad_100000[0x200000-0x100000]; + + /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ + union { /* make all access sizes available. */ + uchar_t c[0x100000 / 1]; + uint16_t s[0x100000 / 2]; + uint32_t l[0x100000 / 4]; + uint64_t d[0x100000 / 8]; + } b_devio_raw[10]; /* 0x200000 */ + + /* b_devio macro is a bit strange; it reflects the + * fact that the Bridge ASIC provides 2M for the + * first two DevIO windows and 1M for the other six. + */ +#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] + + /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ + union { /* make all access sizes available. */ + uchar_t c[0x400000 / 1]; /* read-only */ + uint16_t s[0x400000 / 2]; /* read-write */ + uint32_t l[0x400000 / 4]; /* read-only */ + uint64_t d[0x400000 / 8]; /* read-only */ + } b_external_flash; /* 0xC00000 */ +} bridge_t; + +#else + +/* + * Field formats for Error Command Word and Auxillary Error Command Word + * of bridge. + */ +typedef struct bridge_err_cmdword_s { + union { + uint32_t cmd_word; + struct { + uint32_t didn:4, /* Destination ID */ + sidn:4, /* SOurce ID */ + pactyp:4, /* Packet type */ + tnum:5, /* Trans Number */ + coh:1, /* Coh Transacti */ + ds:2, /* Data size */ + gbr:1, /* GBR enable */ + vbpm:1, /* VBPM message */ + error:1, /* Error occured */ + barr:1, /* Barrier op */ + rsvd:8; + } berr_st; + } berr_un; +} bridge_err_cmdword_t; + +typedef volatile struct bridge_s { + + /* Local Registers 0x000000-0x00FFFF */ + + /* standard widget configuration 0x000000-0x000057 */ + widget_cfg_t b_widget; /* 0x000000 */ + + /* helper fieldnames for accessing bridge widget */ + +#define b_wid_id b_widget.w_id +#define b_wid_stat b_widget.w_status +#define b_wid_err_upper b_widget.w_err_upper_addr +#define b_wid_err_lower b_widget.w_err_lower_addr +#define b_wid_control b_widget.w_control +#define b_wid_req_timeout b_widget.w_req_timeout +#define b_wid_int_upper b_widget.w_intdest_upper_addr +#define b_wid_int_lower b_widget.w_intdest_lower_addr +#define b_wid_err_cmdword b_widget.w_err_cmd_word +#define b_wid_llp b_widget.w_llp_cfg +#define b_wid_tflush b_widget.w_tflush + + /* bridge-specific widget configuration 0x000058-0x00007F */ + bridgereg_t _pad_000058; + bridgereg_t b_wid_aux_err; /* 0x00005C */ + bridgereg_t _pad_000060; + bridgereg_t b_wid_resp_upper; /* 0x000064 */ + bridgereg_t _pad_000068; + bridgereg_t b_wid_resp_lower; /* 0x00006C */ + bridgereg_t _pad_000070; + bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ + bridgereg_t _pad_000078[2]; + + /* PMU & Map 0x000080-0x00008F */ + bridgereg_t _pad_000080; + bridgereg_t b_dir_map; /* 0x000084 */ + bridgereg_t _pad_000088[2]; + + /* SSRAM 0x000090-0x00009F */ + bridgereg_t _pad_000090; + bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ +#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ +#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ + bridgereg_t _pad_000098[2]; + + /* Arbitration 0x0000A0-0x0000AF */ + bridgereg_t _pad_0000A0; + bridgereg_t b_arb; /* 0x0000A4 */ + bridgereg_t _pad_0000A8[2]; + + /* Number In A Can 0x0000B0-0x0000BF */ + bridgereg_t _pad_0000B0; + bridgereg_t b_nic; /* 0x0000B4 */ + bridgereg_t _pad_0000B8[2]; + + /* PCI/GIO 0x0000C0-0x0000FF */ + bridgereg_t _pad_0000C0; + bridgereg_t b_bus_timeout; /* 0x0000C4 */ +#define b_pci_bus_timeout b_bus_timeout + + bridgereg_t _pad_0000C8; + bridgereg_t b_pci_cfg; /* 0x0000CC */ + bridgereg_t _pad_0000D0; + bridgereg_t b_pci_err_upper; /* 0x0000D4 */ + bridgereg_t _pad_0000D8; + bridgereg_t b_pci_err_lower; /* 0x0000DC */ + bridgereg_t _pad_0000E0[8]; +#define b_gio_err_lower b_pci_err_lower +#define b_gio_err_upper b_pci_err_upper + + /* Interrupt 0x000100-0x0001FF */ + bridgereg_t _pad_000100; + bridgereg_t b_int_status; /* 0x000104 */ + bridgereg_t _pad_000108; + bridgereg_t b_int_enable; /* 0x00010C */ + bridgereg_t _pad_000110; + bridgereg_t b_int_rst_stat; /* 0x000114 */ + bridgereg_t _pad_000118; + bridgereg_t b_int_mode; /* 0x00011C */ + bridgereg_t _pad_000120; + bridgereg_t b_int_device; /* 0x000124 */ + bridgereg_t _pad_000128; + bridgereg_t b_int_host_err; /* 0x00012C */ + + struct { + bridgereg_t __pad; /* 0x0001{30,,,68} */ + bridgereg_t addr; /* 0x0001{34,,,6C} */ + } b_int_addr[8]; /* 0x000130 */ + + bridgereg_t _pad_000170; + bridgereg_t b_err_int_view; /* 0x000174 */ + bridgereg_t _pad_000178; + bridgereg_t b_mult_int; /* 0x00017c */ + + struct { + bridgereg_t __pad; /* 0x0001{80,,,B8} */ + bridgereg_t intr; /* 0x0001{84,,,BC} */ + } b_force_always[8]; /* 0x000180 */ + + struct { + bridgereg_t __pad; /* 0x0001{C0,,,F8} */ + bridgereg_t intr; /* 0x0001{C4,,,FC} */ + } b_force_pin[8]; /* 0x0001C0 */ + + /* Device 0x000200-0x0003FF */ + struct { + bridgereg_t __pad; /* 0x0002{00,,,38} */ + bridgereg_t reg; /* 0x0002{04,,,3C} */ + } b_device[8]; /* 0x000200 */ + + struct { + bridgereg_t __pad; /* 0x0002{40,,,78} */ + bridgereg_t reg; /* 0x0002{44,,,7C} */ + } b_wr_req_buf[8]; /* 0x000240 */ + + struct { + bridgereg_t __pad; /* 0x0002{80,,,88} */ + bridgereg_t reg; /* 0x0002{84,,,8C} */ + } b_rrb_map[2]; /* 0x000280 */ +#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ +#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ + + bridgereg_t _pad_000290; + bridgereg_t b_resp_status; /* 0x000294 */ + bridgereg_t _pad_000298; + bridgereg_t b_resp_clear; /* 0x00029C */ + + bridgereg_t _pad_0002A0[24]; + + /* Xbridge only */ + struct { + bridgereg_t __pad1; /* 0x0003{00,,,F0} */ + bridgereg_t upper; /* 0x0003{04,,,F4} */ + bridgereg_t __pad2; /* 0x0003{08,,,F8} */ + bridgereg_t lower; /* 0x0003{0C,,,FC} */ + } b_buf_addr_match[16]; + + /* Performance Monitor Registers (even only) */ + struct { + bridgereg_t __pad1; /* 0x000400,,,5C0 */ + bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ + bridgereg_t __pad2; /* 0x000408,,,5C8 */ + bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ + bridgereg_t __pad3; /* 0x000410,,,5D0 */ + bridgereg_t inflight; /* 0x000414,,,5D4 */ + bridgereg_t __pad4; /* 0x000418,,,5D8 */ + bridgereg_t prefetch; /* 0x00041C,,,5DC */ + bridgereg_t __pad5; /* 0x000420,,,5E0 */ + bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ + bridgereg_t __pad6; /* 0x000428,,,5E8 */ + bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ + bridgereg_t __pad7; /* 0x000430,,,5F0 */ + bridgereg_t max_latency; /* 0x000434,,,5F4 */ + bridgereg_t __pad8; /* 0x000438,,,5F8 */ + bridgereg_t clear_all; /* 0x00043C,,,5FC */ + } b_buf_count[8]; + + char _pad_000600[0x010000 - 0x000600]; + + /* + * The Xbridge has 1024 internal ATE's and the Bridge has 128. + * Make enough room for the Xbridge ATE's and depend on runtime + * checks to limit access to bridge ATE's. + */ + + /* Internal Address Translation Entry RAM 0x010000-0x011fff */ + union { + bridge_ate_t wr; /* write-only */ + struct { + bridgereg_t _p_pad; + bridgereg_t rd; /* read-only */ + } hi; + } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; + +#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd + + /* the xbridge read path for internal ates starts at 0x12000. + * I don't believe we ever try to read the ates. + */ + /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ + struct { + bridgereg_t _p_pad; + bridgereg_t rd; /* read-only */ + } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; + + char _pad_014000[0x20000 - 0x014000]; + + /* PCI Device Configuration Spaces 0x020000-0x027FFF */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type0_cfg_dev[8]; /* 0x020000 */ + + + /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + } b_type1_cfg; /* 0x028000-0x029000 */ + + char _pad_029000[0x007000]; /* 0x029000-0x030000 */ + + /* PCI Interrupt Acknowledge Cycle 0x030000 */ + union { + uchar_t c[8 / 1]; + uint16_t s[8 / 2]; + uint32_t l[8 / 4]; + uint64_t d[8 / 8]; + } b_pci_iack; /* 0x030000 */ + + uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ + + /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ + bridge_ate_t b_ext_ate_ram[0x10000]; + + /* Reserved 0x100000-0x1FFFFF */ + char _pad_100000[0x200000-0x100000]; + + /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ + union { /* make all access sizes available. */ + uchar_t c[0x100000 / 1]; + uint16_t s[0x100000 / 2]; + uint32_t l[0x100000 / 4]; + uint64_t d[0x100000 / 8]; + } b_devio_raw[10]; /* 0x200000 */ + + /* b_devio macro is a bit strange; it reflects the + * fact that the Bridge ASIC provides 2M for the + * first two DevIO windows and 1M for the other six. + */ +#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] + + /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ + union { /* make all access sizes available. */ + uchar_t c[0x400000 / 1]; /* read-only */ + uint16_t s[0x400000 / 2]; /* read-write */ + uint32_t l[0x400000 / 4]; /* read-only */ + uint64_t d[0x400000 / 8]; /* read-only */ + } b_external_flash; /* 0xC00000 */ +} bridge_t; + +#endif + + + + + + +#define berr_field berr_un.berr_st +#endif /* LANGUAGE_C */ + +/* + * The values of these macros can and should be crosschecked + * regularly against the offsets of the like-named fields + * within the "bridge_t" structure above. + */ + +/* Byte offset macros for Bridge internal registers */ + +#define BRIDGE_WID_ID WIDGET_ID +#define BRIDGE_WID_STAT WIDGET_STATUS +#define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR +#define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR +#define BRIDGE_WID_CONTROL WIDGET_CONTROL +#define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT +#define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR +#define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR +#define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD +#define BRIDGE_WID_LLP WIDGET_LLP_CFG +#define BRIDGE_WID_TFLUSH WIDGET_TFLUSH + +#define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ +#define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ +#define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ +#define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ + +#define BRIDGE_DIR_MAP 0x000084 /* Direct Map reg */ + +/* Bridge has SSRAM Parity Error and Xbridge has Map Fault here */ +#define BRIDGE_RAM_PERR 0x000094 /* SSRAM Parity Error */ +#define BRIDGE_MAP_FAULT 0x000094 /* Map Fault */ + +#define BRIDGE_ARB 0x0000A4 /* Arbitration Priority reg */ + +#define BRIDGE_NIC 0x0000B4 /* Number In A Can */ + +#define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ +#define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT +#define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ +#define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ +#define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ + +#define BRIDGE_INT_STATUS 0x000104 /* Interrupt Status */ +#define BRIDGE_INT_ENABLE 0x00010C /* Interrupt Enables */ +#define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ +#define BRIDGE_INT_MODE 0x00011C /* Interrupt Mode */ +#define BRIDGE_INT_DEVICE 0x000124 /* Interrupt Device */ +#define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ + +#define BRIDGE_INT_ADDR0 0x000134 /* Host Address Reg */ +#define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ +#define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) + +#define BRIDGE_INT_VIEW 0x000174 /* Interrupt view */ +#define BRIDGE_MULTIPLE_INT 0x00017c /* Multiple interrupt occured */ + +#define BRIDGE_FORCE_ALWAYS0 0x000184 /* Force an interrupt (always)*/ +#define BRIDGE_FORCE_ALWAYS_OFF 0x000008 /* Force Always offset */ +#define BRIDGE_FORCE_ALWAYS(x) (BRIDGE_FORCE_ALWAYS0+(x)*BRIDGE_FORCE_ALWAYS_OFF) + +#define BRIDGE_FORCE_PIN0 0x0001c4 /* Force an interrupt */ +#define BRIDGE_FORCE_PIN_OFF 0x000008 /* Force Pin offset */ +#define BRIDGE_FORCE_PIN(x) (BRIDGE_FORCE_PIN0+(x)*BRIDGE_FORCE_PIN_OFF) + +#define BRIDGE_DEVICE0 0x000204 /* Device 0 */ +#define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ +#define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) + +#define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ +#define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ +#define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) + +#define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ +#define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ + +#define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ +#define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ + +#define BRIDGE_BUF_ADDR_UPPER0 0x000304 +#define BRIDGE_BUF_ADDR_UPPER_OFF 0x000010 /* PCI Buffer Upper Offset */ +#define BRIDGE_BUF_ADDR_UPPER(x) (BRIDGE_BUF_ADDR_UPPER0+(x)*BRIDGE_BUF_ADDR_UPPER_OFF) + +#define BRIDGE_BUF_ADDR_LOWER0 0x00030c +#define BRIDGE_BUF_ADDR_LOWER_OFF 0x000010 /* PCI Buffer Upper Offset */ +#define BRIDGE_BUF_ADDR_LOWER(x) (BRIDGE_BUF_ADDR_LOWER0+(x)*BRIDGE_BUF_ADDR_LOWER_OFF) + +/* + * Performance Monitor Registers. + * + * The Performance registers are those registers which are associated with + * monitoring the performance of PCI generated reads to the host environ + * ment. Because of the size of the register file only the even registers + * were instrumented. + */ + +#define BRIDGE_BUF_OFF 0x40 +#define BRIDGE_BUF_NEXT(base, off) (base+((off)*BRIDGE_BUF_OFF)) + +/* + * Buffer (x) Flush Count with Data Touch Register. + * + * This counter is incremented each time the corresponding response buffer + * is flushed after at least a single data element in the buffer is used. + * A word write to this address clears the count. + */ + +#define BRIDGE_BUF_0_FLUSH_TOUCH 0x000404 +#define BRIDGE_BUF_2_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 1) +#define BRIDGE_BUF_4_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 2) +#define BRIDGE_BUF_6_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 3) +#define BRIDGE_BUF_8_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 4) +#define BRIDGE_BUF_10_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 5) +#define BRIDGE_BUF_12_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 6) +#define BRIDGE_BUF_14_FLUSH_TOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_TOUCH, 7) + +/* + * Buffer (x) Flush Count w/o Data Touch Register + * + * This counter is incremented each time the corresponding response buffer + * is flushed without any data element in the buffer being used. A word + * write to this address clears the count. + */ + + +#define BRIDGE_BUF_0_FLUSH_NOTOUCH 0x00040c +#define BRIDGE_BUF_2_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 1) +#define BRIDGE_BUF_4_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 2) +#define BRIDGE_BUF_6_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 3) +#define BRIDGE_BUF_8_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 4) +#define BRIDGE_BUF_10_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 5) +#define BRIDGE_BUF_12_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 6) +#define BRIDGE_BUF_14_FLUSH_NOTOUCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_FLUSH_NOTOUCH, 7) + +/* + * Buffer (x) Request in Flight Count Register + * + * This counter is incremented on each bus clock while the request is in + * flight. A word write to this address clears the count. + */ + +#define BRIDGE_BUF_0_INFLIGHT 0x000414 +#define BRIDGE_BUF_2_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 1) +#define BRIDGE_BUF_4_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 2) +#define BRIDGE_BUF_6_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 3) +#define BRIDGE_BUF_8_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 4) +#define BRIDGE_BUF_10_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 5) +#define BRIDGE_BUF_12_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 6) +#define BRIDGE_BUF_14_INFLIGHT BRIDGE_BUF_NEXT(BRIDGE_BUF_0_INFLIGHT, 7) + +/* + * Buffer (x) Prefetch Request Count Register + * + * This counter is incremented each time the request using this buffer was + * generated from the prefetcher. A word write to this address clears the + * count. + */ + +#define BRIDGE_BUF_0_PREFETCH 0x00041C +#define BRIDGE_BUF_2_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 1) +#define BRIDGE_BUF_4_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 2) +#define BRIDGE_BUF_6_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 3) +#define BRIDGE_BUF_8_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 4) +#define BRIDGE_BUF_10_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 5) +#define BRIDGE_BUF_12_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 6) +#define BRIDGE_BUF_14_PREFETCH BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PREFETCH, 7) + +/* + * Buffer (x) Total PCI Retry Count Register + * + * This counter is incremented each time a PCI bus retry occurs and the ad + * dress matches the tag for the selected buffer. The buffer must also has + * this request in-flight. A word write to this address clears the count. + */ + +#define BRIDGE_BUF_0_PCI_RETRY 0x000424 +#define BRIDGE_BUF_2_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 1) +#define BRIDGE_BUF_4_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 2) +#define BRIDGE_BUF_6_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 3) +#define BRIDGE_BUF_8_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 4) +#define BRIDGE_BUF_10_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 5) +#define BRIDGE_BUF_12_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 6) +#define BRIDGE_BUF_14_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_PCI_RETRY, 7) + +/* + * Buffer (x) Max PCI Retry Count Register + * + * This counter is contains the maximum retry count for a single request + * which was in-flight for this buffer. A word write to this address + * clears the count. + */ + +#define BRIDGE_BUF_0_MAX_PCI_RETRY 0x00042C +#define BRIDGE_BUF_2_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 1) +#define BRIDGE_BUF_4_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 2) +#define BRIDGE_BUF_6_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 3) +#define BRIDGE_BUF_8_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 4) +#define BRIDGE_BUF_10_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 5) +#define BRIDGE_BUF_12_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 6) +#define BRIDGE_BUF_14_MAX_PCI_RETRY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_PCI_RETRY, 7) + +/* + * Buffer (x) Max Latency Count Register + * + * This counter is contains the maximum count (in bus clocks) for a single + * request which was in-flight for this buffer. A word write to this + * address clears the count. + */ + +#define BRIDGE_BUF_0_MAX_LATENCY 0x000434 +#define BRIDGE_BUF_2_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 1) +#define BRIDGE_BUF_4_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 2) +#define BRIDGE_BUF_6_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 3) +#define BRIDGE_BUF_8_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 4) +#define BRIDGE_BUF_10_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 5) +#define BRIDGE_BUF_12_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 6) +#define BRIDGE_BUF_14_MAX_LATENCY BRIDGE_BUF_NEXT(BRIDGE_BUF_0_MAX_LATENCY, 7) + +/* + * Buffer (x) Clear All Register + * + * Any access to this register clears all the count values for the (x) + * registers. + */ + +#define BRIDGE_BUF_0_CLEAR_ALL 0x00043C +#define BRIDGE_BUF_2_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 1) +#define BRIDGE_BUF_4_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 2) +#define BRIDGE_BUF_6_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 3) +#define BRIDGE_BUF_8_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 4) +#define BRIDGE_BUF_10_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 5) +#define BRIDGE_BUF_12_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 6) +#define BRIDGE_BUF_14_CLEAR_ALL BRIDGE_BUF_NEXT(BRIDGE_BUF_0_CLEAR_ALL, 7) + +/* end of Performance Monitor Registers */ + +/* Byte offset macros for Bridge I/O space */ + +#define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ + +#define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ +#define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ +#define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ +#define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) +#define BRIDGE_TYPE0_CFG_DEVF(s,f) (BRIDGE_TYPE0_CFG_DEV0+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ + (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) + +#define BRIDGE_TYPE1_CFG 0x00028000 /* Type 1 Cfg space */ + +#define BRIDGE_PCI_IACK 0x00030000 /* PCI Interrupt Ack */ +#define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ + +/* Byte offset macros for Bridge device IO spaces */ + +#define BRIDGE_DEV_CNT 8 /* Up to 8 devices per bridge */ +#define BRIDGE_DEVIO0 0x00200000 /* Device IO 0 Addr */ +#define BRIDGE_DEVIO1 0x00400000 /* Device IO 1 Addr */ +#define BRIDGE_DEVIO2 0x00600000 /* Device IO 2 Addr */ +#define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ + +#define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ +#define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ + +#if LANGUAGE_C + +#define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) +#endif /* LANGUAGE_C */ + +#define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ + +/* ======================================================================== + * Bridge register bit field definitions + */ + +/* Widget part number of bridge */ +#define BRIDGE_WIDGET_PART_NUM 0xc002 +#define XBRIDGE_WIDGET_PART_NUM 0xd002 + +/* Manufacturer of bridge */ +#define BRIDGE_WIDGET_MFGR_NUM 0x036 +#define XBRIDGE_WIDGET_MFGR_NUM 0x024 + +/* Revision numbers for known [X]Bridge revisions */ +#define BRIDGE_REV_A 0x1 +#define BRIDGE_REV_B 0x2 +#define BRIDGE_REV_C 0x3 +#define BRIDGE_REV_D 0x4 +#define XBRIDGE_REV_A 0x1 +#define XBRIDGE_REV_B 0x2 + +/* Part + Rev numbers allows distinction and acscending sequence */ +#define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) +#define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) +#define BRIDGE_PART_REV_C (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_C) +#define BRIDGE_PART_REV_D (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_D) +#define XBRIDGE_PART_REV_A (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_A) +#define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) + +/* Bridge widget status register bits definition */ + +#define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) +#define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) +#define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) +#define BRIDGE_STAT_PCI_GIO_N (0x1 << 5) +#define BRIDGE_STAT_PENDING (0x1F << 0) + +/* Bridge widget control register bits definition */ +#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) +#define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) +#define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) +#define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) +#define BRIDGE_CTRL_RST(n) ((n) << 24) +#define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) +#define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x))) +#define BRIDGE_CTRL_IO_SWAP (0x1 << 23) +#define BRIDGE_CTRL_MEM_SWAP (0x1 << 22) +#define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21) +#define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20) +#define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19) +#define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17) +#define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) +#define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) +#define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) +#define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) +#define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) +#define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16) +#define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12) +#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) +#define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) +#define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) +#define BRIDGE_CTRL_SYS_END (0x1 << 9) +#define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) +#define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) +#define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) +#define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) + +/* Bridge Response buffer Error Upper Register bit fields definition */ +#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20) +#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) +#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16) +#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) +#define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF) + +#define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \ + (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \ + BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) + +#define BRIDGE_RESP_ERRUPPR_DEVICE(x) \ + (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \ + BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) + +/* Bridge direct mapping register bits definition */ +#define BRIDGE_DIRMAP_W_ID_SHFT 20 +#define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) +#define BRIDGE_DIRMAP_RMF_64 (0x1 << 18) +#define BRIDGE_DIRMAP_ADD512 (0x1 << 17) +#define BRIDGE_DIRMAP_OFF (0x1ffff << 0) +#define BRIDGE_DIRMAP_OFF_ADDRSHFT (31) /* lsbit of DIRMAP_OFF is xtalk address bit 31 */ + +/* Bridge Arbitration register bits definition */ +#define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16) +#define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) +#define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8) +#define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) +#define BRIDGE_ARB_FREEZE_GNT (1 << 6) +#define BRIDGE_ARB_HPRI_RING_B2 (1 << 5) +#define BRIDGE_ARB_HPRI_RING_B1 (1 << 4) +#define BRIDGE_ARB_HPRI_RING_B0 (1 << 3) +#define BRIDGE_ARB_LPRI_RING_B2 (1 << 2) +#define BRIDGE_ARB_LPRI_RING_B1 (1 << 1) +#define BRIDGE_ARB_LPRI_RING_B0 (1 << 0) + +/* Bridge Bus time-out register bits definition */ +#define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16) +#define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) +#define BRIDGE_BUS_GIO_TIMEOUT (1 << 12) +#define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0) +#define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) + +/* Bridge interrupt status register bits definition */ +#define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ +#define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ +#define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ +#define BRIDGE_ISR_UNEXP_RESP (0x1 << 29) +#define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28) +#define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27) +#define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26) +#define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25) +#define BRIDGE_ISR_INVLD_ADDR (0x1 << 24) +#define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23) +#define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22) +#define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21) +#define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20) +#define BRIDGE_ISR_LLP_RCTY (0x1 << 19) +#define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18) +#define BRIDGE_ISR_LLP_TCTY (0x1 << 17) +#define BRIDGE_ISR_SSRAM_PERR (0x1 << 16) +#define BRIDGE_ISR_PCI_ABORT (0x1 << 15) +#define BRIDGE_ISR_PCI_PARITY (0x1 << 14) +#define BRIDGE_ISR_PCI_SERR (0x1 << 13) +#define BRIDGE_ISR_PCI_PERR (0x1 << 12) +#define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11) +#define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT +#define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10) +#define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9) +#define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8) +#define BRIDGE_ISR_INT_MSK (0xff << 0) +#define BRIDGE_ISR_INT(x) (0x1 << (x)) + +#define BRIDGE_ISR_LINK_ERROR \ + (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \ + BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \ + BRIDGE_ISR_LLP_TCTY) + +#define BRIDGE_ISR_PCIBUS_PIOERR \ + (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) + +#define BRIDGE_ISR_PCIBUS_ERROR \ + (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ + BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ + BRIDGE_ISR_PCI_PARITY) + +#define BRIDGE_ISR_XTALK_ERROR \ + (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ + BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \ + BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \ + BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \ + BRIDGE_ISR_UNEXP_RESP) + +#define BRIDGE_ISR_ERRORS \ + (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ + BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ + BRIDGE_ISR_PMU_ESIZE_FAULT) + +/* + * List of Errors which are fatal and kill the sytem + */ +#define BRIDGE_ISR_ERROR_FATAL \ + ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ + BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) + +#define BRIDGE_ISR_ERROR_DUMP \ + (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ + BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) + +/* Bridge interrupt enable register bits definition */ +#define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP +#define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT +#define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT +#define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT +#define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR +#define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR +#define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR +#define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP +#define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW +#define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR +#define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR +#define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY +#define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY +#define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY +#define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR +#define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT +#define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY +#define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR +#define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR +#define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT +#define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT +#define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT +#define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT +#define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR +#define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK +#define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) + +/* Bridge interrupt reset register bits definition */ +#define BRIDGE_IRR_MULTI_CLR (0x1 << 6) +#define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) +#define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) +#define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3) +#define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2) +#define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1) +#define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0) +#define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0) +#define BRIDGE_IRR_ALL_CLR 0x7f + +#define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \ + BRIDGE_ISR_XREQ_FIFO_OFLOW) +#define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \ + BRIDGE_ISR_RESP_XTLK_ERR | \ + BRIDGE_ISR_XREAD_REQ_TIMEOUT) +#define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \ + BRIDGE_ISR_BAD_XREQ_PKT | \ + BRIDGE_ISR_REQ_XTLK_ERR | \ + BRIDGE_ISR_INVLD_ADDR) +#define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \ + BRIDGE_ISR_LLP_REC_CBERR | \ + BRIDGE_ISR_LLP_RCTY | \ + BRIDGE_ISR_LLP_TX_RETRY | \ + BRIDGE_ISR_LLP_TCTY) +#define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \ + BRIDGE_ISR_PMU_ESIZE_FAULT) +#define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \ + BRIDGE_ISR_PCI_PARITY | \ + BRIDGE_ISR_PCI_SERR | \ + BRIDGE_ISR_PCI_PERR | \ + BRIDGE_ISR_PCI_MST_TIMEOUT | \ + BRIDGE_ISR_PCI_RETRY_CNT) + +#define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ + BRIDGE_ISR_GIO_MST_TIMEOUT) + +/* Bridge INT_DEV register bits definition */ +#define BRIDGE_INT_DEV_SHFT(n) ((n)*3) +#define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) +#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line)) + +/* Bridge interrupt(x) register bits definition */ +#define BRIDGE_INT_ADDR_HOST 0x0003FF00 +#define BRIDGE_INT_ADDR_FLD 0x000000FF + +#define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 +#define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 +#define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff + +#define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff + +#ifdef SN0 +/* + * The NASID should be shifted by this amount and stored into the + * interrupt(x) register. + */ +#define BRIDGE_INT_ADDR_NASID_SHFT 8 + +/* + * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to + * memory. + */ +#define BRIDGE_INT_ADDR_DEST_IO (1 << 17) +#define BRIDGE_INT_ADDR_DEST_MEM 0 +#define BRIDGE_INT_ADDR_MASK (1 << 17) +#endif + +/* Bridge device(x) register bits definition */ +#define BRIDGE_DEV_ERR_LOCK_EN (1ull << 28) +#define BRIDGE_DEV_PAGE_CHK_DIS (1ull << 27) +#define BRIDGE_DEV_FORCE_PCI_PAR (1ull << 26) +#define BRIDGE_DEV_VIRTUAL_EN (1ull << 25) +#define BRIDGE_DEV_PMU_WRGA_EN (1ull << 24) +#define BRIDGE_DEV_DIR_WRGA_EN (1ull << 23) +#define BRIDGE_DEV_DEV_SIZE (1ull << 22) +#define BRIDGE_DEV_RT (1ull << 21) +#define BRIDGE_DEV_SWAP_PMU (1ull << 20) +#define BRIDGE_DEV_SWAP_DIR (1ull << 19) +#define BRIDGE_DEV_PREF (1ull << 18) +#define BRIDGE_DEV_PRECISE (1ull << 17) +#define BRIDGE_DEV_COH (1ull << 16) +#define BRIDGE_DEV_BARRIER (1ull << 15) +#define BRIDGE_DEV_GBR (1ull << 14) +#define BRIDGE_DEV_DEV_SWAP (1ull << 13) +#define BRIDGE_DEV_DEV_IO_MEM (1ull << 12) +#define BRIDGE_DEV_OFF_MASK 0x00000fff +#define BRIDGE_DEV_OFF_ADDR_SHFT 20 + +#define XBRIDGE_DEV_PMU_BITS BRIDGE_DEV_PMU_WRGA_EN +#define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \ + BRIDGE_DEV_SWAP_PMU) +#define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ + BRIDGE_DEV_SWAP_DIR | \ + BRIDGE_DEV_PREF | \ + BRIDGE_DEV_PRECISE | \ + BRIDGE_DEV_COH | \ + BRIDGE_DEV_BARRIER) +#define XBRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ + BRIDGE_DEV_COH | \ + BRIDGE_DEV_BARRIER) +#define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \ + BRIDGE_DEV_SWAP_DIR | \ + BRIDGE_DEV_COH | \ + BRIDGE_DEV_BARRIER) + +/* Bridge Error Upper register bit field definition */ +#define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ +#define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ +#define BRIDGE_ERRUPPR_DEVNUM_SHFT (16) +#define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) +#define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) +#define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF) + +/* Bridge interrupt mode register bits definition */ +#define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x)) + +/* this should be written to the xbow's link_control(x) register */ +#define BRIDGE_CREDIT 3 + +/* RRB assignment register */ +#define BRIDGE_RRB_EN 0x8 /* after shifting down */ +#define BRIDGE_RRB_DEV 0x7 /* after shifting down */ +#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ +#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ + +/* RRB status register */ +#define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) +#define BRIDGE_RRB_INUSE(r) (0x00000001<<(r)) + +/* RRB clear register */ +#define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) + +/* xbox system controller declarations */ +#define XBOX_BRIDGE_WID 8 +#define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ +#define XBOX_RPS_EXISTS 1 << 6 /* RPS bit in status register */ +#define XBOX_RPS_FAIL 1 << 4 /* RPS status bit in register */ + +/* ======================================================================== + */ +/* + * Macros for Xtalk to Bridge bus (PCI/GIO) PIO + * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings + */ +/* XTALK addresses that map into Bridge Bus addr space */ +#define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L +#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL +#define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L +#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL +#define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L +#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL + +/* Ranges of PCI bus space that can be accessed via PIO from xtalk */ +#define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ +#define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff +#define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ +#define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff + +/* XTALK addresses that map into PCI addresses */ +#define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE +#define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT +#define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE +#define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT +#define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE +#define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT + +/* + * Macros for Bridge bus (PCI/GIO) to Xtalk DMA + */ +/* Bridge Bus DMA addresses */ +#define BRIDGE_LOCAL_BASE 0 +#define BRIDGE_DMA_MAPPED_BASE 0x40000000 +#define BRIDGE_DMA_MAPPED_SIZE 0x40000000 /* 1G Bytes */ +#define BRIDGE_DMA_DIRECT_BASE 0x80000000 +#define BRIDGE_DMA_DIRECT_SIZE 0x80000000 /* 2G Bytes */ + +#define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE + +/* PCI addresses of regions decoded by Bridge for DMA */ +#define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE +#define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE + +#if LANGUAGE_C + +#define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE) +#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ + (uint64_t)(x) >= PCI32_MAPPED_BASE) +#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) +#define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE) +#endif /* LANGUAGE_C */ + +/* + * The GIO address space. + */ +/* Xtalk to GIO PIO */ +#define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE +#define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT + +#define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE + +/* GIO addresses of regions decoded by Bridge for DMA */ +#define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE +#define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE + +#if LANGUAGE_C + +#define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE) +#define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \ + (uint64_t)(x) >= GIO_MAPPED_BASE) +#define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE) +#endif /* LANGUAGE_C */ + +/* PCI to xtalk mapping */ + +/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine + * which xtalk address is accessed + */ +#define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE +#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \ + ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \ + ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE) + +/* 64-bit address attribute masks */ +#define PCI64_ATTR_TARG_MASK 0xf000000000000000 +#define PCI64_ATTR_TARG_SHFT 60 +#define PCI64_ATTR_PREF (1ull << 59) +#define PCI64_ATTR_PREC (1ull << 58) +#define PCI64_ATTR_VIRTUAL (1ull << 57) +#define PCI64_ATTR_BAR (1ull << 56) +#define PCI64_ATTR_SWAP (1ull << 55) +#define PCI64_ATTR_RMF_MASK 0x00ff000000000000 +#define PCI64_ATTR_RMF_SHFT 48 + +#if LANGUAGE_C +/* Address translation entry for mapped pci32 accesses */ +typedef union ate_u { + uint64_t ent; + struct xb_ate_s { /* xbridge */ + uint64_t :16; + uint64_t addr:36; + uint64_t targ:4; + uint64_t reserved:2; + uint64_t swap:1; + uint64_t barrier:1; + uint64_t prefetch:1; + uint64_t precise:1; + uint64_t coherent:1; + uint64_t valid:1; + } xb_field; + struct ate_s { /* bridge */ + uint64_t rmf:16; + uint64_t addr:36; + uint64_t targ:4; + uint64_t reserved:3; + uint64_t barrier:1; + uint64_t prefetch:1; + uint64_t precise:1; + uint64_t coherent:1; + uint64_t valid:1; + } field; +} ate_t; +#endif /* LANGUAGE_C */ + +#define ATE_V (1 << 0) +#define ATE_CO (1 << 1) +#define ATE_PREC (1 << 2) +#define ATE_PREF (1 << 3) +#define ATE_BAR (1 << 4) +#define ATE_SWAP (1 << 5) + +#define ATE_PFNSHIFT 12 +#define ATE_TIDSHIFT 8 +#define ATE_RMFSHIFT 48 + +#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ + ((xid)<<ATE_TIDSHIFT) | \ + (attr) + +/* + * for xbridge, bit 29 of the pci address is the swap bit */ +#define ATE_SWAPSHIFT 29 +#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) +#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) + +#define is_xbridge(bridge) \ + (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM) + +#if LANGUAGE_C + +/* ======================================================================== + */ + +#ifdef MACROFIELD_LINE +/* + * This table forms a relation between the byte offset macros normally + * used for ASM coding and the calculated byte offsets of the fields + * in the C structure. + * + * See bridge_check.c and bridge_html.c for further details. + */ +#ifndef MACROFIELD_LINE_BITFIELD +#define MACROFIELD_LINE_BITFIELD(m) /* ignored */ +#endif + +struct macrofield_s bridge_macrofield[] = +{ + + MACROFIELD_LINE(BRIDGE_WID_ID, b_wid_id) + MACROFIELD_LINE_BITFIELD(WIDGET_REV_NUM) + MACROFIELD_LINE_BITFIELD(WIDGET_PART_NUM) + MACROFIELD_LINE_BITFIELD(WIDGET_MFG_NUM) + MACROFIELD_LINE(BRIDGE_WID_STAT, b_wid_stat) + MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_REC_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_LLP_TX_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_FLASH_SELECT) + MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PCI_GIO_N) + MACROFIELD_LINE_BITFIELD(BRIDGE_STAT_PENDING) + MACROFIELD_LINE(BRIDGE_WID_ERR_UPPER, b_wid_err_upper) + MACROFIELD_LINE(BRIDGE_WID_ERR_LOWER, b_wid_err_lower) + MACROFIELD_LINE(BRIDGE_WID_CONTROL, b_wid_control) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_FLASH_WR_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK50) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK40) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_EN_CLK33) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_RST_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_IO_SWAP) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MEM_SWAP) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_PAGE_SIZE) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_BAD) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SS_PAR_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SSRAM_SIZE_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_F_BAD_PKT) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_LLP_XBAR_CRD_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_RLLP_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_CLR_TLLP_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_SYS_END) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_MAX_TRANS_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_CTRL_WIDGET_ID_MASK) + MACROFIELD_LINE(BRIDGE_WID_REQ_TIMEOUT, b_wid_req_timeout) + MACROFIELD_LINE(BRIDGE_WID_INT_UPPER, b_wid_int_upper) + MACROFIELD_LINE_BITFIELD(WIDGET_INT_VECTOR) + MACROFIELD_LINE_BITFIELD(WIDGET_TARGET_ID) + MACROFIELD_LINE_BITFIELD(WIDGET_UPP_ADDR) + MACROFIELD_LINE(BRIDGE_WID_INT_LOWER, b_wid_int_lower) + MACROFIELD_LINE(BRIDGE_WID_ERR_CMDWORD, b_wid_err_cmdword) + MACROFIELD_LINE_BITFIELD(WIDGET_DIDN) + MACROFIELD_LINE_BITFIELD(WIDGET_SIDN) + MACROFIELD_LINE_BITFIELD(WIDGET_PACTYP) + MACROFIELD_LINE_BITFIELD(WIDGET_TNUM) + MACROFIELD_LINE_BITFIELD(WIDGET_COHERENT) + MACROFIELD_LINE_BITFIELD(WIDGET_DS) + MACROFIELD_LINE_BITFIELD(WIDGET_GBR) + MACROFIELD_LINE_BITFIELD(WIDGET_VBPM) + MACROFIELD_LINE_BITFIELD(WIDGET_ERROR) + MACROFIELD_LINE_BITFIELD(WIDGET_BARRIER) + MACROFIELD_LINE(BRIDGE_WID_LLP, b_wid_llp) + MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXRETRY) + MACROFIELD_LINE_BITFIELD(WIDGET_LLP_NULLTIMEOUT) + MACROFIELD_LINE_BITFIELD(WIDGET_LLP_MAXBURST) + MACROFIELD_LINE(BRIDGE_WID_TFLUSH, b_wid_tflush) + MACROFIELD_LINE(BRIDGE_WID_AUX_ERR, b_wid_aux_err) + MACROFIELD_LINE(BRIDGE_WID_RESP_UPPER, b_wid_resp_upper) + MACROFIELD_LINE(BRIDGE_WID_RESP_LOWER, b_wid_resp_lower) + MACROFIELD_LINE(BRIDGE_WID_TST_PIN_CTRL, b_wid_tst_pin_ctrl) + MACROFIELD_LINE(BRIDGE_DIR_MAP, b_dir_map) + MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_W_ID) + MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_RMF_64) + MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_ADD512) + MACROFIELD_LINE_BITFIELD(BRIDGE_DIRMAP_OFF) + MACROFIELD_LINE(BRIDGE_RAM_PERR, b_ram_perr) + MACROFIELD_LINE(BRIDGE_ARB, b_arb) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_TICK_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_REQ_WAIT_EN_MASK) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_FREEZE_GNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B2) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B1) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_HPRI_RING_B0) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B2) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B1) + MACROFIELD_LINE_BITFIELD(BRIDGE_ARB_LPRI_RING_B0) + MACROFIELD_LINE(BRIDGE_NIC, b_nic) + MACROFIELD_LINE(BRIDGE_PCI_BUS_TIMEOUT, b_pci_bus_timeout) + MACROFIELD_LINE(BRIDGE_PCI_CFG, b_pci_cfg) + MACROFIELD_LINE(BRIDGE_PCI_ERR_UPPER, b_pci_err_upper) + MACROFIELD_LINE(BRIDGE_PCI_ERR_LOWER, b_pci_err_lower) + MACROFIELD_LINE(BRIDGE_INT_STATUS, b_int_status) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_MULTI_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PMU_ESIZE_FAULT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNEXP_RESP) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XRESP_PKT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_BAD_XREQ_PKT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_RESP_XTLK_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_REQ_XTLK_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INVLD_ADDR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_UNSUPPORTED_XOP) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREQ_FIFO_OFLOW) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_SNERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_REC_CBERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_RCTY) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TX_RETRY) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_LLP_TCTY) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_SSRAM_PERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_ABORT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PARITY) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_SERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_PERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_MST_TIMEOUT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_PCI_RETRY_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_XREAD_REQ_TIMEOUT) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_GIO_B_ENBL_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_ISR_INT_MSK) + MACROFIELD_LINE(BRIDGE_INT_ENABLE, b_int_enable) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNEXP_RESP) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PMU_ESIZE_FAULT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XRESP_PKT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_BAD_XREQ_PKT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_RESP_XTLK_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_REQ_XTLK_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INVLD_ADDR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_UNSUPPORTED_XOP) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREQ_FIFO_OFLOW) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_SNERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_REC_CBERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_RCTY) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TX_RETRY) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_LLP_TCTY) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_SSRAM_PERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_ABORT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PARITY) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_SERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_PERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_MST_TIMEOUT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_PCI_RETRY_CNT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_XREAD_REQ_TIMEOUT) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_GIO_B_ENBL_ERR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IMR_INT_MSK) + MACROFIELD_LINE(BRIDGE_INT_RST_STAT, b_int_rst_stat) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_ALL_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_MULTI_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_CRP_GRP_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_RESP_BUF_GRP_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_REQ_DSP_GRP_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_LLP_GRP_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_SSRAM_GRP_CLR) + MACROFIELD_LINE_BITFIELD(BRIDGE_IRR_PCI_GRP_CLR) + MACROFIELD_LINE(BRIDGE_INT_MODE, b_int_mode) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(7)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(6)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(5)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(4)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(3)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(2)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(1)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INTMODE_CLR_PKT_EN(0)) + MACROFIELD_LINE(BRIDGE_INT_DEVICE, b_int_device) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(7)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(6)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(5)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(4)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(3)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(2)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(1)) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_DEV_MASK(0)) + MACROFIELD_LINE(BRIDGE_INT_HOST_ERR, b_int_host_err) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_HOST) + MACROFIELD_LINE_BITFIELD(BRIDGE_INT_ADDR_FLD) + MACROFIELD_LINE(BRIDGE_INT_ADDR0, b_int_addr[0].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(0), b_int_addr[0].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(1), b_int_addr[1].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(2), b_int_addr[2].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(3), b_int_addr[3].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(4), b_int_addr[4].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(5), b_int_addr[5].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(6), b_int_addr[6].addr) + MACROFIELD_LINE(BRIDGE_INT_ADDR(7), b_int_addr[7].addr) + MACROFIELD_LINE(BRIDGE_DEVICE0, b_device[0].reg) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_ERR_LOCK_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PAGE_CHK_DIS) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_FORCE_PCI_PAR) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_VIRTUAL_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PMU_WRGA_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DIR_WRGA_EN) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SIZE) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_RT) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_PMU) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_SWAP_DIR) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PREF) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_PRECISE) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_COH) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_BARRIER) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_GBR) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_SWAP) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_DEV_IO_MEM) + MACROFIELD_LINE_BITFIELD(BRIDGE_DEV_OFF_MASK) + MACROFIELD_LINE(BRIDGE_DEVICE(0), b_device[0].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(1), b_device[1].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(2), b_device[2].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(3), b_device[3].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(4), b_device[4].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(5), b_device[5].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(6), b_device[6].reg) + MACROFIELD_LINE(BRIDGE_DEVICE(7), b_device[7].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF0, b_wr_req_buf[0].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(0), b_wr_req_buf[0].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(1), b_wr_req_buf[1].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(2), b_wr_req_buf[2].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(3), b_wr_req_buf[3].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(4), b_wr_req_buf[4].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(5), b_wr_req_buf[5].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(6), b_wr_req_buf[6].reg) + MACROFIELD_LINE(BRIDGE_WR_REQ_BUF(7), b_wr_req_buf[7].reg) + MACROFIELD_LINE(BRIDGE_EVEN_RESP, b_even_resp) + MACROFIELD_LINE(BRIDGE_ODD_RESP, b_odd_resp) + MACROFIELD_LINE(BRIDGE_RESP_STATUS, b_resp_status) + MACROFIELD_LINE(BRIDGE_RESP_CLEAR, b_resp_clear) + MACROFIELD_LINE(BRIDGE_ATE_RAM, b_int_ate_ram) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV0, b_type0_cfg_dev[0]) + + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(0), b_type0_cfg_dev[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,0), b_type0_cfg_dev[0].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,1), b_type0_cfg_dev[0].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,2), b_type0_cfg_dev[0].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,3), b_type0_cfg_dev[0].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,4), b_type0_cfg_dev[0].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,5), b_type0_cfg_dev[0].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,6), b_type0_cfg_dev[0].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(0,7), b_type0_cfg_dev[0].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(1), b_type0_cfg_dev[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,0), b_type0_cfg_dev[1].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,1), b_type0_cfg_dev[1].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,2), b_type0_cfg_dev[1].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,3), b_type0_cfg_dev[1].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,4), b_type0_cfg_dev[1].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,5), b_type0_cfg_dev[1].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,6), b_type0_cfg_dev[1].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(1,7), b_type0_cfg_dev[1].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(2), b_type0_cfg_dev[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,0), b_type0_cfg_dev[2].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,1), b_type0_cfg_dev[2].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,2), b_type0_cfg_dev[2].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,3), b_type0_cfg_dev[2].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,4), b_type0_cfg_dev[2].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,5), b_type0_cfg_dev[2].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,6), b_type0_cfg_dev[2].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(2,7), b_type0_cfg_dev[2].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(3), b_type0_cfg_dev[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,0), b_type0_cfg_dev[3].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,1), b_type0_cfg_dev[3].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,2), b_type0_cfg_dev[3].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,3), b_type0_cfg_dev[3].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,4), b_type0_cfg_dev[3].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,5), b_type0_cfg_dev[3].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,6), b_type0_cfg_dev[3].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(3,7), b_type0_cfg_dev[3].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(4), b_type0_cfg_dev[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,0), b_type0_cfg_dev[4].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,1), b_type0_cfg_dev[4].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,2), b_type0_cfg_dev[4].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,3), b_type0_cfg_dev[4].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,4), b_type0_cfg_dev[4].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,5), b_type0_cfg_dev[4].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,6), b_type0_cfg_dev[4].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(4,7), b_type0_cfg_dev[4].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(5), b_type0_cfg_dev[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,0), b_type0_cfg_dev[5].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,1), b_type0_cfg_dev[5].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,2), b_type0_cfg_dev[5].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,3), b_type0_cfg_dev[5].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,4), b_type0_cfg_dev[5].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,5), b_type0_cfg_dev[5].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,6), b_type0_cfg_dev[5].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(5,7), b_type0_cfg_dev[5].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(6), b_type0_cfg_dev[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,0), b_type0_cfg_dev[6].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,1), b_type0_cfg_dev[6].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,2), b_type0_cfg_dev[6].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,3), b_type0_cfg_dev[6].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,4), b_type0_cfg_dev[6].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,5), b_type0_cfg_dev[6].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,6), b_type0_cfg_dev[6].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(6,7), b_type0_cfg_dev[6].f[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEV(7), b_type0_cfg_dev[7]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,0), b_type0_cfg_dev[7].f[0]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,1), b_type0_cfg_dev[7].f[1]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,2), b_type0_cfg_dev[7].f[2]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,3), b_type0_cfg_dev[7].f[3]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,4), b_type0_cfg_dev[7].f[4]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,5), b_type0_cfg_dev[7].f[5]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,6), b_type0_cfg_dev[7].f[6]) + MACROFIELD_LINE(BRIDGE_TYPE0_CFG_DEVF(7,7), b_type0_cfg_dev[7].f[7]) + + MACROFIELD_LINE(BRIDGE_TYPE1_CFG, b_type1_cfg) + MACROFIELD_LINE(BRIDGE_PCI_IACK, b_pci_iack) + MACROFIELD_LINE(BRIDGE_EXT_SSRAM, b_ext_ate_ram) + MACROFIELD_LINE(BRIDGE_DEVIO0, b_devio(0)) + MACROFIELD_LINE(BRIDGE_DEVIO(0), b_devio(0)) + MACROFIELD_LINE(BRIDGE_DEVIO(1), b_devio(1)) + MACROFIELD_LINE(BRIDGE_DEVIO(2), b_devio(2)) + MACROFIELD_LINE(BRIDGE_DEVIO(3), b_devio(3)) + MACROFIELD_LINE(BRIDGE_DEVIO(4), b_devio(4)) + MACROFIELD_LINE(BRIDGE_DEVIO(5), b_devio(5)) + MACROFIELD_LINE(BRIDGE_DEVIO(6), b_devio(6)) + MACROFIELD_LINE(BRIDGE_DEVIO(7), b_devio(7)) + MACROFIELD_LINE(BRIDGE_EXTERNAL_FLASH, b_external_flash) +}; +#endif + +#ifdef __cplusplus +}; +#endif +#endif /* C or C++ */ + +#endif /* _ASM_SN_PCI_BRIDGE_H */ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h new file mode 100644 index 000000000..fa5722450 --- /dev/null +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h @@ -0,0 +1,29 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_CVLINK_H +#define _ASM_SN_PCI_CVLINK_H + +#define SET_PCIA64(dev) \ + (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1 +#define IS_PCIA64(dev) (((dev)->dma_mask == 0xffffffffffffffffUL) || \ + (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64)) +#define IS_PCI32G(dev) ((dev)->dma_mask >= 0xffffffff) +#define IS_PCI32L(dev) ((dev)->dma_mask < 0xffffffff) + +struct sn1_widget_sysdata { + devfs_handle_t vhdl; +}; + +struct sn1_device_sysdata { + devfs_handle_t vhdl; + int isa64; +}; + +#endif /* _ASM_SN_PCI_CVLINK_H */ diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h new file mode 100644 index 000000000..d12ad0d58 --- /dev/null +++ b/include/asm-ia64/sn/pci/pci_defs.h @@ -0,0 +1,244 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_PCI_DEFS_H +#define _ASM_SN_PCI_PCI_DEFS_H + +#include <linux/config.h> + +/* defines for the PCI bus architecture */ + +/* Bit layout of address fields for Type-1 + * Configuration Space cycles. + */ +#define PCI_TYPE0_SLOT_MASK 0xFFFFF800 +#define PCI_TYPE0_FUNC_MASK 0x00000700 +#define PCI_TYPE0_REG_MASK 0x000000FF + +#define PCI_TYPE0_SLOT_SHFT 11 +#define PCI_TYPE0_FUNC_SHFT 8 +#define PCI_TYPE0_REG_SHFT 0 + +#define PCI_TYPE0_FUNC(a) (((a) & PCI_TYPE0_FUNC_MASK) >> PCI_TYPE0_FUNC_SHFT) +#define PCI_TYPE0_REG(a) (((a) & PCI_TYPE0_REG_MASK) >> PCI_TYPE0_REG_SHFT) + +#define PCI_TYPE0(s,f,r) ((((1<<(s)) << PCI_TYPE0_SLOT_SHFT) & PCI_TYPE0_SLOT_MASK) |\ + (((f) << PCI_TYPE0_FUNC_SHFT) & PCI_TYPE0_FUNC_MASK) |\ + (((r) << PCI_TYPE0_REG_SHFT) & PCI_TYPE0_REG_MASK)) + +/* Bit layout of address fields for Type-1 + * Configuration Space cycles. + * NOTE: I'm including the byte offset within + * the 32-bit word as part of the register + * number as an extension of the layout in + * the PCI spec. + */ +#define PCI_TYPE1_BUS_MASK 0x00FF0000 +#define PCI_TYPE1_SLOT_MASK 0x0000F100 +#define PCI_TYPE1_FUNC_MASK 0x00000700 +#define PCI_TYPE1_REG_MASK 0x000000FF + +#define PCI_TYPE1_BUS_SHFT 16 +#define PCI_TYPE1_SLOT_SHFT 11 +#define PCI_TYPE1_FUNC_SHFT 8 +#define PCI_TYPE1_REG_SHFT 0 + +#define PCI_TYPE1_BUS(a) (((a) & PCI_TYPE1_BUS_MASK) >> PCI_TYPE1_BUS_SHFT) +#define PCI_TYPE1_SLOT(a) (((a) & PCI_TYPE1_SLOT_MASK) >> PCI_TYPE1_SLOT_SHFT) +#define PCI_TYPE1_FUNC(a) (((a) & PCI_TYPE1_FUNC_MASK) >> PCI_TYPE1_FUNC_SHFT) +#define PCI_TYPE1_REG(a) (((a) & PCI_TYPE1_REG_MASK) >> PCI_TYPE1_REG_SHFT) + +#define PCI_TYPE1(b,s,f,r) ((((b) << PCI_TYPE1_BUS_SHFT) & PCI_TYPE1_BUS_MASK) |\ + (((s) << PCI_TYPE1_SLOT_SHFT) & PCI_TYPE1_SLOT_MASK) |\ + (((f) << PCI_TYPE1_FUNC_SHFT) & PCI_TYPE1_FUNC_MASK) |\ + (((r) << PCI_TYPE1_REG_SHFT) & PCI_TYPE1_REG_MASK)) + +/* Byte offsets of registers in CFG space + */ +#define PCI_CFG_VENDOR_ID 0x00 /* Vendor ID (2 bytes) */ +#define PCI_CFG_DEVICE_ID 0x02 /* Device ID (2 bytes) */ + +#define PCI_CFG_COMMAND 0x04 /* Command (2 bytes) */ +#define PCI_CFG_STATUS 0x06 /* Status (2 bytes) */ + +/* NOTE: if you are using a C "switch" statement to + * differentiate between the Config space registers, be + * aware that PCI_CFG_CLASS_CODE and PCI_CFG_BASE_CLASS + * are the same offset. + */ +#define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */ +#define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */ +#define PCI_CFG_BASE_CLASS 0x09 /* Base Class (1 byte) */ +#define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */ +#define PCI_CFG_PROG_IF 0x0B /* Prog Interface (1 byte) */ + +#define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */ +#define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */ +#define PCI_CFG_HEADER_TYPE 0x0E /* Header Type (1 byte) */ +#define PCI_CFG_BIST 0x0F /* Built In Self Test */ + +#define PCI_CFG_BASE_ADDR_0 0x10 /* Base Address (4 bytes) */ +#define PCI_CFG_BASE_ADDR_1 0x14 /* Base Address (4 bytes) */ +#define PCI_CFG_BASE_ADDR_2 0x18 /* Base Address (4 bytes) */ +#define PCI_CFG_BASE_ADDR_3 0x1C /* Base Address (4 bytes) */ +#define PCI_CFG_BASE_ADDR_4 0x20 /* Base Address (4 bytes) */ +#define PCI_CFG_BASE_ADDR_5 0x24 /* Base Address (4 bytes) */ + +#define PCI_CFG_BASE_ADDR_OFF 0x04 /* Base Address Offset (1..5)*/ +#define PCI_CFG_BASE_ADDR(n) (PCI_CFG_BASE_ADDR_0 + (n)*PCI_CFG_BASE_ADDR_OFF) +#define PCI_CFG_BASE_ADDRS 6 /* up to this many BASE regs */ + +#define PCI_CFG_CARDBUS_CIS 0x28 /* Cardbus CIS Pointer (4B) */ + +#define PCI_CFG_SUBSYS_VEND_ID 0x2C /* Subsystem Vendor ID (2B) */ +#define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */ + +#define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */ + +#define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */ +#define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */ +#define PCI_MIN_GNT 0x3E /* Minimum Grant (1B) */ +#define PCI_MAX_LAT 0x3F /* Maximum Latency (1B) */ + +#define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */ + +/* layout for Type 0x01 headers */ + +#define PCI_CFG_PPB_BUS_PRI 0x18 /* immediate upstream bus # */ +#define PCI_CFG_PPB_BUS_SEC 0x19 /* immediate downstream bus # */ +#define PCI_CFG_PPB_BUS_SUB 0x1A /* last downstream bus # */ +#define PCI_CFG_PPB_SEC_LAT 0x1B /* latency timer for SEC bus */ +#define PCI_CFG_PPB_IOBASE 0x1C /* IO Base Addr bits 12..15 */ +#define PCI_CFG_PPB_IOLIM 0x1D /* IO Limit Addr bits 12..15 */ +#define PCI_CFG_PPB_SEC_STAT 0x1E /* Secondary Status */ +#define PCI_CFG_PPB_MEMBASE 0x20 /* MEM Base Addr bits 16..31 */ +#define PCI_CFG_PPB_MEMLIM 0x22 /* MEM Limit Addr bits 16..31 */ +#define PCI_CFG_PPB_MEMPFBASE 0x24 /* PfMEM Base Addr bits 16..31 */ +#define PCI_CFG_PPB_MEMPFLIM 0x26 /* PfMEM Limit Addr bits 16..31 */ +#define PCI_CFG_PPB_MEMPFBASEHI 0x28 /* PfMEM Base Addr bits 32..63 */ +#define PCI_CFG_PPB_MEMPFLIMHI 0x2C /* PfMEM Limit Addr bits 32..63 */ +#define PCI_CFG_PPB_IOBASEHI 0x30 /* IO Base Addr bits 16..31 */ +#define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */ +#define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */ +#define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */ +#define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */ +#define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */ + /* XXX- these might be DEC 21152 specific */ +#define PCI_CFG_PPB_CHIP_CTRL 0x40 +#define PCI_CFG_PPB_DIAG_CTRL 0x41 +#define PCI_CFG_PPB_ARB_CTRL 0x42 +#define PCI_CFG_PPB_SERR_DISABLE 0x64 +#define PCI_CFG_PPB_CLK2_CTRL 0x68 +#define PCI_CFG_PPB_SERR_STATUS 0x6A + +/* Command Register layout (0x04) */ +#define PCI_CMD_IO_SPACE 0x001 /* I/O Space device */ +#define PCI_CMD_MEM_SPACE 0x002 /* Memory Space */ +#define PCI_CMD_BUS_MASTER 0x004 /* Bus Master */ +#define PCI_CMD_SPEC_CYCLES 0x008 /* Special Cycles */ +#define PCI_CMD_MEMW_INV_ENAB 0x010 /* Memory Write Inv Enable */ +#define PCI_CMD_VGA_PALETTE_SNP 0x020 /* VGA Palette Snoop */ +#define PCI_CMD_PAR_ERR_RESP 0x040 /* Parity Error Response */ +#define PCI_CMD_WAIT_CYCLE_CTL 0x080 /* Wait Cycle Control */ +#define PCI_CMD_SERR_ENABLE 0x100 /* SERR# Enable */ +#define PCI_CMD_F_BK_BK_ENABLE 0x200 /* Fast Back-to-Back Enable */ + +/* Status Register Layout (0x06) */ +#define PCI_STAT_PAR_ERR_DET 0x8000 /* Detected Parity Error */ +#define PCI_STAT_SYS_ERR 0x4000 /* Signaled System Error */ +#define PCI_STAT_RCVD_MSTR_ABT 0x2000 /* Received Master Abort */ +#define PCI_STAT_RCVD_TGT_ABT 0x1000 /* Received Target Abort */ +#define PCI_STAT_SGNL_TGT_ABT 0x0800 /* Signaled Target Abort */ + +#define PCI_STAT_DEVSEL_TIMING 0x0600 /* DEVSEL Timing Mask */ +#define DEVSEL_TIMING(_x) (((_x) >> 9) & 3) /* devsel tim macro */ +#define DEVSEL_FAST 0 /* Fast timing */ +#define DEVSEL_MEDIUM 1 /* Medium timing */ +#define DEVSEL_SLOW 2 /* Slow timing */ + +#define PCI_STAT_DATA_PAR_ERR 0x0100 /* Data Parity Err Detected */ +#define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */ +#define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */ +#define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */ + +/* BIST Register Layout (0x0F) */ +#define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */ +#define PCI_BIST_START_BIST 0x40 /* Start BIST */ +#define PCI_BIST_CMPLTION_MASK 0x0F /* COMPLETION MASK */ +#define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */ + +/* Base Address Register 0x10 */ +#define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */ +#define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */ +#define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */ +#define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */ +#define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */ +#define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */ + +/* PIO interface macros */ + +#ifndef IOC3_EMULATION + +#define PCI_INB(x) (*((volatile char*)x)) +#define PCI_INH(x) (*((volatile short*)x)) +#define PCI_INW(x) (*((volatile int*)x)) +#define PCI_OUTB(x,y) (*((volatile char*)x) = y) +#define PCI_OUTH(x,y) (*((volatile short*)x) = y) +#define PCI_OUTW(x,y) (*((volatile int*)x) = y) + +#else + +extern uint pci_read(void * address, int type); +extern void pci_write(void * address, int data, int type); + +#define BYTE 1 +#define HALF 2 +#define WORD 4 + +#define PCI_INB(x) pci_read((void *)(x),BYTE) +#define PCI_INH(x) pci_read((void *)(x),HALF) +#define PCI_INW(x) pci_read((void *)(x),WORD) +#define PCI_OUTB(x,y) pci_write((void *)(x),(y),BYTE) +#define PCI_OUTH(x,y) pci_write((void *)(x),(y),HALF) +#define PCI_OUTW(x,y) pci_write((void *)(x),(y),WORD) + +#endif /* !IOC3_EMULATION */ + /* effects on reads, merges */ + +#ifdef CONFIG_SGI_IP22 +#define BYTECOUNT_W_GIO 0xbf400000 +#endif + +/* + * Definition of address layouts for PCI Config mechanism #1 + * XXX- These largely duplicate PCI_TYPE1 constants at the top + * of the file; the two groups should probably be combined. + */ + +#define CFG1_ADDR_REGISTER_MASK 0x000000fc +#define CFG1_ADDR_FUNCTION_MASK 0x00000700 +#define CFG1_ADDR_DEVICE_MASK 0x0000f800 +#define CFG1_ADDR_BUS_MASK 0x00ff0000 + +#define CFG1_REGISTER_SHIFT 2 +#define CFG1_FUNCTION_SHIFT 8 +#define CFG1_DEVICE_SHIFT 11 +#define CFG1_BUS_SHIFT 16 + +#ifdef CONFIG_SGI_IP32 + /* Definitions related to IP32 PCI Bridge policy + * XXX- should probaly be moved to a mace-specific header + */ +#define PCI_CONFIG_BITS 0xfe0085ff +#define PCI_CONTROL_MRMRA_ENABLE 0x00000800 +#define PCI_FIRST_IO_ADDR 0x1000 +#define PCI_IO_MAP_INCR 0x1000 +#endif /* CONFIG_SGI_IP32 */ + +#endif /* _ASM_SN_PCI_PCI_DEFS_H */ diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h new file mode 100644 index 000000000..4159fb07b --- /dev/null +++ b/include/asm-ia64/sn/pci/pcibr.h @@ -0,0 +1,360 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_PCIBR_H +#define _ASM_SN_PCI_PCIBR_H + +#if defined(__KERNEL__) + +#include <asm/sn/dmamap.h> +#include <asm/sn/iobus.h> +#include <asm/sn/pio.h> + +#include <asm/sn/pci/pciio.h> +#include <asm/sn/pci/bridge.h> + +/* ===================================================================== + * symbolic constants used by pcibr's xtalk bus provider + */ + +#define PCIBR_PIOMAP_BUSY 0x80000000 + +#define PCIBR_DMAMAP_BUSY 0x80000000 +#define PCIBR_DMAMAP_SSRAM 0x40000000 + +#define PCIBR_INTR_BLOCKED 0x40000000 +#define PCIBR_INTR_BUSY 0x80000000 + +#if LANGUAGE_C + +/* ===================================================================== + * opaque types used by pcibr's xtalk bus provider + */ + +typedef struct pcibr_piomap_s *pcibr_piomap_t; +typedef struct pcibr_dmamap_s *pcibr_dmamap_t; +typedef struct pcibr_intr_s *pcibr_intr_t; + +/* ===================================================================== + * primary entry points: Bridge (pcibr) device driver + * + * These functions are normal device driver entry points + * and are called along with the similar entry points from + * other device drivers. They are included here as documentation + * of their existance and purpose. + * + * pcibr_init() is called to inform us that there is a pcibr driver + * configured into the kernel; it is responsible for registering + * as a crosstalk widget and providing a routine to be called + * when a widget with the proper part number is observed. + * + * pcibr_attach() is called for each vertex in the hardware graph + * corresponding to a crosstalk widget with the manufacturer + * code and part number registered by pcibr_init(). + */ + +extern void pcibr_init(void); + +extern int pcibr_attach(devfs_handle_t); + +/* ===================================================================== + * bus provider function table + * + * Normally, this table is only handed off explicitly + * during provider initialization, and the PCI generic + * layer will stash a pointer to it in the vertex; however, + * exporting it explicitly enables a performance hack in + * the generic PCI provider where if we know at compile + * time that the only possible PCI provider is a + * pcibr, we can go directly to this ops table. + */ + +extern pciio_provider_t pcibr_provider; + +/* ===================================================================== + * secondary entry points: pcibr PCI bus provider + * + * These functions are normally exported explicitly by + * a direct call from the pcibr initialization routine + * into the generic crosstalk provider; they are included + * here to enable a more aggressive performance hack in + * the generic crosstalk layer, where if we know that the + * only possible crosstalk provider is pcibr, and we can + * guarantee that all entry points are properly named, and + * we can deal with the implicit casting properly, then + * we can turn many of the generic provider routines into + * plain brances, or even eliminate them (given sufficient + * smarts on the part of the compilation system). + */ + +extern pcibr_piomap_t pcibr_piomap_alloc(devfs_handle_t dev, + device_desc_t dev_desc, + pciio_space_t space, + iopaddr_t pci_addr, + size_t byte_count, + size_t byte_count_max, + unsigned flags); + +extern void pcibr_piomap_free(pcibr_piomap_t piomap); + +extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, + iopaddr_t xtalk_addr, + size_t byte_count); + +extern void pcibr_piomap_done(pcibr_piomap_t piomap); + +extern caddr_t pcibr_piotrans_addr(devfs_handle_t dev, + device_desc_t dev_desc, + pciio_space_t space, + iopaddr_t pci_addr, + size_t byte_count, + unsigned flags); + +extern iopaddr_t pcibr_piospace_alloc(devfs_handle_t dev, + device_desc_t dev_desc, + pciio_space_t space, + size_t byte_count, + size_t alignment); +extern void pcibr_piospace_free(devfs_handle_t dev, + pciio_space_t space, + iopaddr_t pciaddr, + size_t byte_count); + +extern pcibr_dmamap_t pcibr_dmamap_alloc(devfs_handle_t dev, + device_desc_t dev_desc, + size_t byte_count_max, + unsigned flags); + +extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap); + +extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap, + paddr_t paddr, + size_t byte_count); + +extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap, + alenlist_t palenlist, + unsigned flags); + +extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); + +extern iopaddr_t pcibr_dmatrans_addr(devfs_handle_t dev, + device_desc_t dev_desc, + paddr_t paddr, + size_t byte_count, + unsigned flags); + +extern alenlist_t pcibr_dmatrans_list(devfs_handle_t dev, + device_desc_t dev_desc, + alenlist_t palenlist, + unsigned flags); + +extern void pcibr_dmamap_drain(pcibr_dmamap_t map); + +extern void pcibr_dmaaddr_drain(devfs_handle_t vhdl, + paddr_t addr, + size_t bytes); + +extern void pcibr_dmalist_drain(devfs_handle_t vhdl, + alenlist_t list); + +typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, + pciio_intr_line_t lines); + +extern void pcibr_intr_ibit_set(devfs_handle_t, pcibr_intr_ibit_f *); + +extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, + device_desc_t dev_desc, + pciio_intr_line_t lines, + devfs_handle_t owner_dev); + +extern void pcibr_intr_free(pcibr_intr_t intr); + +extern int pcibr_intr_connect(pcibr_intr_t intr, + intr_func_t intr_func, + intr_arg_t intr_arg, + void *thread); + +extern void pcibr_intr_disconnect(pcibr_intr_t intr); + +extern devfs_handle_t pcibr_intr_cpu_get(pcibr_intr_t intr); + +extern void pcibr_provider_startup(devfs_handle_t pcibr); + +extern void pcibr_provider_shutdown(devfs_handle_t pcibr); + +extern int pcibr_reset(devfs_handle_t dev); + +extern int pcibr_write_gather_flush(devfs_handle_t dev); + +extern pciio_endian_t pcibr_endian_set(devfs_handle_t dev, + pciio_endian_t device_end, + pciio_endian_t desired_end); + +extern pciio_priority_t pcibr_priority_set(devfs_handle_t dev, + pciio_priority_t device_prio); + +extern uint64_t pcibr_config_get(devfs_handle_t conn, + unsigned reg, + unsigned size); + +extern void pcibr_config_set(devfs_handle_t conn, + unsigned reg, + unsigned size, + uint64_t value); + +extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, + int error_code); + +extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, + pciio_space_t *spacep, + iopaddr_t *addrp); + +extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, + int *count_vchan0, + int *count_vchan1); + +extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); +extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, + int *count_vchan0, + int *count_vchan1, + int *count_reserved, + int *count_pool); + +extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, + int dev_1_rrbs, int virt1, + int dev_2_rrbs, int virt2, + int dev_3_rrbs, int virt3, + int dev_4_rrbs, int virt4); + +typedef void +rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, + int *vendor_list); + +typedef rrb_alloc_funct_f *rrb_alloc_funct_t; + +void pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, + rrb_alloc_funct_f *func); + +extern void pcibr_device_unregister(devfs_handle_t); +extern int pcibr_dma_enabled(devfs_handle_t); +/* + * Bridge-specific flags that can be set via pcibr_device_flags_set + * and cleared via pcibr_device_flags_clear. Other flags are + * more generic and are maniuplated through PCI-generic interfaces. + * + * Note that all PCI implementation-specific flags (Bridge flags, in + * this case) are in bits 15-31. The lower 15 bits are reserved + * for PCI-generic flags. + * + * Some of these flags have been "promoted" to the + * generic layer, so they can be used without having + * to "know" that the PCI bus is hosted by a Bridge. + * + * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when + * allocating ATE's. ATE count computation will assume that the + * address to be mapped will start on a page boundary. + */ +#define PCIBR_NO_ATE_ROUNDUP 0x00008000 +#define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */ +#define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */ +#define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */ +#define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */ +#define PCIBR_PRECISE 0x00100000 +#define PCIBR_NOPRECISE 0x00200000 +#define PCIBR_BARRIER 0x00400000 +#define PCIBR_NOBARRIER 0x00800000 +#define PCIBR_VCHAN0 0x01000000 +#define PCIBR_VCHAN1 0x02000000 +#define PCIBR_64BIT 0x04000000 +#define PCIBR_NO64BIT 0x08000000 +#define PCIBR_SWAP 0x10000000 +#define PCIBR_NOSWAP 0x20000000 + +#define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */ +#define PCIBR_ACTIVE 0x80000000 /* need a "done" */ + +/* Flags that have meaning to pcibr_device_flags_{set,clear} */ +#define PCIBR_DEVICE_FLAGS ( \ + PCIBR_WRITE_GATHER |\ + PCIBR_NOWRITE_GATHER |\ + PCIBR_PREFETCH |\ + PCIBR_NOPREFETCH |\ + PCIBR_PRECISE |\ + PCIBR_NOPRECISE |\ + PCIBR_BARRIER |\ + PCIBR_NOBARRIER \ +) + +/* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */ +#define PCIBR_DMA_FLAGS ( \ + PCIBR_PREFETCH |\ + PCIBR_NOPREFETCH |\ + PCIBR_PRECISE |\ + PCIBR_NOPRECISE |\ + PCIBR_BARRIER |\ + PCIBR_NOBARRIER |\ + PCIBR_VCHAN0 |\ + PCIBR_VCHAN1 \ +) + +typedef int pcibr_device_flags_t; + +/* + * Set bits in the Bridge Device(x) register for this device. + * "flags" are defined above. NOTE: this includes turning + * things *OFF* as well as turning them *ON* ... + */ +extern int pcibr_device_flags_set(devfs_handle_t dev, + pcibr_device_flags_t flags); + +/* + * Allocate Read Response Buffers for use by the specified device. + * count_vchan0 is the total number of buffers desired for the + * "normal" channel. count_vchan1 is the total number of buffers + * desired for the "virtual" channel. Returns 0 on success, or + * <0 on failure, which occurs when we're unable to allocate any + * buffers to a channel that desires at least one buffer. + */ +extern int pcibr_rrb_alloc(devfs_handle_t pconn_vhdl, + int *count_vchan0, + int *count_vchan1); + +/* + * Get the starting PCIbus address out of the given DMA map. + * This function is supposed to be used by a close friend of PCI bridge + * since it relies on the fact that the starting address of the map is fixed at + * the allocation time in the current implementation of PCI bridge. + */ +extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); + +extern xwidget_intr_preset_f pcibr_xintr_preset; + +extern void pcibr_hints_fix_rrbs(devfs_handle_t); +extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); +extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t); +extern void pcibr_hints_handsoff(devfs_handle_t); + +typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); +extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); + +extern int pcibr_asic_rev(devfs_handle_t); + +#endif /* _LANGUAGE_C */ +#endif /* #if defined(__KERNEL__) */ +/* + * Some useful ioctls into the pcibr driver + */ +#define PCIBR 'p' +#define _PCIBR(x) ((PCIBR << 8) | (x)) + +#define PCIBR_SLOT_POWERUP _PCIBR(1) +#define PCIBR_SLOT_SHUTDOWN _PCIBR(2) +#define PCIBR_SLOT_INQUIRY _PCIBR(3) + +#endif /* _ASM_SN_PCI_PCIBR_H */ diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h new file mode 100644 index 000000000..f7f033989 --- /dev/null +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -0,0 +1,415 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H +#define _ASM_SN_PCI_PCIBR_PRIVATE_H + +/* + * pcibr_private.h -- private definitions for pcibr + * only the pcibr driver (and its closest friends) + * should ever peek into this file. + */ + +#include <asm/sn/pci/pciio_private.h> + +/* + * convenience typedefs + */ + +typedef uint64_t pcibr_DMattr_t; +typedef uint32_t pcibr_ATEattr_t; + +typedef struct pcibr_info_s *pcibr_info_t, **pcibr_info_h; +typedef struct pcibr_soft_s *pcibr_soft_t; +typedef struct pcibr_soft_slot_s *pcibr_soft_slot_t; +typedef struct pcibr_hints_s *pcibr_hints_t; +typedef struct pcibr_intr_list_s *pcibr_intr_list_t; +typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; + +/* + * Bridge sets up PIO using this information. + */ +struct pcibr_piomap_s { + struct pciio_piomap_s bp_pp; /* generic stuff */ + +#define bp_flags bp_pp.pp_flags /* PCIBR_PIOMAP flags */ +#define bp_dev bp_pp.pp_dev /* associated pci card */ +#define bp_slot bp_pp.pp_slot /* which slot the card is in */ +#define bp_space bp_pp.pp_space /* which address space */ +#define bp_pciaddr bp_pp.pp_pciaddr /* starting offset of mapping */ +#define bp_mapsz bp_pp.pp_mapsz /* size of this mapping */ +#define bp_kvaddr bp_pp.pp_kvaddr /* kernel virtual address to use */ + + iopaddr_t bp_xtalk_addr; /* corresponding xtalk address */ + xtalk_piomap_t bp_xtalk_pio; /* corresponding xtalk resource */ + pcibr_piomap_t bp_next; /* Next piomap on the list */ + pcibr_soft_t bp_soft; /* backpointer to bridge soft data */ + int bp_toc[1]; /* PCI timeout counter */ + +}; + +/* + * Bridge sets up DMA using this information. + */ +struct pcibr_dmamap_s { + struct pciio_dmamap_s bd_pd; +#define bd_flags bd_pd.pd_flags /* PCIBR_DMAMAP flags */ +#define bd_dev bd_pd.pd_dev /* associated pci card */ +#define bd_slot bd_pd.pd_slot /* which slot the card is in */ + struct pcibr_soft_s *bd_soft; /* pcibr soft state backptr */ + xtalk_dmamap_t bd_xtalk; /* associated xtalk resources */ + + size_t bd_max_size; /* maximum size of mapping */ + xwidgetnum_t bd_xio_port; /* target XIO port */ + iopaddr_t bd_xio_addr; /* target XIO address */ + iopaddr_t bd_pci_addr; /* via PCI address */ + + int bd_ate_index; /* Address Translation Entry Index */ + int bd_ate_count; /* number of ATE's allocated */ + bridge_ate_p bd_ate_ptr; /* where to write first ATE */ + bridge_ate_t bd_ate_proto; /* prototype ATE (for xioaddr=0) */ + bridge_ate_t bd_ate_prime; /* value of 1st ATE written */ +}; + +/* + * Bridge sets up interrupts using this information. + */ + +struct pcibr_intr_s { + struct pciio_intr_s bi_pi; +#define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ +#define bi_dev bi_pi.pi_dev /* associated pci card */ +#define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ +#define bi_func bi_pi.pi_func /* handler function (when connected) */ +#define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ +#define bi_tinfo bi_pi.pi_tinfo /* Thread info (when connected) */ +#define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ +#define bi_irq bi_pi.pi_irq /* IRQ assigned. */ +#define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ + unsigned bi_ibits; /* which Bridge interrupt bit(s) */ + pcibr_soft_t bi_soft; /* shortcut to soft info */ +}; + +/* + * per-connect point pcibr data, including + * standard pciio data in-line: + */ +struct pcibr_info_s { + struct pciio_info_s f_c; /* MUST BE FIRST. */ +#define f_vertex f_c.c_vertex /* back pointer to vertex */ +#define f_bus f_c.c_bus /* which bus the card is in */ +#define f_slot f_c.c_slot /* which slot the card is in */ +#define f_func f_c.c_func /* which func (on multi-func cards) */ +#define f_vendor f_c.c_vendor /* PCI card "vendor" code */ +#define f_device f_c.c_device /* PCI card "device" code */ +#define f_master f_c.c_master /* PCI bus provider */ +#define f_mfast f_c.c_mfast /* cached fastinfo from c_master */ +#define f_pops f_c.c_pops /* cached provider from c_master */ +#define f_efunc f_c.c_efunc /* error handling function */ +#define f_einfo f_c.c_einfo /* first parameter for efunc */ +#define f_window f_c.c_window /* state of BASE regs */ +#define f_rbase f_c.c_rbase /* expansion rom base */ +#define f_rsize f_c.c_rsize /* expansion rom size */ +#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ + + /* pcibr-specific connection state */ + int f_ibit[4]; /* Bridge bit for each INTx */ + pcibr_piomap_t f_piomap; +}; + +/* ===================================================================== + * Shared Interrupt Information + */ + +struct pcibr_intr_list_s { + pcibr_intr_list_t il_next; + pcibr_intr_t il_intr; + volatile bridgereg_t *il_wrbf; /* ptr to b_wr_req_buf[] */ +}; + +/* ===================================================================== + * Interrupt Wrapper Data + */ +struct pcibr_intr_wrap_s { + pcibr_soft_t iw_soft; /* which bridge */ + volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ + bridgereg_t iw_intr; /* bits in b_int_status */ + pcibr_intr_list_t iw_list; /* ghostbusters! */ +}; + +#define PCIBR_ISR_ERR_START 8 +#define PCIBR_ISR_MAX_ERRS 32 + +/* ===================================================================== + * Bridge Device State structure + * + * one instance of this structure is kept for each + * Bridge ASIC in the system. + */ + +struct pcibr_soft_s { + devfs_handle_t bs_conn; /* xtalk connection point */ + devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ + int bs_int_enable; /* Mask of enabled intrs */ + bridge_t *bs_base; /* PIO pointer to Bridge chip */ + char *bs_name; /* hw graph name */ + xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ + devfs_handle_t bs_master; /* xtalk master vertex */ + xwidgetnum_t bs_mxid; /* master's xtalk ID number */ + + iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ + xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ + + struct map *bs_int_ate_map; /* rmalloc map for internal ATEs */ + struct map *bs_ext_ate_map; /* rmalloc map for external ATEs */ + short bs_int_ate_size; /* number of internal ates */ + short bs_xbridge; /* if 1 then xbridge */ + + int bs_rev_num; /* revision number of Bridge */ + + unsigned bs_dma_flags; /* revision-implied DMA flags */ + + /* + * Lock used primarily to get mutual exclusion while managing any + * bridge resources.. + */ + lock_t bs_lock; + + devfs_handle_t bs_noslot_conn; /* NO-SLOT connection point */ + pcibr_info_t bs_noslot_info; + struct pcibr_soft_slot_s { + /* information we keep about each CFG slot */ + + /* some devices (ioc3 in non-slotted + * configurations, sometimes) make use + * of more than one REQ/GNT/INT* signal + * sets. The slot corresponding to the + * IDSEL that the device responds to is + * called the host slot; the slot + * numbers that the device is stealing + * REQ/GNT/INT bits from are known as + * the guest slots. + */ + int has_host; + pciio_slot_t host_slot; + devfs_handle_t slot_conn; + /* Potentially several connection points + * for this slot. bss_ninfo is how many, + * and bss_infos is a pointer to + * an array pcibr_info_t values (which are + * pointers to pcibr_info structs, stored + * as device_info in connection ponts). + */ + int bss_ninfo; + pcibr_info_h bss_infos; + + /* Temporary Compatibility Macros, for + * stuff that has moved out of bs_slot + * and into the info structure. These + * will go away when their users have + * converted over to multifunction- + * friendly use of bss_{ninfo,infos}. + */ +#define bss_vendor_id bss_infos[0]->f_vendor +#define bss_device_id bss_infos[0]->f_device +#define bss_window bss_infos[0]->f_window +#define bssw_space w_space +#define bssw_base w_base +#define bssw_size w_size + + /* Where is DevIO(x) pointing? */ + /* bssd_space is NONE if it is not assigned. */ + struct { + pciio_space_t bssd_space; + iopaddr_t bssd_base; + } bss_devio; + + /* Shadow value for Device(x) register, + * so we don't have to go to the chip. + */ + bridgereg_t bss_device; + + /* Number of sets on GBR/REALTIME bit outstanding + * Used by Priority I/O for tracking reservations + */ + int bss_pri_uctr; + + /* Number of "uses" of PMU, 32-bit direct, + * and 64-bit direct DMA (0:none, <0: trans, + * >0: how many dmamaps). Device(x) bits + * controlling attribute of each kind of + * channel can't be changed by dmamap_alloc + * or dmatrans if the controlling counter + * is nonzero. dmatrans is forever. + */ + int bss_pmu_uctr; + int bss_d32_uctr; + int bss_d64_uctr; + + /* When the contents of mapping configuration + * information is locked down by dmatrans, + * repeated checks of the same flags should + * be shortcircuited for efficiency. + */ + iopaddr_t bss_d64_base; + unsigned bss_d64_flags; + iopaddr_t bss_d32_base; + unsigned bss_d32_flags; + + /* Shadow information used for implementing + * Bridge Hardware WAR #484930 + */ + int bss_ext_ates_active; + volatile unsigned *bss_cmd_pointer; + unsigned bss_cmd_shadow; + + } bs_slot[8]; + + pcibr_intr_bits_f *bs_intr_bits; + + /* RRB MANAGEMENT + * bs_rrb_fixed: bitmap of slots whose RRB + * allocations we should not "automatically" change + * bs_rrb_avail: number of RRBs that have not + * been allocated or reserved for {even,odd} slots + * bs_rrb_res: number of RRBs reserved for the + * use of the index slot number + * bs_rrb_valid: number of RRBs marked valid + * for the indexed slot number; indexes 8-15 + * are for the virtual channels for slots 0-7. + */ + int bs_rrb_fixed; + int bs_rrb_avail[2]; + int bs_rrb_res[8]; + int bs_rrb_valid[16]; + + struct { + /* Each Bridge interrupt bit has a single XIO + * interrupt channel allocated. + */ + xtalk_intr_t bsi_xtalk_intr; + /* + * We do not like sharing PCI interrrupt lines + * between devices, but the Origin 200 PCI + * layout forces us to do so. + */ + pcibr_intr_list_t bsi_pcibr_intr_list; + pcibr_intr_wrap_t bsi_pcibr_intr_wrap; + int bsi_pcibr_wrap_set; + + } bs_intr[8]; + + xtalk_intr_t bsi_err_intr; + + /* + * We stash away some information in this structure on getting + * an error interrupt. This information is used during PIO read/ + * write error handling. + * + * As it stands now, we do not re-enable the error interrupt + * till the error is resolved. Error resolution happens either at + * bus error time for PIO Read errors (~100 microseconds), or at + * the scheduled timeout time for PIO write errors (~milliseconds). + * If this delay causes problems, we may need to move towards + * a different scheme.. + * + * Note that there is no locking while looking at this data structure. + * There should not be any race between bus error code and + * error interrupt code.. will look into this if needed. + */ + struct br_errintr_info { + int bserr_toutcnt; +#ifdef IRIX + toid_t bserr_toutid; /* Timeout started by errintr */ +#endif + iopaddr_t bserr_addr; /* Address where error occured */ + bridgereg_t bserr_intstat; /* interrupts active at error time */ + } bs_errinfo; + + /* + * PCI Bus Space allocation data structure. + * This info is used to satisfy the callers of pcibr_piospace_alloc + * interface. Most of these users need "large" amounts of PIO + * space (typically in Megabytes), and they generally tend to + * take once and never release.. + * For Now use a simple algorithm to manage it. On allocation, + * Update the _base field to reflect next free address. + * + * Freeing does nothing.. So, once allocated, it's gone for good. + */ + struct br_pcisp_info { + iopaddr_t pci_io_base; + iopaddr_t pci_io_last; + iopaddr_t pci_swin_base; + iopaddr_t pci_swin_last; + iopaddr_t pci_mem_base; + iopaddr_t pci_mem_last; + } bs_spinfo; + + struct bs_errintr_stat_s { + uint32_t bs_errcount_total; + uint32_t bs_lasterr_timestamp; + uint32_t bs_lasterr_snapshot; + } bs_errintr_stat[PCIBR_ISR_MAX_ERRS]; + + /* + * Bridge-wide endianness control for + * large-window PIO mappings + * + * These fields are set to PCIIO_BYTE_SWAP + * or PCIIO_WORD_VALUES once the swapper + * has been configured, one way or the other, + * for the direct windows. If they are zero, + * nobody has a PIO mapping through that window, + * and the swapper can be set either way. + */ + unsigned bs_pio_end_io; + unsigned bs_pio_end_mem; +}; + +#define PCIBR_ERRTIME_THRESHOLD (100) +#define PCIBR_ERRRATE_THRESHOLD (100) + +/* + * pcibr will respond to hints dropped in its vertex + * using the following structure. + */ +struct pcibr_hints_s { + /* ph_host_slot is actually +1 so "0" means "no host" */ + pciio_slot_t ph_host_slot[8]; /* REQ/GNT/INT in use by ... */ + unsigned ph_rrb_fixed; /* do not change RRB allocations */ + unsigned ph_hands_off; /* prevent further pcibr operations */ + rrb_alloc_funct_t rrb_alloc_funct; /* do dynamic rrb allocation */ + pcibr_intr_bits_f *ph_intr_bits; /* map PCI INT[ABCD] to Bridge Int(n) */ +}; + +extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; + +/* + * Number of bridge non-fatal error interrupts we can see before + * we decide to disable that interrupt. + */ +#define PCIBR_ERRINTR_DISABLE_LEVEL 10000 + +/* ===================================================================== + * Bridge (pcibr) state management functions + * + * pcibr_soft_get is here because we do it in a lot + * of places and I want to make sure they all stay + * in step with each other. + * + * pcibr_soft_set is here because I want it to be + * closely associated with pcibr_soft_get, even + * though it is only called in one place. + */ + +#define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) +#define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) + +#endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h new file mode 100644 index 000000000..304d4410b --- /dev/null +++ b/include/asm-ia64/sn/pci/pciio.h @@ -0,0 +1,717 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_PCIIO_H +#define _ASM_SN_PCI_PCIIO_H + +/* + * pciio.h -- platform-independent PCI interface + */ + +#include <asm/sn/ioerror.h> +#include <asm/sn/iobus.h> + + +#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) + +#include <asm/sn/dmamap.h> +#include <asm/sn/alenlist.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int pciio_vendor_id_t; + +#define PCIIO_VENDOR_ID_NONE -1 + +typedef int pciio_device_id_t; + +#define PCIIO_DEVICE_ID_NONE -1 + +#ifdef colin +typedef char pciio_bus_t; /* PCI bus number (0..255) */ +typedef char pciio_slot_t; /* PCI slot number (0..31, 255) */ +typedef char pciio_function_t; /* PCI func number (0..7, 255) */ +#else +typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */ +typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */ +typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */ +#endif + +#define PCIIO_SLOTS ((pciio_slot_t)32) +#define PCIIO_FUNCS ((pciio_function_t)8) + +#define PCIIO_SLOT_NONE ((pciio_slot_t)255) +#define PCIIO_FUNC_NONE ((pciio_function_t)255) + +typedef int pciio_intr_line_t; /* PCI interrupt line(s) */ + +#define PCIIO_INTR_LINE(n) (0x1 << (n)) +#define PCIIO_INTR_LINE_A (0x1) +#define PCIIO_INTR_LINE_B (0x2) +#define PCIIO_INTR_LINE_C (0x4) +#define PCIIO_INTR_LINE_D (0x8) + +typedef int pciio_space_t; /* PCI address space designation */ + +#define PCIIO_SPACE_NONE (0) +#define PCIIO_SPACE_ROM (1) +#define PCIIO_SPACE_IO (2) +/* PCIIO_SPACE_ (3) */ +#define PCIIO_SPACE_MEM (4) +#define PCIIO_SPACE_MEM32 (5) +#define PCIIO_SPACE_MEM64 (6) +#define PCIIO_SPACE_CFG (7) +#define PCIIO_SPACE_WIN0 (8) +#define PCIIO_SPACE_WIN(n) (PCIIO_SPACE_WIN0+(n)) /* 8..13 */ +/* PCIIO_SPACE_ (14) */ +#define PCIIO_SPACE_BAD (15) + +#if 1 /* does anyone really use these? */ +#define PCIIO_SPACE_USER0 (20) +#define PCIIO_SPACE_USER(n) (PCIIO_SPACE_USER0+(n)) /* 20 .. ? */ +#endif + +/* + * PCI_NOWHERE is the error value returned in + * place of a PCI address when there is no + * corresponding address. + */ +#define PCI_NOWHERE (0) + +/* + * Acceptable flag bits for pciio service calls + * + * PCIIO_FIXED: require that mappings be established + * using fixed sharable resources; address + * translation results will be permanently + * available. (PIOMAP_FIXED and DMAMAP_FIXED are + * the same numeric value and are acceptable). + * PCIIO_NOSLEEP: if any part of the operation would + * sleep waiting for resoruces, return an error + * instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are + * the same numeric value and are acceptable). + * PCIIO_INPLACE: when operating on alenlist structures, + * reuse the source alenlist rather than creating a + * new one. (PIOMAP_INPLACE and DMAMAP_INPLACE are + * the same numeric value and are acceptable). + * + * PCIIO_DMA_CMD: configure this stream as a + * generic "command" stream. Generally this + * means turn off prefetchers and write + * gatherers, and whatever else might be + * necessary to make command ring DMAs + * work as expected. + * PCIIO_DMA_DATA: configure this stream as a + * generic "data" stream. Generally, this + * means turning on prefetchers and write + * gatherers, and anything else that might + * increase the DMA throughput (short of + * using "high priority" or "real time" + * resources that may lower overall system + * performance). + * PCIIO_DMA_A64: this device is capable of + * using 64-bit DMA addresses. Unless this + * flag is specified, it is assumed that + * the DMA address must be in the low 4G + * of PCI space. + * PCIIO_PREFETCH: if there are prefetchers + * available, they can be turned on. + * PCIIO_NOPREFETCH: any prefetchers along + * the dma path should be turned off. + * PCIIO_WRITE_GATHER: if there are write gatherers + * available, they can be turned on. + * PCIIO_NOWRITE_GATHER: any write gatherers along + * the dma path should be turned off. + * + * PCIIO_BYTE_STREAM: the DMA stream represents a group + * of ordered bytes. Arrange all byte swapping + * hardware so that the bytes land in the correct + * order. This is a common setting for data + * channels, but is NOT implied by PCIIO_DMA_DATA. + * PCIIO_WORD_VALUES: the DMA stream is used to + * communicate quantities stored in multiple bytes, + * and the device doing the DMA is little-endian; + * arrange any swapping hardware so that + * 32-bit-wide values are maintained. This is a + * common setting for command rings that contain + * DMA addresses and counts, but is NOT implied by + * PCIIO_DMA_CMD. CPU Accesses to 16-bit fields + * must have their address xor-ed with 2, and + * accesses to individual bytes must have their + * addresses xor-ed with 3 relative to what the + * device expects. + * + * NOTE: any "provider specific" flags that + * conflict with the generic flags will + * override the generic flags, locally + * at that provider. + * + * Also, note that PCI-generic flags (PCIIO_) are + * in bits 0-14. The upper bits, 15-31, are reserved + * for PCI implementation-specific flags. + */ + +#define PCIIO_FIXED DMAMAP_FIXED +#define PCIIO_NOSLEEP DMAMAP_NOSLEEP +#define PCIIO_INPLACE DMAMAP_INPLACE + +#define PCIIO_DMA_CMD 0x0010 +#define PCIIO_DMA_DATA 0x0020 +#define PCIIO_DMA_A64 0x0040 + +#define PCIIO_WRITE_GATHER 0x0100 +#define PCIIO_NOWRITE_GATHER 0x0200 +#define PCIIO_PREFETCH 0x0400 +#define PCIIO_NOPREFETCH 0x0800 + +/* Requesting an endianness setting that the + * underlieing hardware can not support + * WILL result in a failure to allocate + * dmamaps or complete a dmatrans. + */ +#define PCIIO_BYTE_STREAM 0x1000 /* set BYTE SWAP for "byte stream" */ +#define PCIIO_WORD_VALUES 0x2000 /* set BYTE SWAP for "word values" */ + +/* + * Interface to deal with PCI endianness. + * The driver calls pciio_endian_set once, supplying the actual endianness of + * the device and the desired endianness. On SGI systems, only use LITTLE if + * dealing with a driver that does software swizzling. Most of the time, + * it's preferable to request BIG. The return value indicates the endianness + * that is actually achieved. On systems that support hardware swizzling, + * the achieved endianness will be the desired endianness. On systems without + * swizzle hardware, the achieved endianness will be the device's endianness. + */ +typedef enum pciio_endian_e { + PCIDMA_ENDIAN_BIG, + PCIDMA_ENDIAN_LITTLE +} pciio_endian_t; + +/* + * Interface to set PCI arbitration priority for devices that require + * realtime characteristics. pciio_priority_set is used to switch a + * device between the PCI high-priority arbitration ring and the low + * priority arbitration ring. + * + * (Note: this is strictly for the PCI arbitrary priority. It has + * no direct relationship to GBR.) + */ +typedef enum pciio_priority_e { + PCI_PRIO_LOW, + PCI_PRIO_HIGH +} pciio_priority_t; + +/* + * handles of various sorts + */ +typedef struct pciio_piomap_s *pciio_piomap_t; +typedef struct pciio_dmamap_s *pciio_dmamap_t; +typedef struct pciio_intr_s *pciio_intr_t; +typedef struct pciio_info_s *pciio_info_t; +typedef struct pciio_piospace_s *pciio_piospace_t; + +/* PIO MANAGEMENT */ + +/* + * A NOTE ON PCI PIO ADDRESSES + * + * PCI supports three different address spaces: CFG + * space, MEM space and I/O space. Further, each + * card always accepts CFG accesses at an address + * based on which slot it is attached to, but can + * decode up to six address ranges. + * + * Assignment of the base address registers for all + * PCI devices is handled centrally; most commonly, + * device drivers will want to talk to offsets + * within one or another of the address ranges. In + * order to do this, which of these "address + * spaces" the PIO is directed into must be encoded + * in the flag word. + * + * We reserve the right to defer allocation of PCI + * address space for a device window until the + * driver makes a piomap_alloc or piotrans_addr + * request. + * + * If a device driver mucks with its device's base + * registers through a PIO mapping to CFG space, + * results of further PIO through the corresponding + * window are UNDEFINED. + * + * Windows are named by the index in the base + * address register set for the device of the + * desired register; IN THE CASE OF 64 BIT base + * registers, the index should be to the word of + * the register that contains the mapping type + * bits; since the PCI CFG space is natively + * organized little-endian fashion, this is the + * first of the two words. + * + * AT THE MOMENT, any required corrections for + * endianness are the responsibility of the device + * driver; not all platforms support control in + * hardware of byteswapping hardware. We anticipate + * providing flag bits to the PIO and DMA + * management interfaces to request different + * configurations of byteswapping hardware. + * + * PIO Accesses to CFG space via the "Bridge" ASIC + * used in IP30 platforms preserve the native byte + * significance within the 32-bit word; byte + * addresses for single byte accesses need to be + * XORed with 3, and addresses for 16-bit accesses + * need to be XORed with 2. + * + * The IOC3 used on IP30, and other SGI PCI devices + * as well, require use of 32-bit accesses to their + * configuration space registers. Any potential PCI + * bus providers need to be aware of this requirement. + */ + +#define PCIIO_PIOMAP_CFG (0x1) +#define PCIIO_PIOMAP_MEM (0x2) +#define PCIIO_PIOMAP_IO (0x4) +#define PCIIO_PIOMAP_WIN(n) (0x8+(n)) + +typedef pciio_piomap_t +pciio_piomap_alloc_f (devfs_handle_t dev, /* set up mapping for this device */ + device_desc_t dev_desc, /* device descriptor */ + pciio_space_t space, /* which address space */ + iopaddr_t pcipio_addr, /* starting address */ + size_t byte_count, + size_t byte_count_max, /* maximum size of a mapping */ + unsigned flags); /* defined in sys/pio.h */ + +typedef void +pciio_piomap_free_f (pciio_piomap_t pciio_piomap); + +typedef caddr_t +pciio_piomap_addr_f (pciio_piomap_t pciio_piomap, /* mapping resources */ + iopaddr_t pciio_addr, /* map for this pcipio address */ + size_t byte_count); /* map this many bytes */ + +typedef void +pciio_piomap_done_f (pciio_piomap_t pciio_piomap); + +typedef caddr_t +pciio_piotrans_addr_f (devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + pciio_space_t space, /* which address space */ + iopaddr_t pciio_addr, /* starting address */ + size_t byte_count, /* map this many bytes */ + unsigned flags); + +typedef caddr_t +pciio_pio_addr_f (devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + pciio_space_t space, /* which address space */ + iopaddr_t pciio_addr, /* starting address */ + size_t byte_count, /* map this many bytes */ + pciio_piomap_t *mapp, /* in case a piomap was needed */ + unsigned flags); + +typedef iopaddr_t +pciio_piospace_alloc_f (devfs_handle_t dev, /* PIO space for this device */ + device_desc_t dev_desc, /* Device descriptor */ + pciio_space_t space, /* which address space */ + size_t byte_count, /* Number of bytes of space */ + size_t alignment); /* Alignment of allocation */ + +typedef void +pciio_piospace_free_f (devfs_handle_t dev, /* Device freeing space */ + pciio_space_t space, /* Which space is freed */ + iopaddr_t pci_addr, /* Address being freed */ + size_t size); /* Size freed */ + +/* DMA MANAGEMENT */ + +typedef pciio_dmamap_t +pciio_dmamap_alloc_f (devfs_handle_t dev, /* set up mappings for this device */ + device_desc_t dev_desc, /* device descriptor */ + size_t byte_count_max, /* max size of a mapping */ + unsigned flags); /* defined in dma.h */ + +typedef void +pciio_dmamap_free_f (pciio_dmamap_t dmamap); + +typedef iopaddr_t +pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources */ + paddr_t paddr, /* map for this address */ + size_t byte_count); /* map this many bytes */ + +typedef alenlist_t +pciio_dmamap_list_f (pciio_dmamap_t dmamap, /* use these mapping resources */ + alenlist_t alenlist, /* map this address/length list */ + unsigned flags); + +typedef void +pciio_dmamap_done_f (pciio_dmamap_t dmamap); + +typedef iopaddr_t +pciio_dmatrans_addr_f (devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + paddr_t paddr, /* system physical address */ + size_t byte_count, /* length */ + unsigned flags); /* defined in dma.h */ + +typedef alenlist_t +pciio_dmatrans_list_f (devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + alenlist_t palenlist, /* system address/length list */ + unsigned flags); /* defined in dma.h */ + +typedef void +pciio_dmamap_drain_f (pciio_dmamap_t map); + +typedef void +pciio_dmaaddr_drain_f (devfs_handle_t vhdl, + paddr_t addr, + size_t bytes); + +typedef void +pciio_dmalist_drain_f (devfs_handle_t vhdl, + alenlist_t list); + +/* INTERRUPT MANAGEMENT */ + +typedef pciio_intr_t +pciio_intr_alloc_f (devfs_handle_t dev, /* which PCI device */ + device_desc_t dev_desc, /* device descriptor */ + pciio_intr_line_t lines, /* which line(s) will be used */ + devfs_handle_t owner_dev); /* owner of this intr */ + +typedef void +pciio_intr_free_f (pciio_intr_t intr_hdl); + +typedef int +pciio_intr_connect_f (pciio_intr_t intr_hdl, /* pciio intr resource handle */ + intr_func_t intr_func, /* pciio intr handler */ + intr_arg_t intr_arg, /* arg to intr handler */ + void *thread); /* intr thread to use */ + +typedef void +pciio_intr_disconnect_f (pciio_intr_t intr_hdl); + +typedef devfs_handle_t +pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ + +/* CONFIGURATION MANAGEMENT */ + +typedef void +pciio_provider_startup_f (devfs_handle_t pciio_provider); + +typedef void +pciio_provider_shutdown_f (devfs_handle_t pciio_provider); + +typedef int +pciio_reset_f (devfs_handle_t conn); /* pci connection point */ + +typedef int +pciio_write_gather_flush_f (devfs_handle_t dev); /* Device flushing buffers */ + +typedef pciio_endian_t /* actual endianness */ +pciio_endian_set_f (devfs_handle_t dev, /* specify endianness for this device */ + pciio_endian_t device_end, /* endianness of device */ + pciio_endian_t desired_end); /* desired endianness */ + +typedef pciio_priority_t +pciio_priority_set_f (devfs_handle_t pcicard, + pciio_priority_t device_prio); + +typedef uint64_t +pciio_config_get_f (devfs_handle_t conn, /* pci connection point */ + unsigned reg, /* register byte offset */ + unsigned size); /* width in bytes (1..4) */ + +typedef void +pciio_config_set_f (devfs_handle_t conn, /* pci connection point */ + unsigned reg, /* register byte offset */ + unsigned size, /* width in bytes (1..4) */ + uint64_t value); /* value to store */ + +typedef int +pciio_error_devenable_f (devfs_handle_t pconn_vhdl, int error_code); + +typedef pciio_slot_t +pciio_error_extract_f (devfs_handle_t vhdl, + pciio_space_t *spacep, + iopaddr_t *addrp); + +/* + * Adapters that provide a PCI interface adhere to this software interface. + */ +typedef struct pciio_provider_s { + /* PIO MANAGEMENT */ + pciio_piomap_alloc_f *piomap_alloc; + pciio_piomap_free_f *piomap_free; + pciio_piomap_addr_f *piomap_addr; + pciio_piomap_done_f *piomap_done; + pciio_piotrans_addr_f *piotrans_addr; + pciio_piospace_alloc_f *piospace_alloc; + pciio_piospace_free_f *piospace_free; + + /* DMA MANAGEMENT */ + pciio_dmamap_alloc_f *dmamap_alloc; + pciio_dmamap_free_f *dmamap_free; + pciio_dmamap_addr_f *dmamap_addr; + pciio_dmamap_list_f *dmamap_list; + pciio_dmamap_done_f *dmamap_done; + pciio_dmatrans_addr_f *dmatrans_addr; + pciio_dmatrans_list_f *dmatrans_list; + pciio_dmamap_drain_f *dmamap_drain; + pciio_dmaaddr_drain_f *dmaaddr_drain; + pciio_dmalist_drain_f *dmalist_drain; + + /* INTERRUPT MANAGEMENT */ + pciio_intr_alloc_f *intr_alloc; + pciio_intr_free_f *intr_free; + pciio_intr_connect_f *intr_connect; + pciio_intr_disconnect_f *intr_disconnect; + pciio_intr_cpu_get_f *intr_cpu_get; + + /* CONFIGURATION MANAGEMENT */ + pciio_provider_startup_f *provider_startup; + pciio_provider_shutdown_f *provider_shutdown; + pciio_reset_f *reset; + pciio_write_gather_flush_f *write_gather_flush; + pciio_endian_set_f *endian_set; + pciio_priority_set_f *priority_set; + pciio_config_get_f *config_get; + pciio_config_set_f *config_set; + + /* Error handling interface */ + pciio_error_devenable_f *error_devenable; + pciio_error_extract_f *error_extract; +} pciio_provider_t; + +/* PCI devices use these standard PCI provider interfaces */ +extern pciio_piomap_alloc_f pciio_piomap_alloc; +extern pciio_piomap_free_f pciio_piomap_free; +extern pciio_piomap_addr_f pciio_piomap_addr; +extern pciio_piomap_done_f pciio_piomap_done; +extern pciio_piotrans_addr_f pciio_piotrans_addr; +extern pciio_pio_addr_f pciio_pio_addr; +extern pciio_piospace_alloc_f pciio_piospace_alloc; +extern pciio_piospace_free_f pciio_piospace_free; +extern pciio_dmamap_alloc_f pciio_dmamap_alloc; +extern pciio_dmamap_free_f pciio_dmamap_free; +extern pciio_dmamap_addr_f pciio_dmamap_addr; +extern pciio_dmamap_list_f pciio_dmamap_list; +extern pciio_dmamap_done_f pciio_dmamap_done; +extern pciio_dmatrans_addr_f pciio_dmatrans_addr; +extern pciio_dmatrans_list_f pciio_dmatrans_list; +extern pciio_dmamap_drain_f pciio_dmamap_drain; +extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain; +extern pciio_dmalist_drain_f pciio_dmalist_drain; +extern pciio_intr_alloc_f pciio_intr_alloc; +extern pciio_intr_free_f pciio_intr_free; +extern pciio_intr_connect_f pciio_intr_connect; +extern pciio_intr_disconnect_f pciio_intr_disconnect; +extern pciio_intr_cpu_get_f pciio_intr_cpu_get; +extern pciio_provider_startup_f pciio_provider_startup; +extern pciio_provider_shutdown_f pciio_provider_shutdown; +extern pciio_reset_f pciio_reset; +extern pciio_write_gather_flush_f pciio_write_gather_flush; +extern pciio_endian_set_f pciio_endian_set; +extern pciio_priority_set_f pciio_priority_set; +extern pciio_config_get_f pciio_config_get; +extern pciio_config_set_f pciio_config_set; +extern pciio_error_devenable_f pciio_error_devenable; +extern pciio_error_extract_f pciio_error_extract; + +/* Widgetdev in the IOERROR structure is encoded as follows. + * +---------------------------+ + * | slot (7:3) | function(2:0)| + * +---------------------------+ + * Following are the convenience interfaces to get at form + * a widgetdev or to break it into its constituents. + */ + +#define PCIIO_WIDGETDEV_SLOT_SHFT 3 +#define PCIIO_WIDGETDEV_SLOT_MASK 0x1f +#define PCIIO_WIDGETDEV_FUNC_MASK 0x7 + +#ifdef IRIX +#define pciio_widgetdev_create(slot,func) \ + ((slot) << PCIIO_WIDGETDEV_SLOT_SHFT + (func)) +#else +#define pciio_widgetdev_create(slot,func) \ + (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func)) +#endif + +#define pciio_widgetdev_slot_get(wdev) \ + (((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK) + +#define pciio_widgetdev_func_get(wdev) \ + ((wdev) & PCIIO_WIDGETDEV_FUNC_MASK) + + +/* Generic PCI card initialization interface + */ + +extern int +pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */ + pciio_device_id_t device_id, /* card's device number */ + char *driver_prefix, /* driver prefix */ + unsigned flags); + +extern void +pciio_error_register (devfs_handle_t pconn, /* which slot */ + error_handler_f *efunc, /* function to call */ + error_handler_arg_t einfo); /* first parameter */ + +extern void pciio_driver_unregister(char *driver_prefix); + +typedef void pciio_iter_f(devfs_handle_t pconn); /* a connect point */ + +extern void pciio_iterate(char *driver_prefix, + pciio_iter_f *func); + +/* Interfaces used by PCI Bus Providers to talk to + * the Generic PCI layer. + */ +extern devfs_handle_t +pciio_device_register (devfs_handle_t connectpt, /* vertex at center of bus */ + devfs_handle_t master, /* card's master ASIC (pci provider) */ + pciio_slot_t slot, /* card's slot (0..?) */ + pciio_function_t func, /* card's func (0..?) */ + pciio_vendor_id_t vendor, /* card's vendor number */ + pciio_device_id_t device); /* card's device number */ + +extern void +pciio_device_unregister(devfs_handle_t connectpt); + +extern pciio_info_t +pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */ + devfs_handle_t master, /* card's master ASIC (pci provider) */ + pciio_slot_t slot, /* card's slot (0..?) */ + pciio_function_t func, /* card's func (0..?) */ + pciio_vendor_id_t vendor, /* card's vendor number */ + pciio_device_id_t device); /* card's device number */ + +extern void +pciio_device_info_free(pciio_info_t pciio_info); + +extern devfs_handle_t +pciio_device_info_register( + devfs_handle_t connectpt, /* vertex at center of bus */ + pciio_info_t pciio_info); /* details about conn point */ + +extern void +pciio_device_info_unregister( + devfs_handle_t connectpt, /* vertex at center of bus */ + pciio_info_t pciio_info); /* details about conn point */ + + +extern int pciio_device_attach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */ +extern int pciio_device_detach(devfs_handle_t pcicard); /* vertex created by pciio_device_register */ + +/* + * Generic PCI interface, for use with all PCI providers + * and all PCI devices. + */ + +/* Generic PCI interrupt interfaces */ +extern devfs_handle_t pciio_intr_dev_get(pciio_intr_t pciio_intr); +extern devfs_handle_t pciio_intr_cpu_get(pciio_intr_t pciio_intr); + +/* Generic PCI pio interfaces */ +extern devfs_handle_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap); +extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap); +extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap); +extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); +extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); +extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); + +#ifdef IRIX +#ifdef USE_PCI_PIO +extern uint8_t pciio_pio_read8(volatile uint8_t *addr); +extern uint16_t pciio_pio_read16(volatile uint16_t *addr); +extern uint32_t pciio_pio_read32(volatile uint32_t *addr); +extern uint64_t pciio_pio_read64(volatile uint64_t *addr); +extern void pciio_pio_write8(uint8_t val, volatile uint8_t *addr); +extern void pciio_pio_write16(uint16_t val, volatile uint16_t *addr); +extern void pciio_pio_write32(uint32_t val, volatile uint32_t *addr); +extern void pciio_pio_write64(uint64_t val, volatile uint64_t *addr); +#else /* !USE_PCI_PIO */ +__inline uint8_t pciio_pio_read8(volatile uint8_t *addr) +{ + return *addr; +} +__inline uint16_t pciio_pio_read16(volatile uint16_t *addr) +{ + return *addr; +} +__inline uint32_t pciio_pio_read32(volatile uint32_t *addr) +{ + return *addr; +} +__inline uint64_t pciio_pio_read64(volatile uint64_t *addr) +{ + return *addr; +} +__inline void pciio_pio_write8(uint8_t val, volatile uint8_t *addr) +{ + *addr = val; +} +__inline void pciio_pio_write16(uint16_t val, volatile uint16_t *addr) +{ + *addr = val; +} +__inline void pciio_pio_write32(uint32_t val, volatile uint32_t *addr) +{ + *addr = val; +} +__inline void pciio_pio_write64(uint64_t val, volatile uint64_t *addr) +{ + *addr = val; +} +#endif /* USE_PCI_PIO */ +#endif + +/* Generic PCI dma interfaces */ +extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); + +/* Register/unregister PCI providers and get implementation handle */ +extern void pciio_provider_register(devfs_handle_t provider, pciio_provider_t *pciio_fns); +extern void pciio_provider_unregister(devfs_handle_t provider); +extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider); + +/* Generic pci slot information access interface */ +extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); +extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); +extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); +extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); +extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); +extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); +extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); +extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info); +extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info); +extern devfs_handle_t pciio_info_master_get(pciio_info_t pciio_info); +extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info); +extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info); +extern error_handler_f *pciio_info_efunc_get(pciio_info_t); +extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t); +extern pciio_space_t pciio_info_bar_space_get(pciio_info_t, int); +extern iopaddr_t pciio_info_bar_base_get(pciio_info_t, int); +extern size_t pciio_info_bar_size_get(pciio_info_t, int); +extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); +extern size_t pciio_info_rom_size_get(pciio_info_t); + +extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); +extern int pciio_dma_enabled(devfs_handle_t); + +#ifdef __cplusplus +}; +#endif +#endif /* C or C++ */ +#endif /* _ASM_SN_PCI_PCIIO_H */ diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h new file mode 100644 index 000000000..00daf01d8 --- /dev/null +++ b/include/asm-ia64/sn/pci/pciio_private.h @@ -0,0 +1,100 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 2000 by Colin Ngam + */ +#ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H +#define _ASM_SN_PCI_PCIIO_PRIVATE_H + +#ifdef colin +#include <ksys/xthread.h> +#endif + +/* + * pciio_private.h -- private definitions for pciio + * PCI drivers should NOT include this file. + */ + +#ident "sys/PCI/pciio_private: $Revision: 1.13 $" + +/* + * All PCI providers set up PIO using this information. + */ +struct pciio_piomap_s { + unsigned pp_flags; /* PCIIO_PIOMAP flags */ + devfs_handle_t pp_dev; /* associated pci card */ + pciio_slot_t pp_slot; /* which slot the card is in */ + pciio_space_t pp_space; /* which address space */ + iopaddr_t pp_pciaddr; /* starting offset of mapping */ + size_t pp_mapsz; /* size of this mapping */ + caddr_t pp_kvaddr; /* kernel virtual address to use */ +}; + +/* + * All PCI providers set up DMA using this information. + */ +struct pciio_dmamap_s { + unsigned pd_flags; /* PCIIO_DMAMAP flags */ + devfs_handle_t pd_dev; /* associated pci card */ + pciio_slot_t pd_slot; /* which slot the card is in */ +}; + +/* + * All PCI providers set up interrupts using this information. + */ + +struct pciio_intr_s { + unsigned pi_flags; /* PCIIO_INTR flags */ + devfs_handle_t pi_dev; /* associated pci card */ + device_desc_t pi_dev_desc; /* override device descriptor */ + pciio_intr_line_t pi_lines; /* which interrupt line(s) */ + intr_func_t pi_func; /* handler function (when connected) */ + intr_arg_t pi_arg; /* handler parameter (when connected) */ +#ifdef IRIX + thd_int_t pi_tinfo; /* Thread info (when connected) */ +#endif + cpuid_t pi_mustruncpu; /* Where we must run. */ + int pi_irq; /* IRQ assigned */ + int pi_cpu; /* cpu assigned */ +}; + +/* PCIIO_INTR (pi_flags) flags */ +#define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */ +#define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ + +/* + * Each PCI Card has one of these. + */ + +struct pciio_info_s { + char *c_fingerprint; + devfs_handle_t c_vertex; /* back pointer to vertex */ + pciio_bus_t c_bus; /* which bus the card is in */ + pciio_slot_t c_slot; /* which slot the card is in */ + pciio_function_t c_func; /* which func (on multi-func cards) */ + pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */ + pciio_device_id_t c_device; /* PCI card "device" code */ + devfs_handle_t c_master; /* PCI bus provider */ + arbitrary_info_t c_mfast; /* cached fastinfo from c_master */ + pciio_provider_t *c_pops; /* cached provider from c_master */ + error_handler_f *c_efunc; /* error handling function */ + error_handler_arg_t c_einfo; /* first parameter for efunc */ + + struct { /* state of BASE regs */ + pciio_space_t w_space; + iopaddr_t w_base; + size_t w_size; + } c_window[6]; + + unsigned c_rbase; /* EXPANSION ROM base addr */ + unsigned c_rsize; /* EXPANSION ROM size (bytes) */ + + pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ +}; + +extern char pciio_info_fingerprint[]; +#endif /* _ASM_SN_PCI_PCIIO_PRIVATE_H */ |