diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1994-12-01 08:00:00 +0000 |
|---|---|---|
| committer | <ralf@linux-mips.org> | 1994-12-01 08:00:00 +0000 |
| commit | 90ecc248e200fee448001248dde0ca540dd3ef64 (patch) | |
| tree | a3fe89494ce63b4835f0f9cf5c45e74cde88252b /include/asm-mips/cachectl.h | |
| parent | 1513ff9b7899ab588401c89db0e99903dbf5f886 (diff) | |
Import of Linux/MIPS 1.1.68
Diffstat (limited to 'include/asm-mips/cachectl.h')
| -rw-r--r-- | include/asm-mips/cachectl.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h new file mode 100644 index 000000000..167727c97 --- /dev/null +++ b/include/asm-mips/cachectl.h @@ -0,0 +1,32 @@ +/* + * include/asm-mips/cachectl.h + * + * Written by Ralf Baechle, + * Copyright (C) 1994 by Waldorf GMBH + * + * Defines for Risc/OS compatible cacheflush systemcall + */ +#ifndef _ASM_MIPS_CACHECTL +#define _ASM_MIPS_CACHECTL + +/* + * cachectl.h -- defines for MIPS cache control system calls + */ + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#define CACHELINES 512 /* number of cachelines */ + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +extern int sys_cacheflush(void *addr, int nbytes, int cache); + +#endif +#endif +#endif /* _ASM_MIPS_CACHECTL */ |