diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2000-12-13 19:43:03 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2000-12-13 19:43:03 +0000 |
| commit | 8ecd5b87ddd65325753a989b80a64c60294adbab (patch) | |
| tree | 0c0d0030d4b7e4468e507cdbce8121c3bdc28cfd /include/asm-mips/gt64120.h | |
| parent | ce0560ca5cf571fea993f6ea6f4ea19699824b92 (diff) | |
First batch of PMC Ocelot CP7000 patches.
Diffstat (limited to 'include/asm-mips/gt64120.h')
| -rw-r--r-- | include/asm-mips/gt64120.h | 57 |
1 files changed, 55 insertions, 2 deletions
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h index d706870d7..1ef59a11d 100644 --- a/include/asm-mips/gt64120.h +++ b/include/asm-mips/gt64120.h @@ -25,14 +25,19 @@ */ #define GT_CPU_OFS 0x000 +/* + * Interrupt Registers + */ #define GT_INTRCAUSE_OFS 0xc18 #define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ #define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ #define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ + #define GT_PCI0_CFGADDR_OFS 0xcf8 #define GT_PCI0_CFGDATA_OFS 0xcfc #define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ #define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ + #define GT_SDRAM_BM_OFS 0x478 #define GT_SDRAM_ADDRDECODE_OFS 0x47c #define GT_SDRAM_B0_OFS 0x44c @@ -40,8 +45,6 @@ #define GT_SDRAM_CFG_OFS 0x448 #define GT_SDRAM_OPMODE_OFS 0x474 -#define GT_ISD_OFS 0x068 - #define GT_SCS10LD_OFS 0x008 #define GT_SCS10HD_OFS 0x010 #define GT_SCS32LD_OFS 0x018 @@ -54,6 +57,7 @@ #define GT_PCI0IOHD_OFS 0x050 #define GT_PCI0M0LD_OFS 0x058 #define GT_PCI0M0HD_OFS 0x060 +#define GT_ISD_OFS 0x068 #define GT_PCI0M1LD_OFS 0x080 #define GT_PCI0M1HD_OFS 0x088 #define GT_PCI1IOLD_OFS 0x090 @@ -111,10 +115,59 @@ #define GT_TC3_OFS 0x85C #define GT_TC_CONTROL_OFS 0x864 +/* + * I2O Support Registers + */ +#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 +#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 +#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 +#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c +#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 +#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 +#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 +#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 +#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 +#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 +#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c + +#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 +#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 +#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 +#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c +#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 +#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 +#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 +#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c +#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 +#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 +#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 +#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 +#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 +#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 +#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 +#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 +#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 +#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c +#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 +#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 +#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 +#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c /* * Register encodings */ + #define GT_CPU_WR_SHF 16 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) #define GT_CPU_WR_BIT GT_CPU_WR_MSK |