diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 1997-09-12 23:25:15 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 1997-09-12 23:25:15 +0000 |
| commit | 0c9824af05b775b18bff274f3a07d174c718bae1 (patch) | |
| tree | 4890f863496f44ef27897017d7c1ac3feadba770 /include/asm-mips/mipsregs.h | |
| parent | e8ad72aaaa65930e821f72c4b568219f8392ba7b (diff) | |
- Set caching mode for KSEG0 to cached-noncoherent for all machines.
On some MIPS boxes the firmware doesn't do that for us.
- We still had two unprotected loads in the sys_sigrestore(2). Use
__get_user().
- Handle QED-style L1 caches != 16kb per cache correctly.
- Protect the cacheflush instructions for the signal trampoline
just like the loads in __get_user(). Otherwise the following
code will result in a nice "Can not handle kernel paging request"
message:
#include <signal.h>
static void hurz(void)
{
}
main()
{
signal(SIGSEGV, hurz);
/* Chainsaw the stack pointer ... */
asm("move $29,%0" : :"r"(0x70000000));
*(int *) 8 = 0;
}
With the fix applied I still get the error message. The cause of
this problem is that gas produces an __ex_table section with wrong
contents. Oh well, how good that I have a nice working post 2.8.1
binutils version at home in good ol' Germany ...
Diffstat (limited to 'include/asm-mips/mipsregs.h')
| -rw-r--r-- | include/asm-mips/mipsregs.h | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index bf2340305..0dcd71a44 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -5,8 +5,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * + * $Id: mipsregs.h,v 1.2 1997/09/12 22:25:34 ralf Exp $ */ #ifndef __ASM_MIPS_MIPSREGS_H #define __ASM_MIPS_MIPSREGS_H @@ -160,7 +162,7 @@ * Manipulate the status register. * Mostly used to access the interrupt bits. */ -#define BUILD_SET_CP0(name,register) \ +#define __BUILD_SET_CP0(name,register) \ extern __inline__ unsigned int \ set_cp0_##name(unsigned int change, unsigned int new) \ { \ @@ -175,8 +177,9 @@ set_cp0_##name(unsigned int change, unsigned int new) \ return res; \ } -BUILD_SET_CP0(status,CP0_STATUS) -BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(status,CP0_STATUS) +__BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(config,CP0_CONFIG) #endif /* defined (__LANGUAGE_ASSEMBLY__) */ @@ -298,9 +301,18 @@ BUILD_SET_CP0(cause,CP0_CAUSE) /* * Bits in the coprozessor 0 config register. */ -#define CONFIG_DB (1 << 4) -#define CONFIG_IB (1 << 5) -#define CONFIG_SC (1 << 17) +#define CONFIG_CM_CACHABLE_NO_WA 0 +#define CONFIG_CM_CACHABLE_WA 1 +#define CONFIG_CM_UNCACHED 2 +#define CONFIG_CM_CACHABLE_NONCOHERENT 3 +#define CONFIG_CM_CACHABLE_CE 4 +#define CONFIG_CM_CACHABLE_COW 5 +#define CONFIG_CM_CACHABLE_CUW 6 +#define CONFIG_CM_CACHABLE_ACCELERATED 7 +#define CONFIG_CM_CMASK 7 +#define CONFIG_DB (1 << 4) +#define CONFIG_IB (1 << 5) +#define CONFIG_SC (1 << 17) /* * R10000 performance counter definitions. |