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authorRalf Baechle <ralf@linux-mips.org>2000-06-20 01:06:27 +0000
committerRalf Baechle <ralf@linux-mips.org>2000-06-20 01:06:27 +0000
commit68a1cd72aca3ddd79de33703a1760887e3dbe164 (patch)
tree128a3c32d6b8883de3fff9a70fd7a68dc643aa55 /include/asm-mips/mipsregs.h
parent6d403070f28cd44860fdb3a53be5da0275c65cf4 (diff)
R3000 cache handling. flush_icache_page now actually flushes
something.
Diffstat (limited to 'include/asm-mips/mipsregs.h')
-rw-r--r--include/asm-mips/mipsregs.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 23ed82cfd..f7a29a81f 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -234,6 +234,8 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
#define ST0_UX 0x00000020
#define ST0_SX 0x00000040
#define ST0_KX 0x00000080
+#define ST0_DE 0x00010000
+#define ST0_CE 0x00020000
/*
* Bitfields in the R[23]000 cp0 status register.
@@ -245,6 +247,8 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
#define ST0_IEO 0x00000010
#define ST0_KUO 0x00000020
/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC 0x00010000
+#define ST0_SWC 0x00020000
/*
* Bits specific to the R4640/R4650
@@ -273,8 +277,6 @@ __BUILD_SET_CP0(config,CP0_CONFIG)
#define STATUSF_IP6 (1 << 14)
#define STATUSB_IP7 15
#define STATUSF_IP7 (1 << 15)
-#define ST0_DE 0x00010000
-#define ST0_CE 0x00020000
#define ST0_CH 0x00040000
#define ST0_SR 0x00100000
#define ST0_BEV 0x00400000