diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2001-02-22 04:12:11 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2001-02-22 04:12:11 +0000 |
| commit | c884ada29ead83a2777c4097489dc4db26419624 (patch) | |
| tree | 98bc5e293200d703cb6d9b47ab6f052dfaba0041 /include/asm-mips/mipsregs.h | |
| parent | 95b2d612949328e196b54c7569324e22f98c6ec0 (diff) | |
Support for Phillips PDAs.
Diffstat (limited to 'include/asm-mips/mipsregs.h')
| -rw-r--r-- | include/asm-mips/mipsregs.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9d3f591f6..c5d8ac759 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -294,6 +294,39 @@ __BUILD_SET_CP0(config,CP0_CONFIG) #define ST0_DL (1 << 24) /* + * Bitfields in the R3912 CP0 Configuration Register 3 + */ +#define R3912_CONF_ICS_SHIFT 19 +#define R3912_CONF_ICS_MASK 0x00380000 +#define R3912_CONF_ICS_1KB 0x00000000 +#define R3912_CONF_ICS_2KB 0x00080000 +#define R3912_CONF_ICS_4KB 0x00100000 +#define R3912_CONF_ICS_8KB 0x00180000 +#define R3912_CONF_ICS_16KB 0x00200000 + +#define R3912_CONF_DCS_SHIFT 16 +#define R3912_CONF_DCS_MASK 0x00070000 +#define R3912_CONF_DCS_1KB 0x00000000 +#define R3912_CONF_DCS_2KB 0x00010000 +#define R3912_CONF_DCS_4KB 0x00020000 +#define R3912_CONF_DCS_8KB 0x00030000 +#define R3912_CONF_DCS_16KB 0x00040000 + +#define R3912_CONF_CWFON 0x00004000 +#define R3912_CONF_WBON 0x00002000 +#define R3912_CONF_RF_SHIFT 10 +#define R3912_CONF_RF_MASK 0x00000c00 +#define R3912_CONF_DOZE 0x00000200 +#define R3912_CONF_HALT 0x00000100 +#define R3912_CONF_LOCK 0x00000080 +#define R3912_CONF_ICE 0x00000020 +#define R3912_CONF_DCE 0x00000010 +#define R3912_CONF_IRSIZE_SHIFT 2 +#define R3912_CONF_IRSIZE_MASK 0x0000000c +#define R3912_CONF_DRSIZE_SHIFT 0 +#define R3912_CONF_DRSIZE_MASK 0x00000003 + +/* * Status register bits available in all MIPS CPUs. */ #define ST0_IM 0x0000ff00 |