Optimized cache flushing on r10k/o200s, assuming processor handles

VCEs in hardwire, and system guarantees io coherency. Only need to
do cache flushes for icache coherency.

1 files changed, 24 insertions, 0 deletions

diff --git a/include/asm-mips64/pgtable.h b/include/asm-mips64/pgtable.h
index a5b5b977d..c40380569 100644
--- a/include/asm-mips64/pgtable.h
+++ b/include/asm-mips64/pgtable.h
@@ -34,6 +34,8 @@ extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page)
 extern void (*_flush_page_to_ram)(struct page * page);
 
 #define flush_cache_all()		do { } while(0)
+
+#ifndef CONFIG_CPU_R10000
 #define flush_cache_mm(mm)		_flush_cache_mm(mm)
 #define flush_cache_range(mm,start,end)	_flush_cache_range(mm,start,end)
 #define flush_cache_page(vma,page)	_flush_cache_page(vma, page)
@@ -47,6 +49,28 @@ do {									\
 	addr = page_address(page);					\
 	_flush_cache_page(vma, addr);					\
 } while (0)                                                              
+#else /* !CONFIG_CPU_R10000 */
+/*
+ * Since the r10k handles VCEs in hardware, most of the flush cache
+ * routines are not needed. Only the icache on a processor is not
+ * coherent with the dcache of the _same_ processor, so we must flush
+ * the icache so that it does not contain stale contents of physical
+ * memory. No flushes are needed for dma coherency, since the o200s 
+ * are io coherent. The only place where we might be overoptimizing 
+ * out icache flushes are from mprotect (when PROT_EXEC is added).
+ */
+extern void andes_flush_icache_page(unsigned long);
+#define flush_cache_mm(mm)		do { } while(0)
+#define flush_cache_range(mm,start,end)	do { } while(0)
+#define flush_cache_page(vma,page)	do { } while(0)
+#define flush_page_to_ram(page)		do { } while(0)
+#define flush_icache_range(start, end)	_flush_cache_l1()
+#define flush_icache_page(vma, page)					\
+do {									\
+	if ((vma)->vm_flags & VM_EXEC)					\
+		andes_flush_icache_page(page_address(page));		\
+} while (0)
+#endif /* !CONFIG_CPU_R10000 */
 
 /*
  * The foll cache flushing routines are MIPS specific.